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A High Step-Down DC-DC Converter with Reduced Inductor Current Ripple

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DOI: 10.1109/TIA.2020.3046703

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 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 57, NO. 2, MARCH/APRIL 2021
A High Step-Down DC–DC Converter With Reduced
Inductor Current Ripple and Low Voltage Stress
Mriganka Biswas , Student Member, IEEE, Somanath Majhi , Senior Member, IEEE,
and Harshal B. Nemade , Senior Member, IEEE
Abstract—This article presents a buck converter with a large
step-down voltage conversion ratio, reduced ripple in inductor
current and low semiconductor voltage stress. The proposed con-
verter produces a lower output voltage at a sufficiently higher duty
ratio compared to the conventional buck converter. The step-down
voltage conversion ratio is modified by a series-parallel transition of
two identical capacitors of a switch-capacitor cell. Two parallelly
placed switches and two cross-connected identical capacitors are
utilized to design the cell. An extra inductor is placed at the input
side to oppose the sudden change in input current due to the
series-parallel transition of the two identical capacitors. Therefore,
two inductors are required to design the converter. These two
inductors are coupled directly. The modified voltage conversion
ratio reduces the ripple in inductor currents and output voltage.
Direct coupling between the two inductors helps to further reduce
the ripple in inductor currents and output voltage. The operating
principle, analysis of ripple in inductor currents, and ripple in
output voltage are discussed. The analysis of small-signal modeling
is carried out and a voltage mode PI-controller is designed to
enable the closed-loop operation. Finally, the proposed converter
is implemented in hardware and the performance of the proposed
converter is verified experimentally.
Index Terms—Buck converter, coupled-inductor, current ripple,
step-down ratio, voltage ripple.
I. INTRODUCTION
HE dc–dc buck converter is extensively used due to its
T simple structure and cost-effectiveness in a variety of
nonisolated type applications such as battery chargers, volt-
age regulator modules for microprocessors, telecommunication,
power systems, LED drivers, and automotive applications [1]–
[4]. Conventional buck converters can be made to yield very
low output voltage by operating at extremely small duty cycle
which leads to high power losses and low overall efficiency. In
Manuscript received June 15, 2020; revised September 27, 2020 and Novem-
ber 18, 2020; accepted November 29, 2020. Date of publication December
22, 2020; date of current version March 17, 2021. This work was supported
by the Ministry of Electronics and Information Technology, Government of
India. Paper 2020-IPCC-0929.R2, presented at the 2020 IEEE International
Conference on Power Electronics, Smart Grid and Renewable Energy, Cochin,
India, Jan 2–4, and approved for publication in the IEEE TRANSACTIONS ON
INDUSTRY APPLICATIONS by the Industrial Power Converter Committee of the
IEEE Industry Applications Society. (Corresponding author: Mriganka Biswas.)
The authors are with the Department of Electronics and Electrical Engineer-
ing, Indian Institute of Technology Guwahati, Guwahati 781039, India (e-mail:
b.mriganka@iitg.ac.in; smajhi@iitg.ac.in; harshal@iitg.ac.in).
Color versions of one or more figures in this article are available at https:
//doi.org/10.1109/TIA.2020.3046703.
Digital Object Identifier 10.1109/TIA.2020.3046703
0093-9994 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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1559
addition, it results in high ripple in inductor current as well as in
output voltage which is not desirable; therefore achieving high
step-down conversion ratio with lower ripple values is a topic of
interest among the contemporary researchers.
Large inductance is commonly used to reduce the ripple
in buck converters [5]. However, it deteriorates the dynamic
response of the converter other than being voluminous and
heavy [6], [7]. For high voltage to very low voltage conver-
sion, though a two-stage cascaded buck converter is a possible
solution [8], the overall efficiency decreases and the converter
unit becomes bulkier. Several attempts to design single-stage
buck converter with a larger step-down ratio have been re-
ported. In [9], a buck converter is presented to achieve a wider
conversion ratio by using a switched capacitor network. A
transformer-less high step-down dc–dc converter is introduced
in [10]. However, both the design use a large number of active
and passive components resulting in increased overall cost and
size of the converters. A resonant high step-down ratio buck
converter is designed by using a coupled inductor and one reso-
nant energy-transferring capacitor in [11] with a very complex
topology. In addition, the effect of the coupled inductor on ripple
improvement is not discussed. A wider conversion ratio for a
bidirectional buck/boost converter is reported in [12] with a
large number of active and passive components. A nonisolated
buck converter is presented in [13] to achieve a high step-down
conversion ratio by using a transformer and an energy transfer-
ring capacitor; however, the switches are subjected to high input
voltage stress. Another high step-down converter introduced
in [14] has the demerit of a requirement of magnetic cores
and components. In addition, the voltage step-down ratio of the
converter depends on the turns ratio of a coupled inductor. A
buck module with low source current ripple is introduced in [15].
This topology uses several semiconductor devices; however, it
could not modify the conversion ratio.
A high step-down conversion ratio buck converter with a
dual winding coupled inductor is proposed in this article. The
proposed converter uses a switched capacitor cell to accomplish
a larger step-down conversion ratio. The converter is proposed
to achieve the following:
1) a larger step-down conversion ratio to avoid the narrow
duty cycle for high to very low voltage conversion;
2) reduction of ripple in input current, inductor current, and
output voltage;
3) reduction of voltage stresses in the semiconductor devices;
4) improvement of efficiency.
 1560 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 57, NO. 2, MARCH/APRIL 2021

operating in CCM. The Li − and L represent the two windings

of the coupled inductor. The input voltage vin is applied to the
Li -winding of the coupled inductor. The rLi is the parasitic
of the Li -winding. Thereafter, a switch-capacitor cell is used
and it combines two switches S1 and S2 placed in parallel and
two cross-connected identical capacitors C1 and C2 . The diode
D is placed parallel to the switch-capacitor cell followed by
the L-winding of the coupled inductor. Both the switches turn
ON and OFF simultaneously. When both S1 and S2 are ON, the
diode D is in reverse bias. Therefore, the two identical capacitors
Fig. 1. Proposed high step-down dc–dc converter with coupled inductor. become parallel to each other and discharge their energy to the
load side. When the switches are OFFsimultaneously, the diode D
is in forward bias because of which the two identical capacitors
The conversion ratio of the proposed converter is independent charge in series with the Li -winding. Thus, the proposed con-
of the turns ratio of the coupled inductor. The modified step- verter produces lower output voltage at a sufficiently large duty
down conversion ratio reduces the ripple in inductor currents and cycle compared to the conventional buck converter. To oppose
output voltage which is further improved by the use of coupled the sudden change in the input current due to the series-parallel
inductor as its windings are directly coupled. transition of the two identical capacitors, the Li -winding is
In our previous work [16], the operating principle of the placed at the input side. Cf represents the output capacitor
proposed converter was explained in detail. The function of and rCf is the parasitic. vo is the output voltage at output load
a coupled inductor to reduce the ripple in current flowing resistance R. The rL and rLi are negligible as rL , rLi  R.
through the inductor branches and the ripple in output voltage
was discussed. In addition, analyzes of voltage stresses of the A. Generalized Equations of Coupled Inductor
semiconductor devices, power losses, and efficiency were also The generalized inductive voltages vLi and vL across the Li
included. The present article further extends the work and makes and L windings of the coupled inductor, respectively, are as
the following contributions: follows:
1) minimum inductance value for the coupled inductor
diLi diL
branches is derived to operate the proposed converter in v Li = Li ±M (1)
dt dt
continuous conduction mode (CCM);
2) power losses and efficiency are analyzed by considering diL diLi
vL = L ±M . (2)
the switching losses; dt dt
3) small-signal modeling of the proposed converter with the Here, iLi and iL represent the currents flowing through the
coupled inductor is carried out. Thereafter, the voltage to Li and L windings, respectively. Since the two windings of
duty ratio power stage transfer function is determined; the coupled inductor have identical inductances √ L = Li . The
4) a voltage mode PI controller is designed to enable the mutual inductance M is defined as M = k Li L where k is
closed-loop control; the coupling factor. The windings will be directly coupled or
5) closed-loop stability is examined; inversely coupled depending upon whether k ∈ (0, 1) or k ∈
6) experimental results of the closed-loop control systems (0, −1), respectively. The leakage inductance (Lr ) is defined by
are presented. Lr = L(1 − k 2 ). The two inductor branches are coupled directly
The article is organized as follows. Section II explains the to reduce the ripple in current and output voltage for the proposed
operation principle. Ripple current in inductor branches and converter. Therefore, over a time period of Ts , (1) and (2) can
input current are discussed in Sections III and IV, respectively. be expressed as
Section V discusses the minimum inductance value of the cou- 
 Ts  Ts vL k LLi  Ts
pled inductor. The output voltage ripple and CCM/discontinuous v Li
conduction mode (DCM) boundary load conditions are provided diLi = dt − dt (3)
0 (1 − k 2 )Li 0 (1 − k 2 )Li 0
in Sections VI and VII, respectively. The voltage and current 
stresses are provided in Section VIII. Section IX discusses power  Ts  Ts v L k L  T
vL i Li s

losses and efficiency. Small-signal modeling and control scheme diL = dt − dt. (4)
0 (1 − k 2 )L 0 (1 − k 2 )L 0
are provided in Sections X and XI, respectively. Section XII
describes the simulation work. Experimental set-up and results B. Switching Modes
are provided in Section XIII. Finally, Section XIV concludes the
article. The converter, whose duty ratio is denoted by α, has one
ON-state and one OFF-state, as both the switches S1 and S2
turn ON and OFF simultaneously over a time period of Ts as
II. OPERATING PRINCIPLE
shown in Fig. 2. Here, vS1,2 represents drain to source voltage
The proposed high step-down buck converter, shown in for the switches, whereas vD is the diode voltage stress. In the
Fig. 1 combines a coupled inductor and a switch-capacitor cell duration 0 < t < αTs , both the inductor currents, iLi through

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 BISWAS et al.: HIGH STEP-DOWN DC-DC CONVERTER WITH REDUCED INDUCTOR CURRENT RIPPLE 1561

Fig. 4. Circuit configuration in the OFF-state.

⎡ M RrCf
⎤
−(M +L) MR
0 LLi −M 2 (LLi −M 2 )(R+rCf ) (LLi −M 2 )(R+rCf ) ⎥
⎢
⎢ 1 −1 ⎥
⎢ 2C 0 0 ⎥
⎢ 2C ⎥
A1= ⎢ −Li RrCf ⎥,
Fig. 2. Idealized waveform of the proposed ripple improved converter. ⎢0 Li +M −Li R ⎥
⎢ LLi −M 2 (LLi −M 2 )(R+rCf ) (LLi −M )(R+rCf ) ⎥
2
⎣ ⎦
R −1
0 0 Cf (R+rCf ) RCf (R+rCf )

T
L −M
B1 = 0 0 ,
LLi − M 2 LLi − M 2
 RrCf

R
Z1 = 0 0 R+rCf R+rCf

.
2) OFF-state (αTs < t ≤ Ts ): In this interval, both the
switches are OFF and the diode D is in forward bias as shown
Fig. 3. Circuit configuration in the ON-state.
in Fig. 4. Therefore, the identical capacitors are in series with
Li -winding. The resultant voltage across the two capacitors
becomes vC + vC = 2vC .
The inductor voltage equations are as follows:
Li -winding and iL through L-winding increase. In the next
duration, αTs < t < Ts , both the inductor currents decrease. diLi diL
v L i = Li +M = vin − 2vC (9)
The switching operations are described below. dt dt
1) ON-state (0 < t ≤ αTs ): In this switching period, the S1 diL diLi
and S2 are simultaneously ON as shown in Fig. 3. The diode D vL = L +M = −vCf − rCf iCf . (10)
dt dt
is in reverse bias.Therefore, the two identical capacitors become
parallel to each other and the voltage across the capacitors The state-space representation of the OFF-state is as follows:
becomes vC . ẋ(t) = A2 x(t) + B2 vin (t) (11)
The voltages vLi and vL are expressed as
y(t) = Z2 x(t) (12)
diLi diL
v L i = Li +M = vin − vC (5) where
dt dt ⎡ ⎤
−2L M RrCf MR
diL diLi 0
vL = L +M = vC − vCf − rcf iCf (6) ⎢ LLi −M 2 (LLi −M 2 )(R+rCf ) (LLi −M 2 )(R+rCf ) ⎥
dt dt ⎢1 ⎥
⎢C 0 0 0 ⎥
⎢ ⎥
where vCf is the voltage across Cf and iCf is the current flowing A2 = ⎢ −Li RrCf ⎥,
⎢0 2M −Li R ⎥
through Cf . ⎢ LLi −M 2 (LLi −M 2 )(R+rCf ) (LLi −M 2 )(R+rCf ) ⎥
The state vectors are defined as x(t) = [iLi vC iL vCf ]T and ⎣ ⎦
R −1
the output vector as y(t) = vo . The state-space representation 0 0 Cf (R+rCf ) RCf (R+rCf )
of the ON-state is as follows:

T
L −M
ẋ(t) = A1 x(t) + B1 vin (t) (7) B1 = 0 0 ,
LLi − M 2 LLi − M 2
y(t) = Z1 x(t) (8) 
RrCf R
Z2 = 0 0 R+rCf R+rCf .
where

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 1562 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 57, NO. 2, MARCH/APRIL 2021

C. Step-Down Voltage Conversion Ratio as follows:

At ideal case, by using (5) and (9), the volt-second balance (1 − α)Ts αvin
iL (αTs ) = + iL (0). (19)
(VSB) equation of the Li -winding is expressed as follows: (2 − α)(1 + k)L

(vin − vC )α + (vin − 2vC )(1 − α) = 0 In the next switching period (αTs < t < Ts ), by substituting (9)
and (10) into (4), the instantaneous current iL (Ts ) is derived as
vC 1 follows:
= . (13)
vin 2−α (1 − α)Ts αvin
iL (Ts ) = iL (αTs ) − . (20)
In the next stage, by using (6) and (10), the VSB equation of the (2 − α)(1 + k)L
L-winding is written as
Therefore, the ripple in inductor current of L-winding is as
(vC − vo )α − vo (1 − α) = 0 follows:
vo = αvC . (14) (1 − α)αTs
ΔiL = iL (αTs ) − iL (0) = vin
(2 − α)(1 + k)L
Therefore, from (13) and (14), the voltage conversion ratio of
(1 − α)Ts
the proposed converter is determined as = vo . (21)
(1 + k)L
vo α
= . (15)
vin 2−α IV. RIPPLE IN INPUT CURRENT
The voltage conversion ratio of the conventional buck con- The duty ratio and ripple in input current of existing conven-
verter is vo /vin = α. Therefore, the proposed converter produces tional buck converter are considered as αb and Δib . The input
less output voltage at the same duty ratio as compared to the ripple current of conventional buck is as follows [17]:
conventional buck converter. The comparison plots of the dc
input-to-output voltage conversion ratio between the proposed (1 − αb )Ts
Δib = vo . (22)
and conventional buck converters along with other reported buck L
topologies are provided in Fig. 24(a) in the results section. The input ripple current (Δiin ) of the proposed buck converter
is as follows:
III. RIPPLE CURRENT IN INDUCTOR BRANCHES (1 − α)Ts
Δiin = ΔiLi = vo . (23)
By considering the L = Li , the ripple currents in the L and Li (1 + k)Li
windings of the coupled inductor are determined at ideal case. While both converter has the same input and output voltage, the
The effect of coupling factor k on ripple reduction is analyzed. relation between two duty ratios is expressed as follows:
2αb
A. Ripple Current in Li -Winding α= . (24)
1 + αb
During the interval (0 < t < αTs ), the instantaneous inductor
Considering that the both the converter has the same inductance
current iLi (αTs ) is derived by substituting (5) and (6) into (3)
value (L = Li ), the relation between Δib and Δiin is as follows:
as follows:
(1 − α)Ts αvin Δiin (1 − α)
iLi (αTs ) = + iLi (0). (16) = . (25)
(2 − α)(1 + k)Li Δib (1 + k)(1 − αb )
Substituting the (24) into (25), the following relation is achieved:
In the subsequent interval (αTs < t < Ts ), the instantaneous
current iLi (Ts ) is determined by substituting (9) and (10) into Δiin 1
= wherek ∈ {0, 1} . (26)
(3) as follows: Δib (1 + k)(1 + αb )
(1 − α)Ts αvin Therefore, from (26), it can be said that the proposed converter
iLi (Ts ) = iLi (αTs ) − . (17)
(2 − α)(1 + k)Li has less input ripple current than the conventional one. The use
of coupled inductor causes further ripple improvement in input
Therefore, the ripple current of Li -winding is as follows: current as shown in (26).
(1 − α)αTs
ΔiLi = iLi (αTs ) − iLi (0) = vin V. MINIMUM INDUCTANCE VALUE OF COUPLED INDUCTOR
(2 − α)(1 + k)Li
(1 − α)Ts The average input current iin is determined by using (18) as
= vo . (18) follows:
(1 + k)Li
ΔiLi (1 − α)Ts
iin = = vo . (27)
B. Ripple Current in L-Winding 2 2(1 + k)Li
In the duration (0 < t < αTs ), the instantaneous current The output current io is the same as the load current iR . Now, at
iL (αTs ) is determined by substituting (5) and (6) into (4) lossless condition vin iin = vo io , the input current can be written

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 BISWAS et al.: HIGH STEP-DOWN DC-DC CONVERTER WITH REDUCED INDUCTOR CURRENT RIPPLE 1563

Fig. 5. Plot of ripple in iL versus duty ratio α at different values of coupling Fig. 6. Plot of normalized load resistance at CCM/DCM boundary.
factor k for equal input voltage.

VII. CCM/DCM BOUNDARY LOAD CONDITION

by using (15) as
In this section, the load value at the boundary between the
α CCM and DCM is derived. The average input current (Iin ) is the
iin = io . (28)
2−α same as the current through the Li −winding and calculated by
Therefore, by equating (27) and (28), for a given load R, we get using (16) and (17) as
iLi (0) + iLi (αTs )+ iL (αTs ) + iLi (Ts )
vo 2Li α(1 + k) Iin = α+ i (1 − α)
R= = . (29) 2 2
io (2 − α)(1 − α)Ts
(1 − α)Ts vo
Thus, the minimum inductance value can be written as = + iLi (0). (33)
2(1 + k)Li
(2 − α)(1 − α)Ts R At the boundary condition (iLi (0) = iLi (Ts ) = 0), the Iin is
min {Li } = . (30)
2α(1 + k)
(1 − α)vo
Both the windings of the coupled inductor are considered to have Iin = . (34)
2(1 + k)Li fs
equal inductance value (Li = L).
α
The average input current can be expressed by Iin = 2−α io .
α
Therefore, by substituting Iin = 2−α io into (34), the boundary
VI. RIPPLE IN OUTPUT VOLTAGE
load RLB is derived as follows:
In every cycle Ts , the output filter capacitor stores charge and
the maximum increment (ΔQ) of the charge is calculated as vo 2(1 + k)Li fs α
RLB = = . (35)
follows: io (1 − α)(2 − α)
Ts ΔiL
ΔiL Ts The normalized boundary load RLB /(2(1 + k)Li fs ) as a func-
ΔQ = 2 2
= . (31) tion of duty ratio α for the proposed buck converter is shown in
2 8
Fig. 6.
Therefore, the peak to peak ripple voltage Δvo in the proposed
converter is
VIII. VOLTAGE AND CURRENT STRESSES
ΔQ (1 − α)Ts 2 αvin The voltage stresses of the switches and the diode are de-
Δvo = = . (32)
Cf 8(1 + k)(2 − α)LCf termined by neglecting the ripple in capacitor voltages. The
switching voltage stresses vS1 and vS2 , respectively, of the
The output ripple voltage of the conventional buck converter is
(1−α)Ts 2
switches S1 and S2 are provided as follows:
Δvo = ΔQ Cf = 8LCf αvin .
vin
In Fig. 5, the ripple ΔiL of the proposed converter for dif- v S = v S1 = v S2 = v C = . (36)
ferent values of coupling factor k is compared with that of the 2−α
conventional buck converter for the same input voltage. It is The diode voltage stress vD is as follows:
observed from this figure that the proposed converter has less
vin
ripple than the conventional converter in the entire range of α. As vD = vC = . (37)
2−α
expected, the ripple decreases with increase in coupling factor.
If the proposed converter utilizes two independent inductors The current stresses of the switches and the diode due to the
instead of a coupled inductor, i.e., k = 0, the proposed converter current flow is determined by neglecting the ripple in inductor
still offers less ripple than conventional buck converter. current. The approximation of the maximum switching current

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 1564 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 57, NO. 2, MARCH/APRIL 2021

TABLE I TABLE II
COMPARISON OF PARAMETERS BETWEEN THE PROPOSED AND CONVENTIONAL ANALYSIS OF POWER LOSS
BUCK CONVERTERS

and the diode current are as follows:


io , for 0 < t ≤ αTs
i S 1 = iS 2 = (38)
0, for αTs < t ≤ Ts

0, for 0 < t ≤ αTs
iD = (39)
io , for αTs < t ≤ Ts
where io is the output load current. By using (21), the maximum
current stresses of the switches (iSmax ) and the diode current
stress (iDmax ) are determined as follows:
ΔiL (1 − α)Ts αvin
iSmax = iDmax = io + = io + (40)
2 2(1 + k)(2 − α)L
iS1rms and iS2rms are the root mean square (rms) currents flowing
through the switches S1 and S2 , respectively, and are as follows:

 Ts Theoretical efficiency due to change of (a) α and (b) load R.
1 √ Fig. 7.
iS1rms = iS2rms = i2S1 dt = io α. (41)
Ts 0
The rms current iDrms flowing through the diode is The output power Po can be written as Po = vo io = i2o R. The

 Ts expressions of loss analysis are provided in Table II.
1 √
iDrms = i2D dt = io 1 − α. (42) The rDS , Cs , rD , and vD represent, respectively, the ON-state
Ts 0 resistance, output capacitance of the switches, diode conduction
The average current, iD , flowing through the diode is resistance and diode forward bias voltage as provided in Table II.
 Thus, the efficiency, η, is derived as follows by using the loss
 Ts
1 expressions provided in Table II:
iD = iD dt = io (1 − α). (43)
Ts 0
η=
In Table I, the parameters of the proposed buck converter are
compared with the conventional buck converter for the same 1
α 2f C v 2 v (1−α) rL i
.
+ rD (1−α) ) + rRL
2r α 2
input and output voltage condition. 1+ (ds)
R + s v2o C R + f d vo + R ( 2−α
o
(44)
IX. ANALYSIS OF POWER LOSS AND EFFICIENCY
The power loss is mainly due to the semiconductor devices The theoretical efficiencies of the proposed buck converter due
and the resistances of inductors in the proposed converter. The to the variation of duty ratio (α) and load resistance (R) are
loss analysis is carried out by assuming all the capacitors ideal. shown in Fig. 7(a) and (b), respectively.

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 BISWAS et al.: HIGH STEP-DOWN DC-DC CONVERTER WITH REDUCED INDUCTOR CURRENT RIPPLE 1565

X. SMALL SIGNAL MODELING TABLE III

COEFFICIENTS OF TRANSFER FUNCTIONS Gvg (s) AND Gvα (s)
A. Average State-Space Matrices
The general average state-space equations are written as fol-
lows:

ẋ(t) = Aavg x(t) + Bavg vin (t) (45)

y(t) = Zavg x(t). (46)

The average state matrices of (45) and (46) are as follows:

Aavg = (A1 − A2 )α + A2
⎡ α(L−M )−2L M RrCf M RrCf ⎤
0 LLi −M 2 (LLi −M 2 )(R+rCf ) (LLi −M 2 )(R+rCf )
⎢ ⎥
⎢ 2−α 0 −α
0 ⎥
⎢ ⎥
=⎢ 2C 2M +α(Li −M ) 2C
−LiRrCf −Li RrCf ⎥
⎢ 0 ⎥
⎣ LLi −M 2 (LLi −M 2 )(R+rCf ) (LLi −M 2 )(R+rCf ) ⎦
R −1
0 0 Cf (R+rC ) RCf (R+rCf )
f

(47)

T
L −M
Bavg = (B1 − B2 )α + B2 = 0 0
LLi − M 2 LLi − M 2
(48)
 RrC
From (55), the dc input-to-output voltage ratio can be written as
R
Zavg = (Z1 − Z2 )α + Z2 = 0 0 R+rCf R+rC .
f f V Cf Vo α
(49) = = . (56)
Vin Vin 2−α
Now, considering a perturbation v̂in (t) in the steady state in- Plots of the dc input-to-output voltage conversion ratio between
put voltage Vin , the input voltage is vin (t) = Vin + v̂in (t). This the proposed and conventional buck converters with other re-
perturbation in vin affects the steady-state values of inductor ported buck topologies are provided in Fig. 24(a) in the results
currents and capacitor voltages. If the instantaneous state vec- section.
tor x(t) and output vo (t) are x(t) = X + x̂(t) and vo (t) =
Vo + v̂o (t), respectively, the state-space equation with the per- C. Power-Stage Transfer Functions
turbation can be written as follows:
The input-to-output voltage transfer function (Gvg (s)) can be
˙
Ẋ + x̂(t) = Aav (X + x̂(t)) + Bav (Vin + v̂in (t)) (50) determined by using (45) to (49) as follows:

Vo + v̂o (t) = Zav (X + x̂(t)). v̂o (s)

(51) Gvg (s) = = Zav (sI − Aav )−1 Bav
v̂in (s)
This perturbation also affects the nominal duty cycle α that be-
−n3 s3 − n2 s2 + n1 s + n0
comes α(t) + α̂(t). Substituting it into (47) to (49), the average = . (57)
state-space matrices are expressed as follows: b4 s 4 + b 3 s 3 + b 2 s 2 + b 1 s + b0
The coefficients of the denominator of Gvg (s) are provided in
Aavg = (A1 − A2 )(α(t) + α̂(t)) + A2 (52) M RrC
Table III. The numerators of Gvg (s) are n3 = (LL −M 2 )(R+r
f
)
,
i Cf
Bavg = (B1 − B2 )(α(t) + α̂(t)) + B2 (53) (2−α)αM RrC
n2 = MR
(LLi −M 2 )(R+rC )Cf
, n1 = f
2(LLi −M 2 )(R+rC )C
, n0 =
Zavg = (Z1 − Z2 )(α(t) + α̂(t)) + Z2 . (54) α(2−α)R
f f
. Since the coefficients of the numerator
2(LLi −M 2 )(R+rC )CCf
f
are negative, there is a zero on the right-half of the s-plane.
B. Steady-State Analysis Therefore, Gvg (s) becomes nonminimum phase in nature.
Under ideal condition, the parasitics rL , rLi , and rCf are Fig. 8 shows the responses of the transfer function of the
neglected as rL , rLi , rCf << R and the steady-state values of Gvg (s) for different values of α. The Gvg (s) is tested with a
the state variables are step-signal of amplitude equal to vin = 20 V. The undershoot in
the responses of the proposed buck validates the nonminimum
X = [ILi VC IL VCf ]T = −Aav −1 Bav Vin phase behavior. The responses of the Gvg (s) of the proposed

T converter are compared with Gvg (s) of the conventional buck
α2 Vin Vin αVin αVin
= . (55) converter [18] which is not a nonminimum phase system and
R(2 − α)2 2 − α 2R(2 − α) 2 − α its response has no undershoot.

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 1566
Fig. 8. Step response of transfer function Gvg (s) for the uncompensated
proposed buck converter and conventional buck converter at different α values.
TABLE IV
CIRCUIT PARAMETERS CONSIDERED FOR CCM OPERATION
By using (45) to (55), the voltage to duty ratio transfer function
Gvα (s) is derived as follows:
v̂o (s)
Gvα (s) = = Zav (sI − Aav )−1 [(A1 − A2 )X
α̂(s)
+ (B1 − B2 )Vin ] + (Z1 − Z2 )X.
By using (58), the following voltage to duty ratio transfer func-
tion is derived:
a3 s 3 + a2 s 2 + a1 s + a0
Gvα (s) = . (59)
b4 s 4 + b 3 s 3 + b 2 s 2 + b 1 s + b0
The coefficients of Gvα (s) in terms of RLC-parameters are
provided in Table III. By substituting the parameter values
provided in Table IV, the coefficients of Gvα (s) are deter-
mined. The coefficients of numerator are a3 = 9.7559 × 103 ,
a2 = 1.2267 × 108 , a1 = 1.5731 × 1012 , a0 = 2.3890 × 1016 .
The coefficient of denominator are b4 = 1, b3 = 2141, b2 =
1.459 × 108 , b1 = 1.832 × 1011 , b0 = 1.529 × 1015 .
The bode diagram of Gvα (s) is provided in Fig. 9. The gain
margin and the phase margin of the transfer function are -15 dB
and −150◦ , respectively. A PI controller is designed in the
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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 57, NO. 2, MARCH/APRIL 2021
Fig. 9. Bode diagrams of Gvα (s) with and without PI controller.
Fig. 10. Block diagram representation of closed-loop system.
voltage mode framework to make the closed-loop system stable
and is described in the following section.
XI. CONTROL SCHEME
The block diagram representation of the closed-loop system of
the proposed converter is shown in Fig. 10. In the voltage mode
control framework a PI controller is designed and is defined as
Ki
Gc (s) = Kp + . (60)
s
The coefficients of the controller Gc (s) are Kp = 0.001205 and
Ki = 25. Fig. 9 shows the bode diagram of the uncompensated
(Gvα (s)) and compensated plant (Gc (s) ∗ Gvα (s)). The gain
(58) and phase margins of the compensated plant are 11.8 dB and
89.8◦ , respectively. The closed-loop zeros are z1 = −1.37 ×
104 , z2 = −2.07 × 104 , z3,4 = 6.00 × 102 ± i1.33 × 104 . The
closed-loop poles are s1 = −3.86 × 102 , s2,3 = −425.19 ±
i1.153 × 104 , s4,5 = −458.05 ± i3.38 × 103 . All the closed-
loop poles are on left half of the s-plane. Therefore, the closed-
loop system is stable.
XII. SIMULATION RESULTS
The MATLAB-Simscape platform is used to carry out the
simulation work for the proposed converter using the parameters
given in Table IV. At α = 0.40 and Vin = 20 V, the steady-state
output voltages of the proposed and conventional buck convert-
ers are 4.9 and 7.9 V, respectively, as shown in Fig. 11. The
simulation result of the proposed buck converter validates the
step-down conversion ratio given in (15). Thus, the proposed
 BISWAS et al.: HIGH STEP-DOWN DC-DC CONVERTER WITH REDUCED INDUCTOR CURRENT RIPPLE 1567

Fig. 11. Simulation results of the output voltages of the proposed and conven-
tional buck converters at α = 0.40 and vin = 20 V.

Fig. 13. Ripple for conventional buck converter and proposed buck converter
with k = 0 and k = 0.5. (a) Inductor current iL and (b) output voltage Vo .

Fig. 12. Voltage stress of switches and diodes for α = 0.40.

buck converter produces a lower output voltage at the same duty

cycle. Both the converters have a 0.1 V steady-state error.
Fig. 12 shows the voltage stress vS1,2 = vin /(2 − α) = 12.5
V and the diode stress vD = 12.5 V at α = 0.40. Therefore, it
can be said that the stresses of the semiconductor devices are
less than vin i.e., 20 V. The effects of voltage conversion ratio
and coupling factor on ripple reduction in iL and vo are shown
in Fig. 13(a) and (b), respectively. The conventional and the
proposed buck converters are simulated in equal input–output
voltage condition. Therefore, for α = 0.40, the required duty
ratio for the conventional buck is αb = α/(2 − α) = 0.25. The
ΔiL and Δvo of the conventional buck converter are 424.8 mA
and 89.5 mV, respectively. The ΔiL of the proposed buck
converter with k = 0 is 339.5 mA and it is 226.3 mA when
k = 0.5. The Δvo of the proposed buck with k = 0 is 71.6 mV
and it is 47.8 mV when k = 0.5.

XIII. EXPERIMENTAL SET-UP AND RESULTS
The schematic circuit diagram of the closed-loop control of
the proposed converter is shown in Fig. 14.
To validate the mathematical expressions and simulation
results, the proposed converter is designed by the parame-
ters given in Table IV and the setup is shown in Fig. 15.
The switches S1 and S2 are implemented by power MOS-
FETs IRF540 N and the diode D is implemented by
Fig. 14. Schematic circuit of the closed-loop system of the proposed converter.
NTST30100SG/NFK03TS30100SG. Two FOD3180 optocou-
pler gate driver ICs are used.
The coupled inductor is designed by two U/C type ferrite core
as shown in Fig. 15. The flux density Bmax of the ferrite core
is 0.3 Tesla. Both the windings are identical having a maximum
current rating (Ipk ) of 8 A. The magnetic cross-section area

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 1568
Fig. 15. Experimental set-up of the proposed converter.
Fig. 16. Ripple in inductor currents iLi and iL for α = 0.40 and k = 0.
(Ae ) of the core is Ae = 2.4 cm2 . The turns number (N ) can
LI
be determined by the equation N = BmaxpkAe [19]. Therefore, the
turns number are calculated as N = 20.
A. Ripple Improvement
Initially, two single inductors, i.e., coupling factor k = 0 are
used to test the proposed converter. For α = 0.40, ΔiLi in Li
and ΔiL in L are 400 mA as observed in Fig. 16. The ON-
state duration of iL and iLi is defined by ΔT = αTs = 0.4 ×
(1/50 000) = 8 μs.
Next, a dual-winding coupled inductor with coupling factor
k = 0.5 is used to test the proposed converter. The ripple in
input current i.e. ripple current in Li -winding is ΔiLi = 300
mA at α = 0.40 as shown in Fig. 17. The ripple current in
L-winding is ΔiL = 300 mA as shown in Fig. 17. Therefore,
the proposed converter with coupled inductor has better ripple
reduction performance.
The voltage stresses of switches and diode are vs = vD =
12.5 V as shown in Fig. 18 for α = 0.40. The inductive voltages
vLi and vL are shown in Fig. 18. Fig. 17 and 18 resemble
the idealized waveform provided in Fig. 2. The output voltage
Vo of the proposed converter at α = 0.40 is 5 V as observed
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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 57, NO. 2, MARCH/APRIL 2021
Fig. 17. Ripple in inductor currents iLi and iL for α = 0.40 and k = 0.5.
Fig. 18. Experimental results of vD , vS , vLi , and vL for α = 0.40.
in Fig. 19(a). The ripple in output voltage is measured and
found to be 50 mV. Fig. 19(b) shows the steady-state output
voltages for different values of α. These results validate the
voltage conversion ratio derived in (15) and are consistent with
the simulated steady-state response shown in Fig. 8.
The experimental results of efficiency versus duty ratio and
load for the proposed converter with the coupled inductor are
shown in Fig. 20(a) and (b), respectively.
A maximum efficiency of 93.5 % is achieved at α = 0.55.
The experimental efficiencies are compared with the efficiencies
of the conventional buck converter. Plot of power loss versus
load for the proposed converter is shown in Fig. 21. Power loss
increases with increase in load current as the load resistance
decreases.
 BISWAS et al.: HIGH STEP-DOWN DC-DC CONVERTER WITH REDUCED INDUCTOR CURRENT RIPPLE
Fig. 19. Output voltages of the proposed converter. (a) Vo = 5 V for α = 0.40
and k = 0.5. (b) Steady-state Vo values for different values of α.
Fig. 20. Plots of experimental efficiency versus the variation in (a) α and (b)
load R for conventional and proposed buck converters.
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1569
Fig. 21. Plot of power loss versus load R for the proposed converter.
Fig. 22. Experimental results for reference voltage change on (a) Vo and (b)
iL .
B. Closed-Loop Performance
In Fig. 22(a), output reference voltage Vref f is increased from
5 to 9 V and decreased from 9 to 7 V. The output does not show
any peak overshoot and it follows the Vref f . The load value is
R = 5.33 Ω. The change of iL due to reference voltage change
is shown in Fig. 22(b) and it follows the reference change.
A total of 50% load change is carried out to investigate the
sensitivity to load variation. Despite of 50% load change, the
output voltage follows Vref f as shown in Fig. 23(a). The change
of input current i.e., the current through the Li winding is shown
and it is observed that iLi reaches 0.25 to 0.5 A when the load is
changed from 5 to 2.5 Ω. Thereafter, the iLi comes back to the
previous state when the load is increased from 2.5 to 5 Ω. The
load current for 50% load change is shown in Fig. 23(b). Output
load current increases from 1 to 2 A when the load is reduced
 1570 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 57, NO. 2, MARCH/APRIL 2021

TABLE V
COMPARISONS AMONG THE EXISTING AND THE PROPOSED STEP-DOWN CONVERTERS

 Not provided in the references.

Fig. 23. Experimental results of (a) iLi and (b) load current for 50% load Fig. 24. Comparison plots based on the theoretical expressions of (a) voltage
change. gain and (b) voltage stress against the duty ratio α, for the proposed, conven-
tional, and reported buck converters.

from 5 to 2.5 Ω and decreases from 2 to 1 A when the load is

increased from 2.5 to 5 Ω.
A comparison of the proposed step-down converter with re-
ported step-down topologies is carried out in Table V. Apart from
the step-down ratios of the converters reported in [11]– [13],
the coupled inductor does not help in improving the ripple in
current and output voltage in these topologies. These converters
use more number of switches. The voltage conversion ratio of
the converter presented in [11] depends upon the ratio of leakage
inductance Lr to magnetizing inductance Lm . The step-down
conversion ratio of the converters presented in [20] and [21] is
less than the proposed converter. A comparison plot for voltage
conversion ratio is shown in Fig. 24(a) by considering n = 1.
A comparison of voltage stress is shown in Fig. 24(b). The
switches of these converters suffer high input voltage stress.
Whereas, the proposed converter has voltage stress less than the
input voltage vin and it is possible to use switches with lower volt-
age rating to implement the proposed converter. In addition, the
proposed converter utilizes fewer active components compared
to the converters reported in [20]–[23]. The proposed converter
is less bulky as it utilizes a dual-winding coupled inductor.
XIV. CONCLUSION
In this article, a transformerless buck converter with large
voltage step-down ratio has been designed where the conversion
ratio is independent of the turns ratio of the dual-winding cou-
pled inductor. By comparing the proposed buck converter with
the conventional one, it is seen that the former produces less

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 BISWAS et al.: HIGH STEP-DOWN DC-DC CONVERTER WITH REDUCED INDUCTOR CURRENT RIPPLE
output voltage than the latter under the same condition. Hence,
the proposed converter is suitable for applications requiring
large step-down ratio while avoiding a narrow duty cycle to
get a lower output voltage. Moreover, in case of the proposed
topology, the coupled inductor reduces the ripples in currents
through the inductors and in output voltage. It is also found that
the voltage stresses of the semiconductor devices are less than
the input voltage in this topology which has shown a maximum
experimental efficiency of 93.5%. Small-signal modeling of
the proposed converter with coupled inductor has been carried
out and a voltage mode PI-controller is designed to investigate
the closed-loop performance. Closed-loop experiment shows a
stable performance of the converter without any overshoot under
a step-change in reference voltage and 50% load change. The
intended general application of this converter can be in the field
of battery chargers, solar chargers, PCs, and laptops.
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Mriganka Biswas (Student Member, IEEE) received
the B.Tech. degree in electrical engineering from the
West Bengal University of Technology, West Ben-
gal, India, in 2012, the M.E. degree in electrical
engineering from the Birla Institute of Technology
Mesra, Ranchi, India, in 2014. Presently, he is work-
ing toward the Ph.D. degree in power electronics
and control with the Department of Electronics and
Electrical Engineering, Indian Institute of Technol-
ogy Guwahati, Guwahati, India.
He was a Post-graduate (M.E.) Project Fellow with
Variable Energy Cyclotron Centre, Kolkata, India, during 2013–2014. His
research interests include dc–dc converter topology, swicthed-capacitor cell,
diode-capacitor cell, coupled inductor, control of dc–dc power converters.
Somanath Majhi (Senior Member, IEEE) received
the D.Phil. degree in control systems engineering
from Sussex University, Brighton, U.K.
He is currently a Professor with the Department of
Electronics and Electrical Engineering, Indian Insti-
tute of Technology Guwahati, Guwahati, India. He
has published and presented more than 170 research
papers in reputed national and international journals
and conferences. His research interests include re-
lay control systems, design of automatic controllers,
model identification, and applications of control
theory.
Dr. Majhi has been awarded the Commonwealth Scholarship and the Alexan-
der von Humboldt Research Fellowship for his doctoral and postdoctoral re-
search programmes, respectively. He is a Life Member of Systems Society of
India and Indian Society for Technical Engineers.
Harshal B. Nemade (Senior Member, IEEE) re-
ceived the B.E. degree in instrumentation engineering
from the College of Engineering, Pune, India in 1989,
the M.Tech. degree in electronics design and technol-
ogy from the Indian Institute of Science, Bangalore,
India, in 1992, and the Ph.D. degree in electrical
engineering from the Indian Institute of Technology,
Bombay, India, in 2000.
He is currently a Professor with the Department of
Electronics and Electrical Engineering, Indian Insti-
tute of Technology Guwahati, Guwahati, India. His
research interests include systems design and integration, and instrumentation.