IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 13, NO.
2, MAY 2000
A Simple and Efficient Measurement Method for
Characterizing Capacitance Matrix of Multilayer
Interconnection in VLSI
Tetsuhisa Mido, Hiroshi Ito, and Kunihiro Asada, Member, IEEE
Abstract—A compact new test structure for direct extraction of
components of the capacitance matrix for multilayer interconnec-
tions is presented. In this new method, each capacitive component
in integrated structures is separately and directly obtained from
measurement, and the total pads are kept to eight, independent
of the size of the target matrix. As a result of evaluation of mea-
surement errors caused by the asymmetry of structures, this new
method can measure components of capacitance matrix with a pre-
cision of femto-farad order.
Index Terms—Capacitance extraction method, capacitance ma-
trix, multilayer interconnection, VLSI.
I. INTRODUCTION
R ECENTLY, interconnect capacitance is one of the most
important parameters in estimating the circuit delay in the
multilayer interconnections in VLSI circuits. According to the
Semiconductor Industry Association’s (SIA’s) roadmap in 1997
[1], interconnection delay will continue to increase in future
generations even if we can develop new lower dielectric mate-
rials and use copper interconnects. On the other hand, SIA pre-
dicts that transistor gate delay will continue to decrease. There-
fore, in current and future generations, delay of interconnection
becomes a dominant factor for determining the performance of
digital systems, and it becomes important to estimate the capac-
itance matrix of multilayer interconnection in designing VLSI
systems [7] and for delay calculation [2]. Several methods for
modeling interconnect capacitance [3]–[5], and for delay esti-
mation [6], [7] have been proposed, but the accuracy of these
models should be certificated based on comparison with mea-
surement results, especially in deep submicrion (DSM) design.
Therefore, it is requested to develop precise measurement of
capacitance components in complex patterns of conductors in
DSM VLSI. Extraction of capacitance components of multi-
layer interconnections, however, has many difficulties. A large
number of test pads are needed to extract these components be-
cause the number of the capacitance components is increasing
in proportion to the square of the conductor number. In addi-
tion, test structures for extracting target capacitance components
should be large enough to neglect parasitic effects. Therefore a
precise and simple method for extraction with a small test el-
ement group (TEG) pattern becomes a key issue for now and
Manuscript received February 7, 2000.
The authors are with the VLSI Design and Education Center, University of
Tokyo, Bunkyo-ku, Tokyo 113, Japan (e-mail: {mido; ito; asada}@silicon.u-
tokyo.ac.jp).
Publisher Item Identifier S 0894-6507(00)03555-7.
0894–6507/00$10.00 © 2000 IEEE
145
future VLSI’s. Several proposals of precise measurement of in-
terconnect capacitance are made in [3], [8], and [9], but these
are not suitable for multilayer interconnection from measure-
ment time and area cost point of view. In our previous work
[10], we had proposed the test structure with a shift register
for extraction of capacitance matrix based on the high-resolu-
tion measurement technique [8] and a new extraction method. In
that method, it was required to process measured data to obtain
the matrix components of the capacitance, because the measure-
ment data were linear combinations of the matrix components.
The calculation process was composed of multiple steps of sub-
tractions, so that degradations of the significant digits should
be carefully treated. In this paper, we will propose an improved
measurement method to extract capacitances directly without
degradations of the significant digits.
II. PRINCIPLE OF EXTRACTING COMPONENTS OF
CAPACITANCE MATRIX
To measure the interconnect capacitance with subfemto-farad
resolution, the test structure was presented by Chen et al. [8].
Fig. 1(a) shows a schematic diagram of their test circuit that has
two driver units: a reference unit and a load unit. The reference
unit is used to cancel the parasitic capacitances in the load unit.
The interconnect capacitance is obtained by comparing the cur-
rent induced to load capacitance with reference. The gate inputs
of nMOS and pMOS are separated to suppress the through-cur-
rent by supplying nonoverlapping clock signals. In that method,
the larger the number of the components of capacitance ma-
trix becomes, the larger the number of test pads becomes. In
our previous work, we employed the combination of driver cir-
cuits, which we mentioned above, and a shift register circuit
to keep the number of test pads to eight, independent of the
number of components of the matrix. Now, to reduce extrac-
tion error, we propose an improved method by refining driver
circuits, which can measure the target capacitance directly, as
shown in Fig. 1(b).
Our target is to extract the components of capacitance matrix,
which consists of conductors and grounded substrate. The prin-
ciple of extraction is divided into two processes: extraction of
conductor–conductor capacitance and conductor–substrate ca-
pacitance, because the substrate is kept grounded. First, to ex-
tract conductor–conductor capacitance, as shown in Fig. 2(a)
(in this case, the target is capacitance between and ),
one of two conductors ( ) is driven to and ground synchro-
nized with a driving clock, and , and the other conductor
146 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 13, NO. 2, MAY 2000

Fig. 2. The principle of measurement. Because the voltage of substrate is

invariable, the process of extraction is divided into two. These examples are
for a single-layer model, but the principle for multilayer model is similar
to these. (a) Measurement of conductor-to-conductor capacitance, C . (b)
Measurement of conductor–substrate capacitance, C .

the discharging current induced to the target capacitance is mea-

sured as (1).
Fig. 1. Schematic diagram of test structure with subfemto-farad resolution. To implement the above measurement principle, each driver
Gate signals of nMOS and pMOS are separated to suppress through-current and connected to conductors needs to take the following four driving
are supplied by a nonoverlapping clock. (a) Driver circuitry in previous work. modes using three MOS transistors; pMOS for charging, ,
(b) Proposed driver circuitry. Differently from the previous driver, the target
to measure is discharging current from the conductor or the negative-charging nMOS for discharging, , and nMOS for measuring dis-
current to the conductor. Nonoverlapping driving signals are similar to the charging current, . The four driving modes are as follows.
signals for the previous driver but depend on the driving condition of each
conductor.
• Mode 1: As shown in Fig. 3(a), for measuring
charging/discharging current is cut off and the gate nodes
of and are connected to the nonoverlapping
is connected to ground by two ways; one is directly connected clock signals, and , respectively. In this case,
to common ground, and the other is through the ampere meter. charging current flows through to the conductor
These two ways are switched by the driving clock signals. In and discharging current flows through from the
these charging and discharging processes, the conductor ( ) is conductor.
kept grounded but electrostatistically-induced current caused by • Mode 2: As shown in Fig. 3(b), and are cut off
the mutual capacitance [ in Fig. 2(a)] flows to the conductor and is kept on. In this case, the target conductor is
when the conductor ( ) is driven to and ground. Using a kept grounded and the electrostatistically induced current
current circuit, as shown in Fig. 2(a), the conductor ( ) is con- caused by the mutual capacitance flows through .
nected to ground through the ampere meter in charging cycle, • Mode 3: As shown in Fig. 3(c), is cut off and the
and it is connected directly to ground in discharging cycle, so gate nodes of and are connected to nonoverlap-
that the ampere meter indicates the charging current as ping clock signals, and , respectively. In this case,
charging current flows through to the conductor and
discharging current flows through and the ampere
meter.
(1) • Mode 4: As shown in Fig. 3(d), is cut off and the gate
nodes of and are connected to the nonoverlap-
Here, is clock frequency. ping clock signals, and , respectively. In this case,
Second, to extract conductor–substrate capacitance, as shown the target conductor is kept grounded, but the electrostatis-
in Fig. 2(b) (in this case, the target is capacitance between and tically induced current caused by mutual capacitance cir-
substrate, ), all conductors are driven to and ground. In culates through the ampere meter.
the discharging cycle, only one conductor ( ) corresponding to For example, in the case of Fig. 2, each conductor takes the
the target capacitance is connected to ground through the am- following driving mode, depending on the target capacitance to
pere meter to measure the discharging current. As a result, only measure, as shown in Table I.
MIDO et al.: CAPACITANCE MATRIX OF MULTILAYER INTERCONNECTION 147

TABLE I
DRIVING MODE FOR EACH CONDUCTOR TO
EXTRACT CAPACITANCES IN FIG. 2

Fig. 4. Circuitry to generate the gate signals for determining the driving
modes. D and M are control signals provided from D flip-flops in the shift
register.

TABLE II
THE SIGNALS D AND M FOR EACH DRIVING MODE.

Fig. 3. (a)–(d) Four driving modes for each conductor in target matrix. Gray
arrow indicates the current flow in charging and discharging cycle.  and 
are nonoverlapping clock signals, as shown in Fig. 1.

According to these four driving modes, the gate signals, ,

, and of , , and can be expressed as

(2)
(3)
(4)

respectively. These gate signals are realized, as shown in Fig. 4.

Here, and are control signals of drivers to determine the
modes described above, as shown in Table II. These control sig-
nals are provided from flip-flops. In this method, each driver
needs to connect two flip-flops to take four driving modes, as
shown in Fig. 5.
III. IMPLEMENTATION OF THE TEST STRUCTURE
A block diagram of this test structure is shown in Fig. 5. As
shown in this figure, using a shift register for storing the and
signals, the number of test pads is kept to eight, independent
of the size of the target matrix. For direct measurement of the
Fig. 5. Schematic diagram of the test structure using a shift register circuit.
Each conductor is controlled by the outputs of 2 D flip-flops, D and M , to
determine the drive modes. The number of pads is kept to eight, independent of
the size of the target matrix.
components of the capacitance matrix, it needs to preset the shift
register to determine the driving mode of each conductor before
applying the clock signals, and .
These test structures are fabricated in the chip fabrication pro-
gram of the VLSI Design and Education Center (VDEC), Uni-
versity of Tokyo, Tokyo, Japan, with the collaboration by NTT
Electronics Corporation and Dai Nippon Printing Corporation.
148 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 13, NO. 2, MAY 2000
Fig. 6. Microphotograph of the test structure to characterize capacitance
matrix components with shift register. Horizontally symmetric driver and
shift register units are stacked up vertically. On the right side of these units,
long wires for extraction are placed, and, on the left side, reference loads for
compensating the parasitic capacitances in the driver units are placed. Test
pads are the size of 50 m square, and these are for a probe card for fully
automating a probe system.
An example of the test structure is shown in Fig. 6. This test
structure extracts four conductor matrix. It is composed of 86
field-effect transistors (FET’s) for each conductor to drive with
reference circuit: 32 FET’s for 2 flip-flops in shift register, 27
FET’s for the load driver circuit, and 27 FET’s for the reference
driver circuit.
IV. MEASUREMENT RESULTS
In this section, we will demonstrate the method, showing
some examples of measurement results, and then we will show
its accuracy by evaluating measurement errors caused by asym-
metry of the structures.
A. Measuring Flow
Once probes for measurement are placed correctly, the mea-
surement process for this method can be automatically carried
out using a GPIB script, which controls measurement equip-
ment, such as a DC voltage source (HP4145B) and a data gen-
erator (HP80000). The measurement process is as follows.
1) Set test vectors for the shift register to specify the driving
mode for each conductor to determine the target capaci-
tance.
2) Set the driving frequency by specifying the period of
nonoverlapping clock signals for the target conductors.
3) Send the test vectors from the pulse generator to the shift
register through the shift-in pad.
4) Send the clock signal, and start the cycle of charging and
discharging conductors.
5) Measure the target current value that flows through the
target capacitance as the mean value of 20 measured data.
The final data are obtained as differences between the
current values for the driving circuits and for the reference
circuits.
Fig. 7. Frequency characteristics of measured capacitance values. These
capacitances are thought to be the largest in this test fabrication. We can see
that capacitance values are independent of driving frequency in the range where
the frequency is less than 1 MHz as the saturated region.
If the driving frequency is too high, the current values are
saturated because of the limit of driving current source. This
saturation results in underestimation of the static capacitance
values. On the other hand, when the driving frequency is too
low, the relative magnitude of noise becomes larger because
measurement values become small. Fig. 7 shows an example of
frequency characteristics of measured capacitances that are the
largest capacitances in this test chip. As a result, we conclude
that each capacitance value can be obtained with enough accu-
racy by linear fitting of measurement values from 100 KHz to
1 MHz.
B. Measurement Results
Using the measurement process mentioned above, we ob-
tained components of capacitance matrices, as shown in Fig. 8
for examples. In Fig. 8, the width of conductors in each layer is
1.2 m, and the horizontal gap between two conductors is 0.7 ,
as drawn. In calculating capacitance values per unit length (1
cm), we measured two types of structures with line lengths of
1.645 and 3.29 mm, and we obtained capacitance values as a
function of line length.
C. Error Estimation by Measuring Structure Without Load
Capacitance
The major factor of measurement error is caused by the asym-
metry of the drive unit and the reference unit. Therefore, we
estimated the magnitude of error caused by the asymmetry by
measuring test structures without load capacitance. Fig. 9 shows
the histogram of magnitude of measurement errors, .
is defined from measurement as follows:
(5)
(6)
MIDO et al.: CAPACITANCE MATRIX OF MULTILAYER INTERCONNECTION 149

1 1
Fig. 9. Histogram of magnitude of measurement errors, x . x is defined
as (7). In making this histogram, we measured 150 samples of errors from
all over the wafer. Each sample is a mean value of 20 measurements. Three
thousand measurements are used for making this histogram.

Assuming that these values of errors are distributed as

Gaussian, we can obtain the standard deviation, , as follows:

(8)

(9)

As a result of (9) and value from 3000 measurements, we

can estimate the range of absolute errors caused by the asym-
metry, , as follows:

(10)
fF (11)
Fig. 8. Examples of measurement results of test structures. (a) Poly-M1, (b)
Poly-M1, and (c) M1–M2. All capacitance values in these figures are in the unit
of pF/cm. The width of wires in each layer is 1.2 m, and the horizontal gap According to the error evaluation described above, we can con-
between two wires is 0.7 m, as drawn.
clude that this measurement method can measure the compo-
nents of capacitance matrix with the precision of femto-farad
order.
(7)
D. Comparison Between Measurement and Calculation
Here, , , , , , and are the number of measure-
We compared the measurement results with numerical calcu-
ment for one sample, the number of samples, current in the
lations using “Raphael” on structures. Structures for calcu-
driving side, current in the reference side, supply voltage, and
lation were created based on cross-sectional microphotographs,
driving frequency, respectively. For simplicity, we set the center
as shown in Fig. 10.
of distribution of 0 by employing geometric mean values as
Table III shows the comparison between measurements and
. In making the histogram, as shown in Fig. 9, we measured
numerical calculations. In this table, relative error values, Err,
150 samples of errors from all over the wafer. Each sample is
are obtained by
a mean value of 20 measurements, according to the measuring
process mentioned above. Therefore, 3000 measurements ware
carried out for making this histogram. (12)
150
(a)
Fig. 10. Cross-sectional view of interconnections: (a) Poly-M1; (b) Poly-M2; and (c) M1-M2.
As shown in this table, measurement values are in good
agreement with calculation values, but the relative errors
of cross-capacitance values, such as po(r)-m1(l), po(r)-m2(l),
m1(l)-m2(r), and so on, are bigger than the errors of other ca-
pacitances because of their low absolute capacitance values.
The absolute differences between measurements and calcu-
lations are more than 1 fF, because cross-sectional photos
were not clear and some errors exist between the calculation
model and the real devices.
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 13, NO. 2, MAY 2000
(b)
(c)
V. CONCLUSION
A compact new test structure for direct extraction of compo-
nents of the capacitance matrix for the multilayer interconnec-
tions has been presented. In this new method, each capacitive
component in integrated structures was separately and directly
obtained from measurement, and the total pads are kept to eight,
independent of the size of the target matrix. As a result of evalu-
ation of measurement error caused by asymmetry of structures,
MIDO et al.: CAPACITANCE MATRIX OF MULTILAYER INTERCONNECTION
TABLE III
COMPARISON BETWEEN MEASUREMENT AND NUMERICAL CALCULATION.
CALCULATION MODELS FOR “RAPHAEL” ARE BASED ON CROSS-SECTIONAL
VIEWS, AS SHOWN IN FIG. 10. IN THESE TABLES (a)–(c), “po,” “m1,”
“m2,” AND “sub” INDICATE POLY SILICON, METAL 1, METAL 2, AND
SUBSTRATE, RESPECTIVELY, AND “(1)” AND “(r)” MEANS THE RIGHT AND
LEFT SIDE, RESPECTIVELY.
this new method can measure components of capacitance matrix
with a precision of femto-farad order. Measurement data are in
agreement with numerical calculation.
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Tetsuhisa Mido was born in Ehime, Japan, in 1970.
He received the B.S. degree in electric engineering
from the University of Tokyo, Tokyo, Japan, in 1993,
and the M.S. and Ph.D. degrees in electronic engi-
neering from the University of Tokyo, in 1996 and
1999, respectively.
He is currently with Avant! Corporation as a Re-
search and Development Staff Member of analysis
product line. He is interested in design and evalua-
tion of CMOS VLSI system for low-power and high-
speed application.
Dr. Mido is a member of the Institute of Electronics, Information, and Com-
munication Engineerings of Japan (IEICEJ) and the Japan Society of Applied
Physics (JSAP).
Hiroshi Ito was born in Kanagawa, Japan, in 1971.
He received the B.E. degree from the Tokyo Univer-
sity of Agriculture and Technology, Tokyo, Japan, in
1993, the M.S. and Ph.D. degrees in electronic en-
gineering from the University of Tokyo, in 1995 and
1999, respectively.
He is currently with the VLSI Design and Educa-
tion Center (VDEC), University of Tokyo. He is in-
terested in process integration, device modeling, and
silicon-on-insulator (SOI) devices for low-power and
high-speed applications.
Dr. Ito is a member of the Japan Society of Applied Physics.
Kunihiro Asada (S’77–M’80) was born in Fukui,
Japan, on June 16, 1952. He received the B.S., M.S.,
and Ph.D. degrees in electronic engineering from the
University of Tokyo, Tokyo, Japan, in 1975, 1977,
and 1980, respectively.
He joined the faculty of the University of Tokyo as
a Research Associate in 1980 and became a Lecturer,
an Associate Professor, and a Professor in the Depart-
ment of Electronic Engineering in 1981, 1985, and
1995, respectively. From 1985 to 1986, he stayed at
Edinburgh University, Edinburgh, Scotland, as a Vis-
iting Scholar supported by the British Council. He moved to the VLSI Design
and Education Center (VDEC), University of Tokyo, when it was newly estab-
lished in 1996. He is currently a Professor of VDEC, also engaged in education
in the Department of Electronic Engineering. His interests are in design and
evaluation of integrated systems and their component devices.
Dr. Asoda is a member of the Institute of Electronics, Information, and Com-
munication Engineering of Japan (IEICEJ) and the Institute of Electrical Engi-
neerings of Japan (IEEJ). He served as the Editor of IEICEJ TRANSACTION ON
ELECTRONICS from 1990 to 1992.