13428 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 37, NO.
11, NOVEMBER 2022
Simplified Approach for Acquisition of Submodule
Capacitor Voltages of the Modular Multilevel
Converter Using Low Sampling Rate
Sensing and Estimation
Bishwajyoti Purkayastha and Tanmoy Bhattacharya , Member, IEEE
Abstract—The modular multilevel converter (MMC), used in
high-voltage dc applications, consists of hundreds of submodules in
each arm. The operation and control of the MMC require sensing
of the capacitor voltage of each submodule. The transmission of
the sensed data from hundreds of submodules over individual
channels leads to wiring complexity. This work suggests that time-
multiplexing can be used to transmit the sensed data of multiple
submodules across a common serial interface bus. Time multiplex-
ing, however, decreases the sampling rate. Since the submodule
capacitor voltage has both ac and dc components, an adequate
sampling rate must be maintained to avoid the aliasing of ac
components. In this article, an estimation scheme is investigated for
reconstructing the ac components of the submodule capacitor volt-
ages within the processing platform, leaving just the dc component
to be transmitted over the common bus. The mathematical analysis
of the data transmission system and proposed estimation scheme
is performed, and the influence on the closed-loop performance
is studied. The proposed scheme is experimentally verified in the
laboratory.
Index Terms—Modular multilevel converter (MMC), sampling,
submodule capacitor voltage estimation.
I. INTRODUCTION
HE modular multilevel converter (MMC) is a popular
T choice for high-voltage dc (HVdc) application because
of its modularity, scalability, high efficiency, and excellent har-
monic performance [1]. The MMC utilized in HVdc applications
is made up of hundreds of submodules [2]. The operation and
control of an MMC require the sensing of capacitor voltages
of all these submodules [3]. Owing to the large number of
submodules, the sensing process can lead to a complex wiring
system [4]. Moreover, a large number of input ports are required
by the processor to acquire the sensed data.
Manuscript received 26 January 2022; revised 23 April 2022; accepted 30 May
2022. Date of publication 16 June 2022; date of current version 26 July 2022.
This article was presented in part at National Power Electronics Conference
(NPEC), Tiruchirappalli, India, Dec. 13–15, 2019 [30]. Recommended for pub-
lication by Associate Editor F. Dijkhuizen. (Corresponding author: Bishwajyoti
Purkayastha.)
The authors are with the Department of Electrical Engineering, Indian In-
stitute of Technology Kharagpur, Kharagpur 721302, India (e-mail: bishwajy-
oti18@gmail.com; btanmoy@ee.iitkgp.ernet.in).
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TPEL.2022.3183504.
Digital Object Identifier 10.1109/TPEL.2022.3183504
0885-8993 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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In order to avoid the aforementioned problems, open-loop
control strategies were presented in [4] and [5], which do not
require the sensing of submodule capacitor voltages. However,
the stability of the open-loop approach is a concern [6]. Hence,
the closed-loop control is usually adopted, which require the
knowledge of the submodule capacitor voltage. There are two
main approaches available in the literature to address the com-
plexity associated with capacitor voltage sensing, which are as
follows:
1) eliminate the use of capacitor voltage sensors and estimate
the capacitor voltages [2], [7]–[25];
2) keep the individual capacitor voltage sensors and simplify
complexity using local and global processors [6], [26],
[27] and some form of estimation [6], [27], [28].
For estimation, some alternate voltage measurements such
as dc-link voltage, arm voltage, arm inductor voltage, output
voltage, etc., are required. In [7], the capacitor current of the
submodule is integrated to estimate the voltage and any error
in prediction is corrected by sensing the total output voltage
of the submodules in an arm. The authors in [7] and [12]
utilize a single voltage sensor per arm for this measurement.
The capacitor current of the submodules are calculated using
the gate signal status and the arm currents. The measurement
of the arm voltage is divided into groups in [8]–[11], [14].
In order to ensure the periodic correction of all the estimated
submodule voltages in an arm, Picas et al. [8] have introduced
an enforced measuring algorithm. In order to ensure frequent
extraction of the capacitor voltage from the voltage sensors, the
algorithm of switching of the submodules is modified in [9].
Since the measurement of the switching waveform of the arm
voltage is limited by the bandwidth of the voltage sensor, in [10],
a compensation technique is introduced to overcome the asso-
ciated error. In [11], a matrix method is proposed to determine
the submodule capacitor voltage from the measurement of the
output voltage of a group of submodules and their corresponding
switching state. Algorithm-based techniques such as Kalman fil-
ter [12]–[14], exponentially weighted recursive least square [2],
adaptive linear neuron (ADALINE) [15], [16], hybrid adaptive
linear neuron RLS scheme [17], and neural network [18] have
also been studied for estimating the capacitor voltages. The
observer-based techniques such as state observer [19], adaptive
PURKAYASTHA AND BHATTACHARYA: SIMPLIFIED APPROACH FOR ACQUISITION OF SUBMODULE CAPACITOR VOLTAGES
Fig. 1. Serial data frame containing capacitor voltage information of 500
submodules for two consecutive samples.
observer [20], interconnected observer [21], and sliding mode
observer [22]–[25] have also been used to estimate submodule
capacitor voltages from the alternate measurements. A capacitor
sizing model is proposed in [29] for drives application to estimate
the capacitor voltage ripple.
In the second approach, the authors of [6], [26], and [27],
sensed the capacitor voltage of each submodule of an arm and
used it in a local processor for balancing the submodules in
that arm. The circulating current control and generation of the
modulation signal for the arms require the knowledge of the
sum of the capacitor voltages in each arm and not the individual
voltages. This sum is estimated in a global processor using the
analytical technique in [27] and using the discrete sliding mode
observer in [6] from the measurement of the arm currents and
terminal voltages. Thus, the processing burden is divided into
multiple processors. However, reduction in wiring complexity is
not considered in this approach. In [28], the submodule capacitor
voltage sensing is divided into six groups. At a given time, only
one of the six groups communicates with the processor; and
the capacitor voltages of the submodules belonging to the rest
of the groups are estimated during that interval. This reduces
the input port requirement of the processor to one-sixth but the
wiring complexity remains. While dividing the measurement
into groups, the concern is to keep the sampling rate suffi-
ciently high to avoid loss of information in the sensed capacitor
voltages. In [30], an estimation algorithm is proposed that can
compensate the loss of information due to a low sampling rate.
The authors in [31] provide a review of different estimation
techniques.
The second approach, which employs voltage sensors for each
submodule, is used in this study. In order to reduce the associated
complexity of acquiring the capacitor voltage information of the
large number of submodules, this work suggests that multiple
submodules can use a common serial interface bus for commu-
nicating the sensed data to the processing platform. This can
substantially simplify the associated wiring system. However,
the serial interfacing has its own set of limitations, which can be
explained using the example shown in Fig. 1.
The figure shows two successive frames (samples) of data
containing capacitor voltage information of 500 submodules. It
is assumed that the data field corresponding to each submodule
is 50 bits long. Apart from the actual sensed data, a data field
has various components such as the start bit, stop bit, acknowl-
edgement, command, address, error checking bits, etc. Hence,
assuming a data field length of 50 bits is reasonable. Considering
the baud rate of the serial communication to be 5 Mb/s, the
time length of each data field is 10 μs; going further, the time
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13429
length of the complete data frame (denoted by τs ) containing
the capacitor voltage information of 500 submodules is 5 ms,
which implies that the sampling rate of capacitor voltage sensing
is 200 samples per second. Since the data are being transmitted
serially, the value of the capacitor voltage of a particular instant
can take up to τs unit time (i.e., 5 ms in this example) to
reach the processor. There can be two potential problems of
this approach. First, because of the relatively low sampling rate,
the ac components of capacitor voltage may not be reproduced
properly. According to the sampling theorem [32], aliasing can
occur when the sampling rate is less than twice the frequency
of a constituent ac component. Thus, there arises a limitation
on the number of submodules that can use a common serial
interface for transmitting the sensed data. Second, in order to
achieve an adequate bandwidth for the closed-loop system, a
higher order compensator is required to compensate for the
delay induced by the time length of the data frame. In order to
overcome these limitations, the estimation algorithm presented
in [30] is explored. Using analysis, it is shown that the estimation
algorithm requires knowledge of the arm current and the dc
component of the capacitor voltage in order to recreate the entire
profile of the capacitor voltage. Thus, the dc component alone
needs to be transmitted, which can be done at a low sampling
rate. This allows transfer of the sensed data from a large number
of submodules over a common bus without having to worry
about the resulting low sampling rate.
For estimation, the existing techniques depend on alternate
sensing such as dc-link voltage, total output voltage of submod-
ules, etc. If the accompanying sensing circuit fails, it can com-
promise the estimation of all submodule capacitor voltages that
rely on that measurement. The scheme proposed in this article is
a hybrid approach because the dc component of the submodules’
capacitor voltage is sensed through individual voltage sensors,
whereas the ac component is estimated from the arm current. If a
submodule’s voltage sensing circuit fails, the capacitor voltage’s
dc component information is lost for that submodule only. The
failure in the arm current sensing, however, will result in the
loss of ac component information for all submodules belonging
to that arm. However, it should be emphasized that the arm
current sensing is crucial for the circulating current control
and its failure will jeopardize the MMC’s overall operation,
regardless of whether estimation is utilized or not. Though the
reduced sensors approach [2], [7]–[25] minimizes the cost of
sensing, the provision of individual sensing provides a sense
of security and reliability. The reduced sensors approach can
actually supplement an MMC system, running on individual
sensing, by increasing the reliability [8]. However, the failure
in serial communication is a major source of concern in the
proposed approach. In this context, literature suggests that there
are solutions available, which can increase the reliability of
serial communication, such as daisy-chain configuration, error-
detecting schemes [33].
The subsequent sections are as follows: Section II discusses
the outline of the data acquisition scheme; the analysis of the
estimation scheme and the closed-loop system are considered in
Sections III and IV, respectively; followed by the experimental
results in Section V, and finally, Section VI concludes this
article.
 13430
Fig. 2. Transmission of sensed data using common interface bus.
II. OUTLINE OF THE DATA ACQUISITION SCHEME
Fig. 2 shows the implementation scheme for transmitting the
dc component information of the capacitor voltage of N sub-
modules (SM -1, SM -2,...,SM -N) using a common interface
bus. All the N-submodules may belong to a single arm or more
than one arm.
Each submodule contains a voltage sensor, a low-pass filter
circuit, and an analog-to-digital converter (ADC). An isolation
stage (not shown in the figure) is also necessary to isolate
the power and control circuits. The voltage sensor is used to
measure the capacitor voltage of the submodule, and it pro-
duces a scaled-down reproduction of the actual capacitor voltage
represented in the figure by {vc1 , vc2 , . . ., vcN }. The output
of the voltage sensors consists of dc and ac components; for
an example, vc1 = v̄c1 + v̂c1 , where v̄c1 is the dc component
and v̂c1 represents the ac components. The low-pass filter is
designed with an appropriate cut-off frequency such that it filters
out the ac components. Thus, the output of the filters contains
the dc component v̄c1 , v̄c2 ,.., v̄cN . These signals are converted
into digital data using ADCs associated with the respective
submodules. The digital data from multiple submodules can be
transmitted to the processor over a common serial interface bus.
The data are transmitted serially in the form of frame as shown
in Fig. 1. Since the dc component is being transmitted, the data
from a large number of submodules can be transmitted through
a common bus at a low sampling rate. The estimation scheme,
which is implemented on the processor, uses the dc components
(v̄c1 , v̄c2 ,..., v̄cN ) received through the common serial interface
bus and the reconstructed capacitor currents of the submodules
(ic1 , ic2 , . . ., icN ) to obtain the complete profile of the capacitor
voltages (vc1 , vc2 , . . ., vcN
est est est
) containing both dc and ac com-
ponents. The capacitor currents can be reconstructed using the
arm current and switching states of the submodules as shall be
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 37, NO. 11, NOVEMBER 2022
Fig. 3. Schematics. (a) DC to three-phase ac MMC. (b) Half-bridge
submodule.
explained in Section III-A. The arm current is sensed using the
current sensor. From Fig. 2, it can be understood that the use of
the common bus along with the estimation scheme can reduce
the wiring complexity and minimize the input ports required
by the processor, and hence, simplify the data acquisition. The
estimation scheme, implemented on the processor, serves the
following purposes.
1) It reconstructs the capacitor voltage profile, which is nec-
essary for capacitor voltage balancing of the submodules
in an arm using the sorting algorithm [34].
2) The phase lag introduced by the low-pass filter and the
delay due to serial communication gets compensated by
the estimator.
III. CAPACITOR VOLTAGE ESTIMATION SCHEME
A. Overview of MMC and Determination of Capacitor Current
Fig. 3(a) shows the schematic diagram of a dc–ac MMC
connected to a three-phase ac grid. It consists of three legs, each
containing two arms connected through inductor. Each arm is
constituted of half-bridge submodules as shown in Fig. 3(b).
From Fig. 2, it can be observed that the estimation algorithm
requires information about the capacitor current of the submod-
ules. In the schematic of the half-bridge submodule shown in
Fig. 3(b), imod represents the current entering the submodule
and ic represents the capacitor current. Let ST and SB be two
Boolean functions representing the switching states of the top
and bottom insulated gate bipolar transistors, respectively. The
OFF and ON states of the switches are represented by 0 and 1,
respectively. The capacitor current ic can be obtained from the
module current imod using the following relation:
⎧
⎪
⎨imod ; if (ST = 1) or
ic = [(ST = 0) & (SB = 0) & (imod > 0)] (1)
⎪
⎩
0; otherwise.
The aforementioned equation also considers the situation of
dead time when both the switches are OFF, and one of the two
diodes conducts depending on the direction of current. As seen in
Fig. 3(a), the current flowing into a submodule is the same as the
current flowing in the arm containing that particular submodule.
Thus, it can be concluded that by sensing the current in an arm,
PURKAYASTHA AND BHATTACHARYA: SIMPLIFIED APPROACH FOR ACQUISITION OF SUBMODULE CAPACITOR VOLTAGES 13431

following relation:
1 K 1 1
vcest (s) = ic (s)+ v sen (s).
sC + K sC + K s/ωf + 1 sτs + 1 c
(3)
The frequency response of the system can be obtained from (3)
by putting s = jω as follows:
1 K 1
vcest (jω) = ic (jω) +
jωC + K jωC + K jω/ωf + 1
1
× v sen (jω). (4)
jωτs + 1 c
The frequency response is divided into dc response and ac
response and analyzed individually.

Fig. 4. Block diagram of the estimation scheme.

C. DC Response
1) DC Response to ic keeping vcsen = 0: The corresponding
the capacitor currents of all the submodules present in that arm expression can be obtained from (4) by putting vcsen = 0 and ω
can be determined using their respective switching states. = 0 (for dc response). At steady state, the submodule capacitor
For a given initial voltage Vc0 , the voltage vc across the current has zero dc component (i.e., for ω = 0, ic = 0). Thus,
submodule capacitor C [see Fig. 3(b)] can be equated to its vcest is given by
current ic by the following relation: 
  1
1 t vcest  sen = .0 + 0 = 0. (5)
vc (t) = ic (t) dt + Vc0 . (2) vc =0, ω=0 j.0.C + K
C 0
However, at steady state, the dc component of the submodule
Theoretically, the estimation of the capacitor voltage can be capacitor voltage settles at a finite value, but this is not reflected
done using (2). The submodule capacitor current ic can be in vcest in (5). This proves that the knowledge of the capacitor
determined using (1) and arm current sensing. However, there current (ic ) alone is not sufficient for the estimation scheme of
is a practical limitation to this scheme. Any offset in the arm Fig. 4.
current sensing will also lead to an offset in the capacitor current As mentioned in Section III-A, an offset in arm current
calculated using (1). Applying (2), it can be understood that the sensing will result in an offset in the calculated capacitor current.
presence of a dc offset in ic will result in the integration output Therefore, the overall dc response considering any offset in the
growing continuously. This phenomenon is called integration capacitor current (Icoff ) is given as
drift. It shows that (2) cannot be practically implemented in the
 Icoff
processor to estimate vc . Hence, the estimator shown in Fig. 4  1
vcest  sen = I off
+ 0 = . (6)
has been used for capacitor voltage estimation and is discussed vc =0, ω=0, ic =Icoff j.0.C + K c
K
in detail in the next section.
Unlike (2), the presence of the dc offset in ic in Fig. 4 causes a
fixed offset in the estimated value and does not cause integration
B. Capacitor Voltage Estimation Scheme
drift. This shows the importance of keeping a feedback path (K)
The acquisition of the capacitor voltage of one submodule in the estimator as shown in Fig. 4.
using Fig. 2, along with its corresponding estimator, is depicted 2) DC Response to vcsen keeping ic = 0: By putting ic = 0
in s-domain by the block diagram of Fig. 4. In the figure, vcact and ω = 0 (for dc response) in (4), the first term becomes zero.
represents the actual capacitor voltage. The voltage sensor in If the average/dc value of voltage vcact (and hence vcsen ) is Vc ,
Fig. 2 scales down vcact to a level compatible with the control the expression for the dc response is given by
circuit. Since the analysis is being carried out for the actual  K

values of voltages and currents, the voltage sensor is taken to be vcest  =0+ Vc = Vc . (7)
ic =0,ω=0 j.0.C + K
of unity gain. The low-pass filter is a first-order filter having a
cut-off frequency of ωf . It has been explained in Section I that 3) Complete DC Response to inputs ic and vcsen : The com-
for a frame of time-length τs , there can be a maximum delay of plete dc response is obtained by adding (6) and (7) as follows:
τs for the capacitor voltage information of a particular instant 
 I off
to reach the processor. This delay is represented by a first-order vcest  = c + Vc . (8)
model with a time constant τs . The output of the delay is fed to the ω=0 K
estimator. ic is the capacitor current of the submodule calculated In the ideal case, Icoff = 0, and so, vcest = Vc ; and the parameter
from the arm current using (1). K is a feedback constant used in K does not have a role in the dc response. There may be a little
the estimator. The submodule capacitance is represented by C. offset Icoff in real life; as a result, a value of K that is too small
The estimator output vcest can be related to the sensed capacitor can create a substantial offset in the estimated voltage. From (8),
voltage vcsen and the calculated capacitor current ic using the it can be understood that the sensing is necessary because the

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 13432 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 37, NO. 11, NOVEMBER 2022

dc component of vcest has been obtained from the sensed data where the factor within the square brackets is denoted by G(jω).
(vcsen ). Ideally, G(jω) should be 1 ∠ 0◦ so that the estimated capacitor
voltage (vcest ) is the same as the actual capacitor voltage (10).
D. AC Response As understood from Section III-D1, the performance of the
estimator depends on the value of K; and hence, the magnitude
1) AC Response to ic keeping vcsen = 0: The corresponding
and phase of G(jω) need to be studied for different values of K.
mathematical expression is written as
For this, the parameters ωf , τs , and C in G(jω) are first decided

 1 as follows.
vcest  sen = ic (jω). (9)
vc =0, ω>0 jωC + K a) Choice of ωf : Since the focus of the work is toward
MMC used in HVdc application, an MMC operating as a dc–ac
The ac components of the actual or sensed capacitor voltage can
converter connected to a 50-Hz grid is considered. The promi-
be related to the capacitor current as follows:
nent low-frequency ac components of the submodule capacitor
1 voltage comprise of fundamental, second, and third harmonics
vcact (jω) = vcsen (jω) = ic (jω). (10)
jωC as follows: 50, 100, and 150 Hz [35]. The low-pass filter is used
to filter out the ac components present in the capacitor voltage.
By comparing (9) and (10), it can be understood that if K is
Since the lowest frequency present in the capacitor voltage is
chosen such that K << ωC or, in other words, K/ωC << 1,
50 Hz or 100π rad/s, ωf is chosen to be 20π rad/s, which is
the following approximation can be made:
one-fifth of the lowest frequency component.
1 1 b) Choice of τs : As mentioned in Section III-B, the time
≈ (11)
jωC + K jωC constant τs in the delay model is the time length of the data frame
containing the capacitor voltage information of one sample
and the estimated capacitor voltage vcest (jω) will approach
(see Fig. 1). A time length of τs indicates a sampling rate of
vcact (jω) = vcsen (jω). The submodule capacitor current and
1/τs samples per unit time. The effectiveness of the estimation
voltage contain a few discrete frequency components; so, in
scheme is analyzed for the minimum allowable sampling rate
order to ensure that the approximation in (11) holds good, K
(1/τs ) for the transmission system i.e., the maximum allowable
has to be chosen sufficiently smaller than the value of ωC
value of τs . The sampling rate should be high enough to capture
corresponding to the constituent lowest frequency component.
the oscillation in capacitor voltage dynamics that occur during
2) AC Response to vcsen keeping ic = 0: If ic is not used,
transient conditions. The frequency of this oscillation is approx-
then the corresponding frequency response is obtained from (4)
imately equal to the capacitor voltage controller’s bandwidth.
as follows:
For an intended bandwidth of 10 Hz, the sampling rate should be
 K
 1 1 sufficient enough to capture the associated dynamic oscillation
vcest (jω) = v sen (jω).
ic=0, ω>0 jωC + K jω/ωf + 1 jωτs + 1 c of roughly 10 Hz. In light of this, it is decided to keep the
(12) sampling rate at 10 times the controller’s bandwidth i.e., 100
In Section III-D1, it is found that K is to be chosen such that samples per second. Accordingly, the value of τs turns out to be
K/ωC << 1. For such a value of K, the following approxima- 0.01 s. It can be noted that a sampling rate of 100 samples per
tion can be made: second is not sufficient enough with respect to the constituent
K low-frequency ac components of the capacitor voltage such as
≈ 0. (13) 50, 100, and 150 Hz. It is to be seen whether the estimation
jωC + K
scheme can recreate the capacitor voltage profile from the sensed
So, it is apparent that data that is sampled at such a low rate.

 c) Choice of C: The capacitance C is chosen as 1.5 mF,
vcest  →0 (14)
ic =0,ω>0 which is the value of submodule capacitance in the experimental
and the presence of ac frequency components in the sensed prototype (see Fig. 13).
capacitor voltage vcsen does not play any role during calculation d) Choice of K: The parameters ωf , τs , and C being
of vcest . This justifies the use of the filter in Fig. 2 to remove the decided, a suitable value of K has to be selected. The chosen
ac components from the sensed capacitor voltage (vcsen ). value of K should satisfy G(jω) ≈ 1 ∠ 0◦ in (15). As mentioned
3) Complete AC Response to inputs ic and vcsen : The expres- in Section III-D1, the relation K/ωC << 1 determines the
sion for the complete response can be obtained by putting (10) choice of K, where ω represents the lowest frequency com-
in (4) as follows: ponent present in the capacitor voltage. From the discussion on
“choice of ωf ,” 100π rad/s is found to be the lowest frequency
vcest (jω) component of the capacitor voltage, and accordingly, the relation
 K/(100πC) << 1 needs to be satisfied. In order to arrive at a
ic (jω) jωC K
= + suitable value of K, a range of values of K/(100πC) satisfying
jωC jωC + K (jωC +K)(jω/ωf +1)(jωτs + 1)
K/(100πC) << 1 is chosen; the magnitude and phase of G(jω)
ic (jω) at ω = 100π rad/s is calculated for this range and plotted in
= .G(jω) (15)
jωC Fig. 5. The magnitude and phase of G(j100π) is observed to be

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PURKAYASTHA AND BHATTACHARYA: SIMPLIFIED APPROACH FOR ACQUISITION OF SUBMODULE CAPACITOR VOLTAGES
Fig. 5. Plot of magnitude and phase of G(j100π) as a function of
K/(100πC).
TABLE I
PERCENTAGE OFFSET FOR DIFFERENT VALUES OF K/100πC
TABLE II
VALUES OF PARAMETERS ωF , τS , K, AND C
Fig. 6. Generation of arm voltage references of the leg-i of the MMC.
0.9997 and 0.6◦ for K/(100πC) = 0.01, which is very close
to the ideal 1 ∠ 0◦ . With the increase in K, the phase can be
seen to increase. Thus, K/(100πC) = 0.01 can be considered
to be an appropriate choice. As mentioned in Section III-C3,
for small values of K, a minor offset in current sensing will
cause a substantial offset in the estimated voltage. This is shown
in Table I, where the percentage offset observed for different
values of K/(100πC) is listed. Hence, a compromise is made
between accuracy and sensitivity to offset in current sensing;
and K/(100πC) is chosen as 0.1 or K = 0.1 × (100π rad/s) ×
(1.5 mF) = 0.0471 A/V. The corresponding magnitude and
phase of G(j100π) are 0.9922 and 6◦ , respectively.
The parameters ωf , τs , C, and K are listed in Table II.
IV. CLOSED-LOOP CONTROL SYSTEM
Fig. 6 shows the control system for the generation of arm
voltage references of leg-i, where i = {a, b, c}, for the grid-
connected MMC shown in Fig. 3(a). For the operation of
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13433
Fig. 7. Single submodule equivalent circuit for leg balancing control.
an MMC, the capacitor voltage of the submodules has to be
maintained at a reference value and this is ensured by the leg
balancing and arm balancing controls [36]. The leg-balancing
i
controller regulates the average capacitor voltage V̄cleg of the
∗
ith leg at the reference value Vc . The arm balancing con-
troller ensures that the difference between the average capacitor
i i
voltage of the upper and lower arms (V̄cup , V̄clow ) is zero. A
ff
feed-forward term (Iz ) that relates the active power output
reference of the converter to the dc component of the circulating
current of each leg is added to achieve a fast dynamic response.
The feed-forward term Izff is calculated from the three-phase
active power output reference P ∗ as Izff = P ∗ /3E, where E is
the dc-link voltage. The sum of the output of the controllers
and the feed-forward term forms the circulating current refer-
ence. The circulating current can be calculated from the up-
per and lower arm currents (iiup and iilow ) using the relation
(iiup + iilow )/2. An inner current controller is implemented to
regulate this current. The three-phase output voltage references
of the MMC (v ∗a , v ∗b , v ∗c ) are generated using the d-q control
of the three-phase active and reactive powers having reference
values of P ∗ and Q∗ , respectively [37]. To satisfy the KVL on
the input and output sides of the MMC, appropriate dc (E/2)
and ac (v ∗i ) components are provided as feed-forward terms to
∗i ∗i
form the upper and lower arm voltage references (vup , vlow )
as shown in Fig. 6. Based on the arm voltage references, the
selection of the submodules to be inserted is done using the
sorting algorithm [34]. The sorting algorithm ensures that the
capacitor voltages of the submodules within an arm are balanced.
In this work, the control of the capacitor voltages of the
submodules is based on their estimated value; and as a result, the
estimator needs to be included during the modeling of the outer
capacitor voltage control loop. The leg balancing controller is the
primary controller that balances the input and output side power
for the individual legs. As described in [38], the plant model
of the leg-i consisting of Nleg submodules is represented using
a single submodule as shown in Fig. 7. The output voltage of
this fictitious submodule is equal to the average output voltage
of submodules in the MMC leg; and its capacitor voltage is
equal to the average submodule capacitor voltages in the leg. E
represents the dc-link voltage and the steady-state total output
voltage of the leg; and Vcleg
iΣ
represents the sum of the voltages of
Nleg capacitors in the leg-i. Accordingly, the output voltage and
the capacitor voltage of the fictitious submodule are as shown
in Fig. 7. Thus, the objective of the leg balancing control is
to regulate the capacitor voltage of the fictitious submodule
of Fig. 7; this will ensure that the average capacitor voltage
of the leg (V̄cleg
i
) is controlled at the reference value (Vc∗ ).
 13434 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 37, NO. 11, NOVEMBER 2022

Fig. 9. Block diagram of the closed-loop system for leg balancing control
using ideal sensing through individual lines.

Fig. 8. Block diagram of the closed system for leg balancing control consid-
ering serial interface and the estimation scheme.

Applying the input–output power balance, the capacitor current

(ic ) of the fictitious submodule can be related to the submodule
current associated with the leg balancing control (iz ) using (16).
The submodules in a dc to ac MMC generate both dc and ac
Fig. 10. Block diagram of the closed-loop system for leg balancing control
components; and in order to achieve maximum utilization of the considering the serial transmission interface but excluding the estimator.
capacitor voltage, it is appropriate to maintain the average duty
E/Nleg
ratio of the submodule ( V iΣ /N leg
) at around 0.5; and hence, (16)
cleg
can be approximated to 0.5. This also implies that the reference For designing the compensator, the open-loop transfer func-
voltage of the average capacitor voltage of the submodules is to tion comprising of the plant, voltage sensor, filter, delay, and esti-
be chosen as Vc∗ = 2E/Nleg . mator is considered. The associated open-loop transfer function
that relates IzΔ and V̄cleg
i_est
is denoted by OLTFestimator (since it

 includes the estimator); and is expressed as
ic E/Nleg E
= = ≈ 0.5. (16)
iz iΣ /N
Vcleg leg
iΣ
Vcleg V̄cleg
i_est
s3 +s2 (ωf + τ1s )+s ωτsf + Kω
Cτs
f

OLTFestimator = = 0.5 K
.
IzΔ sC(s + C )(s+ωf )(s + 1
τs )
Fig. 8 shows the closed-loop block diagram of the leg bal- (17)
ancing controller where the plant model consists of the single
In order to understand the necessity of using the estimator from
capacitor of the fictitious submodule shown in Fig. 7. The
the perspective of the control system, the modeling of the voltage
plant model is highlighted in color. Accordingly, the individual
loop for the following two cases are also considered.
estimator for each submodule is replaced by a single estimator.
1) The sensed data from each submodule containing the
The low-pass filter and the delay due to serial communication
entire profile of the capacitor voltage are transmitted to
are also considered. The compensator is provided to account for
the processor through individual lines. In this case, the
losses within the converter and to ensure stable operation during
filter, delay, and estimator are not present. The control
transient condition. The dc circulating current reference consists
block diagram of this ideal approach is shown in Fig. 9.
of two terms IzΔ (output of compensator) and Izff (feed-forward
The associated open-loop transfer function that relates
term). The inner current controller is implemented to control
IzΔ and V̄cleg
i
is denoted by OLTFideal ; and is expressed
this current and is designed to be much faster than the outer
in (18).
voltage loop. Thus, as part of simplification, the current control
2) The sensed capacitor voltage of multiple submodules is
loop (CCL in Fig. 8) is shown as a unity gain during the design
transmitted serially through a common bus, but the estima-
of the voltage controller. The dc component of the circulating
tion algorithm is not used. The control system includes the
current component P ∗ /3E has already been precalculated and
filter and delay due to serial communication and is shown
provided as feed-forward (Izff ). Because of this feed-forward
in Fig. 10. The capacitor voltage control, in this case,
compensation, P ∗ /3E will not contribute to capacitor voltage
is based on the filtered data. The associated open-loop
dynamics and hence, it is subtracted within the plant model
transfer function that relates IzΔ and V̄cleg
i_filt
is denoted by
as shown in the figure. The resulting difference is equal to
OLTFfilter ; and is expressed in (19).
IzΔ (output of the compensator). The capacitor current Ic∗ can
iΣ
be obtained by multiplying the difference with E/Vcleg ≈ 0.5
using (16); and the product goes into the capacitor model. The V̄cleg
i
1
OLTFideal = = 0.5 (18)
capacitor current required by the estimator is extracted from the IzΔ sC
plant model as shown in the figure. From the aforementioned
discussion, it can be understood that the section marked within V̄cleg
i_filt
ωf /τs
OLTFfilter =
IzΔ
= 0.5 1 . (19)
the red box in Fig. 8 can be simplified into a single gain 0.5. sC(s + ωf )(s + τs )

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PURKAYASTHA AND BHATTACHARYA: SIMPLIFIED APPROACH FOR ACQUISITION OF SUBMODULE CAPACITOR VOLTAGES
Fig. 11. Frequency response of OLTFideal , OLTFfilter , and OLTFestimator .
Fig. 12. Open-loop frequency response of Fig. 8 with and without a PI
compensator.
The frequency responses corresponding to (17)–(19) are plot-
ted in Fig. 11 using the parameters listed in Table II.
Comparing the three plots, it is understood that the filter and
delay causes a large amount of phase lag in the system of Fig. 10.
The use of the estimator in Fig. 8 compensates for this phase lag
and the corresponding open-loop frequency response becomes
comparable to that of the ideal individual data transmission
approach of Fig. 9. This shows the importance of including the
estimator from the perspective of compensation of the phase
lag. The compensator in Fig. 8 is designed as a PI controller
with a transfer function of 0.3(1 + 2π/s) to achieve a gain
crossover frequency of 10 Hz for the compensated open-loop
system. Fig. 12 shows the open-loop frequency response before
and after the addition of the compensator.
V. EXPERIMENTAL RESULTS
The estimation scheme is experimentally verified in labora-
tory for a grid-connected MMC. The schematic of the experi-
mental setup is shown in Fig. 13. It consists of a dc to ac MMC
with four half-bridge submodules per arm. A three-phase diode
bridge rectifier having a filter capacitor at the output generates
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13435
Fig. 13. Schematic of the experimental setup.
Fig. 14. Sensed data acquisition system for each submodule in the experimen-
tal prototype.
the dc-link voltage of the MMC. The diode bridge rectifier
is fed from the three-phase ac supply through an autotrans-
former. The ac side of the MMC is connected to a scaled-down
three-phase 100 V, 50 Hz grid, which is obtained using an
autotransformer. The estimation scheme, control loops, modu-
lation [39], and sorting algorithm of the MMC are implemented
on a Digilent’s Genesys digital circuit development board with
Xilinx Virtex-5 field-programmable gate array (FPGA). The
parameters corresponding to the experimental prototype are
listed in Table III. Each submodule along with its associated
sensing interface circuit is implemented on a printed circuit
board (PCB). The interface between each submodule PCB and
the FPGA is represented in the form of a block diagram in
Fig. 14. It shows that the PCB contains voltage sensor and
analog-to-digital conversion circuits in succession. The output
of the analog-to-digital converter is the scaled-down version
of the actual capacitor voltage profile in digital format. This
signal is marked as vcsen . The low-pass filter is digitally encoded
within the FPGA rather than implemented on the PCB. This
is to ensure that the option of operating the MMC with the
sensed capacitor voltage vcsen (ideal case as in Fig. 9) remains
available. The purpose of using the filter is to eliminate the ac
components in the capacitor voltage. The output of the filter is
sampled at a rate of 100 samples per second and given a delay
of 0.01 s. The chosen sampling rate and delay are based on
the decided value of τs in Table II. The sampling and delay are
introduced intentionally to emulate the actual situation as shown
in Fig. 2, where the transmission over a common bus results in
a low sampling rate and introduces delay. This signal is marked
as vcfilt since it represents the filtered version. It represents the
signal that is supposed to reach the processing platform through
serial communication and is used by the estimation algorithm
along with the capacitor current (ic ) to reconstruct the capacitor
 13436
Fig. 15. Experimental result showing dynamic and steady performance of the
capacitor voltage.
TABLE III
CIRCUIT PARAMETERS OF THE EXPERIMENTAL PROTOTYPE
DC-link
DC-link f
voltage profile (marked as vcest ). Fig. 14 is implemented for each
submodule to estimate its capacitor voltage profile.
The grid-connected MMC of Fig. 13 is operated in a closed
loop using the block diagram shown in Fig. 6. The controller
and sorting algorithm use the capacitor voltage information
provided by the estimator; hence, the steady state and dynamic
performance of the capacitor voltage control must be verified.
Fig. 15 shows the waveform of the capacitor voltage (vcact ) of
one submodule, along with the scaled down versions vcsen , vcfilt ,
and vcest corresponding to Fig. 14. The signals vcsen , vcfilt , and
vcest are internal signals of the FPGA that are observed on the
oscilloscope using a digital-to-analog converter (DAC). A DAC
output of 1.25 V is equivalent to 100 V on the actual scale. The
MMC is initially supplying 1.2 kW to the grid at unity power
factor. At instant “T1 ,” the power supplied to the grid is reduced
to 750 W at 0.85 power factor (MMC supplies reactive power to
the grid); at instant “T2 ,” the power supplied is again increased to
1.2 kW at unity power factor. The reference value of the capacitor
voltage controller (Vc∗ ) is 50 V; and it can be seen from the plot
of vcact that the capacitor voltage of the submodule is controlled
at the specified reference, except for the expected oscillation at
“T1 ” and “T2 .” The operating conditions are also summarized in
Table IV. The transient in vcact is also reflected in the scaled down
signals vcsen , vcfilt , and vcest . Two sections (enclosed in red box),
corresponding to the two operating conditions, are magnified
(ZOOM-1 and ZOOM-2) and examined to see the steady-state
performance. For comparison, vcest and vcsen are plotted in the
same window. The observation that vcest fairly overlaps vcsen ,
demonstrates the estimator’s effectiveness in determining the
capacitor voltage profile. The figure also shows vcfilt , which is
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 37, NO. 11, NOVEMBER 2022
TABLE IV
SUMMARY OF TIME INTERVALS FOR FIGS. 15–18
Fig. 16. Experimental result showing the effect of using estimated voltage and
filtered voltage for sorting on the capacitor voltage ripple.
used by the estimator. As can be seen, the ac components are
not present in vcfilt . The ac components are reconstructed by the
estimator in vcest .
The balancing of the capacitor voltages in an arm using the
sorting algorithm requires knowledge of the entire capacitor
voltage profile. Thus, if the data acquisition system of Fig. 2
is used, the presence of estimator is necessary. To verify this
point, the following two scenarios are examined:
1) the estimator is present and the sorting is performed using
estimated voltage;
2) the estimator is absent and the sorting is performed using
filtered data that lacks ac component information.
The corresponding experimental result is shown in Fig. 16.
One submodule is chosen, and the capacitor voltage vcact , as well
as the associated vcest and vcfilt , are plotted. Until instant “T3 ,”
sorting of the submodules is done using the estimated capacitor
voltage. Thus, the capacitor voltage of the chosen submodule
vcact , as well as the associated vcest , are plotted. Between the
instants “T3 ” and “T4 ,” the sorting is carried out using the
filtered data that lacks ac component information; vcact and the
associated vcfilt , are plotted for this interval. Beyond instant “T4 ,”
the sorting is again performed using the estimated capacitor
voltage. ZOOM-1 and ZOOM-2 windows magnify two areas
of the display, corresponding to sorting using estimated voltage
and filtered data, respectively. When the sorting is done with
filtered data, the peak-to-peak ripple of the submodule capacitor
voltage nearly triples. This means that a greater capacitance
PURKAYASTHA AND BHATTACHARYA: SIMPLIFIED APPROACH FOR ACQUISITION OF SUBMODULE CAPACITOR VOLTAGES
Fig. 17. Effect of removing vcsen and K from the estimator.
value will be necessary to keep the capacitor voltage ripple
within a given limit. This indicates that when data are transmitted
across a common bus as shown in Fig. 2, the estimator is
essential. From Fig. 16, it can be said that in the absence of
ac component estimation, the capacitor voltage regulation can
happen at the cost of the increased capacitor voltage ripple. It
has been explained in Sections III-C1 and III-C2 that the use of
ic alone is not sufficient for estimation and the presence of vcsen
is necessary for obtaining the dc component. This is verified in
Fig. 17. The MMC is operated in open loop; the grid connected
to the ac side is removed and replaced by a three-phase passive
load box. Before instant “T5 ,” vcsen is present in the estimation
scheme and it can be seen that vcest and vcsen matches. At instant
“T5 ,” vcsen is withdrawn. As a result, the dc component in the
estimated capacitor voltage (vcest ) immediately collapses. This
phenomenon is magnified in ZOOM-1. At “T6 ,” vcsen is restored
and vcest resumes overlapping vcsen . In Section III-C1, it is also
shown that by using the feedback in Fig. 4, the integration drift
due to the presence of any dc offset in sensing can be avoided.
At instant “T7 ,” the feedback is intentionally removed, i.e., K is
made equal to 0. This makes the estimation scheme same as (2).
It is observed that the estimated voltage slowly starts deviating.
This is because there is always some offset, howsoever small,
in sensing. This phenomenon is called integration drift and is
magnified in ZOOM-2. At instant “T8 ,” the feedback is restored
and the integration drift is corrected.
The proposed scheme does not include capacitance estimation
to take care of the variation in submodule capacitance. Hence, the
performance of the estimation scheme is verified for the situation
when there is a mismatch between the actual submodule capaci-
tance and the one used in the estimator model. The nominal value
of capacitance used in the experimental setup is 1.5 mF, which is
also used in the estimator model. The capacitance of one of the
submodules is changed to 1 mF. Fig. 18 shows the comparison
between the sensed and estimated voltage for two submodule ca-
pacitors C1 = 1 mF and C2 = 1.5 mF. The dynamic performance
of the system is tested under different operating conditions as
listed in Table IV. The capacitor voltage regulation is stable.
Two sections corresponding to the two operating conditions are
expanded in Zoom-1 and Zoom-2 windows. It can be seen for C1
that there is a mismatch between vc1 est
and vc1
sen
. The maximum
mismatch is equal to 47 mV (marked in the figure) in the DAC
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13437
Fig. 18. Experimental result showing effect of mismatch between the actual
submodule capacitance and the capacitance used in the estimator model.
scale, which is equivalent to 3.76 V in the actual scale. This
mismatch occurs for a −33% deviation in capacitance, which
is quite an abnormally large deviation. For the capacitance C2
= 1.5 mF (original value), vc2
est
and vc2
sen
are also shown in the
figure.
VI. CONCLUSION
In this article, a strategy for simplifying the complexity asso-
ciated with the acquisition of sensed data from a large number
of submodules in an MMC has been proposed. This simplifica-
tion is proposed to be accomplished by employing a common
serial bus for dc component transmission and an estimator to
reconstruct the ac components within the processing platform.
The mathematical model of the acquisition system and estimator
has been studied in detail considering a low sampling rate and
the delay associated with serial communication. The effect of
using the estimated capacitor voltage on the closed-loop control
is investigated. Using frequency response analysis, it is shown
that the phase lag introduced due to the filter and serial data
transmission is compensated by the estimator. The importance
of the estimator for sorting-based capacitor voltage balancing
of the MMC is demonstrated experimentally. The experimental
result showing the estimator’s effectiveness in determining the
complete capacitor voltage profile is presented. The closed-loop
performance of the system under sudden change in operating
condition is also tested. The performance of the estimation
scheme is also experimentally verified under variation in sub-
module capacitance.
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Bishwajyoti Purkayastha received the B.Tech. de-
gree in electrical engineering from the West Bengal
University of Technology, Kolkata, India, in 2012,
and the M.E.E. degree in electrical machines from
Jadavpur University, Kolkata, in 2014. He is currently
working toward the Ph.D degree with the Electrical
Engineering Department, Indian Institute of Technol-
ogy, Kharagpur, India.
His research interest includes the application of
modular multilevel converter in railway traction.
Tanmoy Bhattacharya (Member, IEEE) received the
B.E. degree in electrical and electronics engineering
from the National Institute of Technology, Tiruchi-
rapalli, India, in 2002, and the M.Sc. (Eng.) and
Ph.D. degrees in power electronics from the Indian
Institute of Science, Bangalore, India, in 2005 and
2009, respectively.
He also worked as a Research Fellow with the
National University of Singapore, Singapore. He is
currently working as an Assistant Professor with the
Electrical Engineering Department, Indian Institute
of Technology, Kharagpur, India. His research interests include hybrid electric
vehicles, traction drives, wind, solar hybrid systems, renewable powered micro-
grids, etc.