IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 66, NO.

8, AUGUST 2019 3227

Analysis and Design of Cyclic Switched-Capacitor

DC–DC Converters
Kishalay Datta, Vinod Menezes, Member, IEEE, and Shanthi Pavan , Fellow, IEEE

Abstract— We introduce the cyclic switched-capacitor dc–dc

converter for single-input multiple-output power delivery. We
focus on applications in stacked voltage domain (SVD)-based
systems, and show that the cyclic architecture is robust to
load current mismatches. We analyze such converters and give
intuition for their power losses. We give experimental results from
an SVD based power management integrated circuit (PMIC),
designed and fabricated in a 130 nm CMOS technology. The
PMIC is a combination of a 2/3 stage reconfigurable cyclic SC
dc–dc converter and a linear regulator. It can drive 3×3 mA loads
with the input supply voltage varying from 2.35–3.65 V.
Index Terms— DC-DC power converters, switched capacitor
circuits, single-input multiple-output, voltage regulators, charge
recycling, voltage stacking, power management.

I. I NTRODUCTION

C OIN-CELL or cylindrical batteries, which yield voltages

from 2–3.6 V, are required to power digital circuitry
whose supply voltage requirements are in the range 0.8–1.4 V.
Linear regulators are not efficient due to the large drop-out
voltage. Inductive buck dc-dc converters are efficient, but need
external inductors that increase board footprint and cost. More-
over, tampering of external inductors is a potential security
concern. DC-DC converters based on switched-capacitors [1]
are a possible alternative. Unfortunately, they can only achieve
step-down fractions that are ratios of whole numbers [2]. This
can be addressed by using linear regulators in tandem, with
some loss in efficiency. More recently, DC-DC converters with
large power densities, and flying loads [3] have been reported.
However, they have limited step-down ratios, and require
specialized flying-domain level shifters. Hybrid converters that
combine package or PCB inductances and capacitances [4], [5]
have also been explored. These high-power density converters
have good efficiency for loads greater than 0.5 A, but their
efficiency rapidly falls below 40% for lighter loads.
If the low-voltage load can be partitioned into largely equal
units, they can be stacked so that they can be directly driven by
the battery. This is the principle behind stacked voltage domain
(SVD) based power delivery [6]–[12]. SVD power delivery is
particularly effective in a class of hardware-safety and high-
reliability systems called lock-step micro-controllers [8], [13].
Manuscript received December 12, 2018; revised February 17, 2019 and
March 19, 2019; accepted March 21, 2019. Date of publication April 25,
2019; date of current version July 3, 2019. This paper was recommended by
Associate Editor A. Fayed. (Corresponding author: Shanthi Pavan.)
K. Datta and S. Pavan are with the Department of Electrical Engineering,
Indian Institute of Technology Madras, Chennai 600036, India (e-mail:
shanthi@ee.iitm.ac.in).
V. Menezes is with Texas Instruments India Ltd., Bengaluru 560093, India.
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2019.2907309
1549-8328 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Fig. 1. (a) Principle of stacked voltage domain (SVD) power delivery.
(b) SVD regulator using linear voltage regulators.
They are used in many automotive, industrial and mission-
critical applications where hardware safety is an integral
requirement. In these systems, two or more processors execute
the same set of instructions, thereby ensuring reliability by
redundancy. Under normal circumstances, these processors are
in the same state in every clock cycle, hence the name lock-
step. An error in a particular processor will manifest as a
difference in outputs of these multiple identical units, thus
flagging an error. In a three-processor system, for instance,
simple majority voting can greatly reduce the probability of
a defective operation. In this work, the application space
focused is lock-step for ultra-low power industrial systems.
An individual processor core typically consumes an active
mode current per clock frequency of 150 μA/MHz [14]. The
processors consume about 3 mA worst case average current
for the target applications.
Since multiple identical processors operate the same pro-
gram with the same inputs, it follows that their nominal current
draws are identical. In such cases, SVD power delivery, where
the processors are stacked becomes attractive [8]. An example
three-processor stack is shown in Fig. 1(a). Each processor
operates with a supply of VL . The voltage of the battery
is 3 VL , thereby allowing us to stack the processors directly
across it. The role of the SVD regulator is to ensure that VL1
and VL2 equal VL and 2 VL respectively. If the processors draw
identical currents, the regulator does not need to source/sink
any current, thereby ensuring a power efficiency of virtually
100 %. In practice, the load currents drawn by the processors
(denoted by I1 , I2 , and I3 ) will be largely equal, and the
3228 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 66, NO. 8, AUGUST 2019
regulator has to only process the (small) difference between the
currents. Thus, SVD power delivery achieves high efficiency
with equal loads, which are also referred to as balanced loads.
A simple way of realizing the SVD regulator is to use
push-pull linear regulators, as shown in Fig. 1(b) [6]. This
results in excellent efficiency for balanced stacks, where I1 ≈
I2 ≈ I3 . Unfortunately, power efficiency is degraded when
the loads become unbalanced, as explained below. Consider
a load stack where I2 = I3 = 0, and I1 = 0. In such
a situation, both the linear regulators L R1 and L R2 have
to source all of I1 through them. This is equivalent to a
conventional linear regulator providing a dropout of 2 VL from
the battery to drive a current I1 , resulting in an efficiency of
33 %. It is thus seen that extremely unbalanced loads make the
linear-regulator-based SVD power management system very
inefficient. In the context of our intended application of lock-
step microprocessors, imbalanced loads can occur in the case
of errors; when one of the processors shuts down, for instance.
Moreover, due to process variations, there could be worst case
±10% mismatch among the individual processor currents. In
this work, that translates to worst case ±250μA [14].
A more power-efficient approach to realizing the SVD
regulator for Fig. 1(a) is to use a single-input, multiple-
output ladder switched-capacitor dc-dc (SCDCDC) converter
[7], [9]–[12]. While the ladder SCDCDC converter-based SVD
regulator is an improvement over the linear-regulator-based
solution, it has several drawbacks. The aim of this work is
to address these disadvantages. Our solution is the cyclic
switched capacitor dc-dc converter, which robustly tackles the
biggest limitation of SVDs, namely, load current mismatch.
The rest of the paper, which introduces and analyzes the
cyclic SCDCDC converter, is organized as follows. Section II
reviews the operation of the ladder SCDCDC multiple-output
converter, and discusses its limitations. Section III describes
the principle behind cyclic dc-dc conversion, and derives
expressions for its output resistance in the slow-switching
limit. The loss-mechanisms in the converter are also discussed.
Section IV gives the design details of a power management
integrated circuit (PMIC) designed to deliver power to three
loads over a wide range of battery voltages. The PMIC uses a
reconfigurable 2- or 3-stage cyclic SCDCDC converter, along
with a programmable load configuration. Experimental results
from the PMIC, designed in a 130 nm CMOS process, are
given in Section V. The PMIC achieves a peak efficiency of
about 99% when driving a balanced load, while switching at
a low frequency of 1 kHz. Section VI concludes the paper.
II. SVD P OWER D ELIVERY W ITH A L ADDER
SCDCDC C ONVERTER
The switched-capacitor ladder converter is an attempt at
addressing the inefficiency of a LDO-based SVD regulator [7],
[9]–[12]. Fig. 2(a) shows a three-level ladder converter driving
stacked loads that draw currents I1 , I2 , and I3 . Cd1 , Cd2 ,
and Cd3 are decoupling capacitors. In our application (lock-
step microprocessor system), these decoupling capacitors are
the inherent parasitic capacitances presented by the load,
and are nominally equal to 10 nF. C F 1 and C F 2 are the
Fig. 2. (a) Stacked voltage domain power delivery using a switched-
capacitor ladder converter. (b) Circuit to calculate the slow-switching limit
output resistance.
flying capacitors, and are (much) smaller than the decoupling
capacitors. The switching frequency is denoted by f s . Under
no-load conditions, it can be shown [1] that VL1 = V B /3 and
VL2 = 2V B /3.
The average steady-state voltages VL1 and VL2 at the
outputs depend on the load currents, the output resistances
in the slow-switching limit, and the cross-coupling between
the two ports. In the simplified analysis that follows, we
assume that the switches are ideal. The output resistance
looking into the port VL1 in the slow-switching limit, assuming
Cd1 = Cd2 = Cd3 = Cd , C F 1 = C F 2 = C F , and Cd  C F ,
is determined using the circuit of Fig. 2(b) [15], [16]. VT is
a dc test voltage. Denoting the average current drawn from
the test voltage by IT , the output resistance can be obtained
as rout = VT /IT . The steady-state analysis of the network of
Fig. 2(b) (omitted here due to space constraints) yields the
following.
a. The average current drawn from the test voltage source,
if Cd  C F , is given by IT = (9/5) f s C F VT . The output
resistance presented at port VL1 of the ladder of Fig. 2(a)
is thus given by rout = 5/(9 f s C F ).
b. The voltage developed at the upper output port in
Fig. 2(b) when VT is applied at the lower port is 0.8 VT .
The implication of this is the following. If a dc current
IT was drawn from the lower port (with the upper
port being unloaded), its voltage would drop by IT rout .
Consequently, the voltage at upper port would also drop
by 0.8 IT rout .
c. Observing that Fig. 2(b) is symmetric with respect to
the lower and upper ports, it is apparent that the output
resistance looking into the upper port is also 5/(9 f s C F ).
Likewise, applying a test voltage VT at the upper port
would cause a voltage shift 0.8 VT at the lower port.
Using the observations above, we are now in a position to
determine the average steady-state voltages VL1 and VL2 in the
ladder converter of Fig. 2(a). The lower output port supplies a
current (I1 − I2 ), while the upper output port supplies (I2 − I3 ).
DATTA et al.: ANALYSIS AND DESIGN OF CYCLIC SWITCHED-CAPACITOR DC–DC CONVERTERS 3229

Fig. 3. Simulated output voltages of a ladder SCDCDC converter with

V B = 3 V, C F = 1.5 nF, C D = 10 nF and f s = 3 MHz. I1 = I2 = I3 = 0
for t < 20 μs. For t > 20 μs, I1 = 3 mA, I2 = 2.3 mA and I3 = 1 mA.

We thus have
VB 5 (I1 − I2 ) 5 (I2 − I3 )
VL1 = − − 0.8 Fig. 4. Operating principle of the cyclic switched-capacitor dc-dc converter.
3 9 fs C F 9 fs C F
  
effect of current in upper port
2V B 5 (I1 − I2 ) 5 (I2 − I3 ) one phase. This is remedied by adding another flying capacitor
VL2 = − 0.8 − . (1)
3

9 fs C F
 
9 fs C F C F 3 (and a corresponding third phase φ3 ), ensuring that one
effect of current in lower port of three flying capacitors are connected to the battery in
any phase. To explain the principle of operation, we use
The expressions of (1) are confirmed by simulations of a
the example three-level cyclic converter shown in Fig. 4.
ladder SCDCDC converter with V B = 3 V, C F = 1.5 nF,
C F 1 , C F 2 , C F 3 are the three flying capacitors, which are all
C D = 10 nF and f s = 3 MHz.1 These choices yield rout =
nominally identical, and equal to C F . The stacked loads
123 . I1 = I2 = I3 = 0 for t < 20 μs, resulting in VL1 = 1 V
connected across the battery draw constant currents I1 , I2 and
and VL2 = 2 V. At t = 20 μs, load currents I1 = 3 mA,
I3 , and have decoupling capacitors Cd1 , Cd2 , Cd3 connected
I2 = 2.3 mA and I3 = 1 mA are turned on. As a result, VL1
across them. I B denotes the current drawn from the battery.
and VL2 deviate from their no-load values, as shown in Fig. 3.
The switching frequency is f s .
Using (1) to determine the steady-state average voltages, we
The cyclic SCDCDC converter operates in three phases,
obtain VL1 = 785 mV and VL2 = 1.77 V, which is in good
denoted by φ1 , φ2 and φ3 . During phase φ1 , C F 1 , C F 2 and
agreement with simulation results.
C F 3 are connected across loads I1 , I2 and I3 respectively. In
The ladder SCDCDC converter has two drawbacks. Both
the next phase φ2 , the flying capacitors are shifted down by
can be traced to the fact that the flying capacitor C F 1 (see
one position, with C F 2 , C F 3 and C F 1 connected across I1 , I2
Fig. 2(a)) draws current from the battery only during φ1 .
and I3 respectively, as shown in Fig. 4. Thus, the capacitors
This not only increases the output resistance of the converter,
are shifted down by one position every clock phase, thereby
but also results in a “spikier” current being drawn from the
cycling each flying capacitor across every load. Hence the
battery. A consequence of the high peak-to-average ratio of
name cyclic SCDCDC converter.
the battery’s current draw is reduced battery lifetime. The
We now determine the voltages VL1 and VL2 in steady state,
root cause of the problems described above is that the battery
under no-load conditions, namely I1 , I2 , I3 = 0. Fig. 4 then
is “idle” during φ2 ; i.e, none of the flying capacitors are
reduces to Fig. 5. We denote the voltages on Cd1 , Cd2 and
connected to it during that phase. If current was drawn from
Cd3 in φ1 of the n t h clock cycle by v 1 , v 2 and v 3 respectively.
the battery even in its idle phase, the output resistance should
These voltages must satisfy
reduce. Further, a more uniform current would be drawn from
the battery. This is the basic idea behind the cyclic SCDCDC v1 + v2 + v3 = VB . (2)
converter introduced in the next section.
In φ2 , the capacitors are cycled, meaning that C F 2 is in
III. C YCLIC S WITCHED -C APACITOR DC-DC C ONVERSION parallel with Cd1 etc., as shown in Fig. 5. Straightforward
analysis shows that the voltages across Cd1 , Cd2 and Cd3 can
In this section, we introduce the cyclic switched-capacitor be expressed as
dc-dc (SCDCDC) converter. As discussed in Section II, the
ladder SCDCDC converter lets the battery be “idle” during v 1,φ2 = v 1 + k1 (v 2 − v 1 )
1 The values of C and f are chosen to make a fair comparison with the v 2,φ2 = v 2 + k2 (v 3 − v 2 )
F s
cyclic SCDCDC converter introduced in the next section. v 3,φ2 = v 3 + k3 (v 1 − v 3 ) (3)
3230 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 66, NO. 8, AUGUST 2019
Fig. 5. Determining capacitor voltages under steady-state operation: the
voltages in φ1 of the n th and (n + 1)th clock cycles must be identical.
where k1 , k2 and k3 are constants depending on the particular
values of the C F 1,2,3 and Cd1,2,3. Proceeding in a similar
manner, the capacitor voltages during φ1 of the (n +1)t h clock
cycle can be determined to be those on the left-hand-side of
the equations below, where the coefficients m ab are constants
that depend on C F 1,2,3 and Cd1,2,3 . Since the system is in
steady-state, the capacitor voltages during φ1 of the (n + 1)t h
clock cycle must be the same as those in the n t h clock cycle,
namely v 1 , v 2 and v 3 . We thus have
v 1 + m 11 (v 2 − v 1 ) + m 12 (v 3 − v 2 ) + m 13 (v 1 − v 3 ) = v 1
v 2 + m 21 (v 3 − v 2 ) + m 22 (v 1 − v 3 ) + m 23 (v 2 − v 1 ) = v 2
v 3 + m 31 (v 1 − v 3 ) + m 32 (v 2 − v 1 ) + m 33 (v 3 − v 2 ) = v 3 .
It is evident that v 1 = v 2 = v 3 is the solution to the system
of equations above. Further, since v 1 +v 2 +v 3 = V B , it follows
that in steady state,
VB
v1 = v2 = v3 = . (4)
3 by the test voltage. The total charge supplied by VT during
We thus see that the output voltages VL1 and VL2 are given
by V B /3 and 2 V B /3, irrespective of the values of the flying
and decoupling capacitors.
A. Output Resistance
Next, we determine the output resistance of the cyclic
SCDCDC converter, assuming ideal switches. All the flying
capacitors are identical, and equal to C F . To find the output
resistance of the “lower” output port, we apply a test voltage
VT at the port, and find the average current drawn from
this source in steady-state [2], [15], [16]. Fig. 6 shows the
state of the converter in the n t h clock cycle, where n is
Fig. 6. Steady-state operation of the cyclic SCDCDC converter when a test
voltage VT is applied to the lower output port. Analysis shows that v a = 0
in steady state.
assumed to be so large that steady state has been reached.
We denote the potential of the bottom-plate of C F 3 during
φ1 as v a . Straightforward analysis using charge conservation
shows that in φ2 , the potential of the bottom plate of C F 1 will
be −(1/2)v a . It immediately follows that the bottom plate of
C F 2 in φ3 will be −(1/2)(−v a /2) = (1/4)v a .
Continuing the line of reasoning above, we see that C F 3 ’s
bottom-plate potential in φ1 of the (n + 1)t h clock cycle
should be −(1/2)(v a /4) = −(1/8)v a . Since we are assuming
steady-state operation, the voltage C F 3 ’s bottom-plate in phase
φ1 of the n t h and (n + 1)t h clock cycles must be identical.
This therefore means that v a = −(1/8)v a , which leads us to
conclude that v a = 0.
During the transition from φ1 → φ2 , the charge supplied
by the test voltage VT is comprised of two components. The
first is the charge supplied to C F 2 . During φ1 , the charge on
C F 2 ’s top plate is -C F VT . (Recall that all flying capacitors are
identical and equal to C F ). During φ2 , this charge becomes
+C F VT , indicating the VT has to supply 2C F VT . The second
component of charge supplied by VT is to C F 3 . In φ1 , the
charge on C F 3 is zero, since v a = 0. In phase φ2 , the bottom-
plate of C F 3 has a charge C F VT , which needs to be supplied
the φ1 → φ2 transition is thus seen to be 3C F VT . In a similar
manner, it is easy to see that VT supplies a charge 3C F VT
during φ2 → φ3 and φ3 → φ1 transitions.
From the discussion above, we see that the total charge
drawn from the test voltage (in steady state) during one clock
cycle (time duration of 1/ f s ) is given by 9C F VT . The output
resistance looking into the lower port is thus given by
1
rout = . (5)
9 fs C F
Since we have assumed ideal switches, rout above corre-
sponds to the so-called slow-switching limit. Interestingly, the
DATTA et al.: ANALYSIS AND DESIGN OF CYCLIC SWITCHED-CAPACITOR DC–DC CONVERTERS
Fig. 7. Simulated output resistance of a cyclic SCDCDC converter with
C F = 1 nF versus switching frequency. Two cases of C D = 1 nF and C D =
10 nF are shown. The corresponding plots for the ladder converter, where
C F = 1.5 nF are also shown for comparison.
Fig. 8. Steady-state output voltages of cyclic SCDCDC while driving SVD
loads.
steady-state voltage at the “upper” output port in response to
an excitation at the lower port is zero.
Next, we evaluate the output resistance looking into the
upper port. We proceed in a manner similar to that in Fig. 6.
We omit the details here due to space constraints. It turns out
that rout = 9 f s1C F for the upper port too. However, the change
in the voltage at the lower port, due to test voltage VT in the
upper port turns out to be VT . This surprising result seems
reasonable due to the following. The flying capacitors are
“rotating” from top-to-bottom; the upper and lower ports are
therefore not equivalent. Fig. 7 validates (5), and compares the
output resistances of cyclic and ladder architectures. The total
flying capacitance for both cases is kept the same. This shows
that the output resistance of the cyclic SCDCDC converter is
about 3 times lower than that of the ladder.2
Fig. 8 shows a cyclic SCDCDC converter driving three
loads. The effective current supplied by the upper rail is
(I2 − I3 ), while the lower rail supplies (I1 − I2 ). The average
2C
d2 in a ladder converter does behave like a flying-capacitor and influences
the output resistance in the slow-switching limit. This is why rout for the
ladder converter changes with the value of C D in Fig. 7.
3231
Fig. 9. Simulated output voltages of a cyclic SCDCDC converter with V B =
3 V, C F = 1 nF, C D = 10 nF and f s = 2 MHz. I1 = I2 = I3 = 0 for
t < 20 μs. For t > 20 μs, I1 = 3 mA, I2 = 2.3 mA and I3 = 1 mA. The
corresponding waveforms (same as those in Fig. 3) for the ladder converter,
where C F = 1.5 nF and f s = 3 MHz, are also shown for comparison.
voltage of the upper rail is given by
2V B 2V B (I2 − I3 )
VL2 = − (I2 − I3 )rout = − . (6)
3 3 9 fs C F
This is because a stimulus in the lower rail does not cause
any steady-state change in the voltage of the upper rail. The
potential of the lower rail, on the other hand, is given by
VB V B (I1 − I3 )
VL1 = −(I2 − I3 )rout −(I1 − I2 )rout = − .
3 3 9 fs C F
(7)
The deviation of VL1 from its no-load value V B /3 consists of
two components. The first is the drop due to the change in
VL2 , which is (I2 − I3 )rout , and the second is the reduction
due to its own load current.
Fig. 9 shows the simulated output voltages of a cyclic
SCDCDC converter with C F = 1 nF, C D = 10 nF and a
switching frequency f s of 2 MHz. The converter is operated
with a battery voltage of 3 V. For t < 20 μs, the converter
is under no-load conditions, so that I1 = I2 = I3 = 0.
At t > 20 μs, the loads are turned on with I1 = 3 mA,
I2 = 2.3 mA and I3 = 1 mA. rout = 1/(9 f s C F ) turns out
to be 55.5 . For t < 20 μs, VL1 and VL2 are 1 V and 2 V
respectively, as expected. After the loads are turned on, the
steady-state value of VL1 should, by our analysis, deviate from
1 V by about 55.5 · 2 mA = 111 mV. VL2 , on the other hand,
should reduce by 55.5 · 1.3 mA = 70 mV. Notice that these
estimates are in good agreement with the simulation results
shown in Fig. 9. The corresponding voltage waveforms (those
in Fig. 3) with a ladder SCDCDC converter are also shown
for comparison. We see that the cyclic topology outperforms
the ladder-based approach, for the same amount of flying
capacitance (3 nF in each case), and the same number of
switching events per unit time.
B. Battery Current
The cyclic SCDCDC converter also results in a very
desirable waveform for the current drawn from the battery.
3232 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 66, NO. 8, AUGUST 2019
Fig. 10. Simulated battery currents for comparison of ladder (blue) and cyclic
(red) SCDCDCs. V B = 3.6 V and internal resistance of battery is 10 . For
cyclic, C F = 1 nF, C D = 10 nF and f s = 2.5 MHz. I1 = 3 mA, I2 = 2.3 mA
and I3 = 1 mA. For the ladder converter, C F = 1.5 nF and f s = 8.3 MHz.
To see this, we first assume that the decoupling capacitors
are small in relation to the flying capacitors, so that they
can be approximated to zero. We now examine the various
currents and voltages in each phase, assuming steady-state
operation. From Fig. 4, we see that the currents through the
flying capacitors C F 1 , C F 2 and C F 3 during phase φ1 are given
by I B − I1 , I B − I2 , and I B − I3 respectively. Denoting the
voltages across the flying capacitors by v 1 , v 2 and v 3 , we see
that v 1 (t) + v 2 (t) + v 3 (t) must equal the battery voltage V B .
Since the capacitor currents are proportional to the derivatives
of their voltages, it follows that the sum of the flying capacitor
currents are constrained according to
(I − I ) + (I B − I2 ) + (I B − I3 ) =0
 B  1      
current through C F1 current through C F2 current through C F3
resulting in
1 switched-capacitor dc-dc conversion. The PMIC is geared to
IB =
(I1 + I2 + I3 ) . (9)
3 operate in SVD applications, as mentioned in the introduction.
From the discussion above, we see that the cyclic SCD-
CDC converter draws a constant battery current, even when
the decoupling capacitors are zero. Our first-order analysis
assumes instantaneous switching of the flying capacitors; a
practical converter will employ break-before-make switching,
during which the decoupling capacitors supply current to the
load, resulting in small current-spikes through the battery. In
contrast, the ladder SCDCDC converter draws current from the
battery in large spikes (since the flying capacitor is connected
to the battery only during one phase), reducing battery life.
Fig. 10 compares the battery current waveform in a cyclic
converter with that of a ladder converter. Here, the battery is
assumed to have V B = 3.6 V and an internal resistance of
10 . The latter is chosen to emulate the current compliance
of typical batteries [17] used in the target applications for this
work.
C. Loss Mechanisms
Losses, which degrade the power efficiency of a cyclic
SCDCDC converter, are due to the following:
a. Parasitic bottom-plate capacitance of the flying capac-
itors: An integrated capacitor is accompanied by a
parasitic bottom-plate capacitance to ground. In the
130 nm CMOS process technology used in this work,
the parasitic capacitance is α = 1.6% of the intended
capacitor. As the flying capacitors keep changing their
position with phase, the bottom-plate parasitics get
charged/discharged, resulting in power loss. During
successive phases, the bottom-plate capacitor has the
voltages 0 → 2V B /3 → V B /3 → 0 → · · ·. A straightfor-
ward calculation shows that the loss due to the three
bottom-plate capacitors is α C F V B2 f s .
b. Switch resistance and gate-drive: Power is lost due to
dissipation in the switches. To reduce this, the switches,
realized using MOS transistors, should be sized so as to
have a small resistance. Attempting to increase their size,
however, results in increased gate capacitance, which in
turn increases the power needed to drive the switches.
Switch resistance, therefore, has to be chosen as a balance
between I 2 R and switching loss.
c. Charge-sharing between flying and decoupling capaci-
tors: In the presence of mismatched loads, the voltage
across each of the decoupling capacitors is different,
as analyzed earlier in this section. Thus, the voltage
across the flying capacitors changes from phase to phase,
resulting in a loss of efficiency. Space constraints prevent
a detailed analysis here, but it can be shown that this loss
is bounded by 3C F V 2 fs , where V is the worst-case
deviation of the voltage across any of the load currents
from their nominal values.
(8) IV. D ESIGN OF AN SVD-BASED PMIC FOR A
W IDE I NPUT VOLTAGE R ANGE
In this section, we describe the design of a test chip to verify
the efficacy of a power management solution based on cyclic
The loads need to have a supply voltage which is 1.2 V±10%,
and draw a worst-case current of 3 mA. The test chip described
here supports a battery voltage that can vary from 2.35-3.65 V.
To accommodate such a range of input voltage, the loads can
be stacked into two or three levels.
Fig. 11(a) shows the architecture of the PMIC test chip. It
operates in three modes, depending on the battery voltage,
as shown in part (b) of the figure. The mode selector is
responsible to sense the battery voltage and automatically
reconfigure the PMIC to the appropriate mode. It compares
appropriate fractions of the battery voltage to an (external)
bandgap reference voltage to generate control signals that
configure the operational modes of the regulator and load
assemblies. The comparators and resistor ladder in the mode-
selector circuitry consumes a current less than 20 nA. They
occupy about 0.1 mm2 resulting in on-chip area overhead of
2.4% of the overall active area.
A. Regulator Assembly
Fig. 12(a) shows the architecture of the regulator assembly.
It consists of a 2/3 level cyclic SCDCDC converter and a
linear regulator. Depending on the mode of operation, the
DATTA et al.: ANALYSIS AND DESIGN OF CYCLIC SWITCHED-CAPACITOR DC–DC CONVERTERS
Fig. 11. (a) Block diagram of the PMIC test chip that incorporates cyclic
switched-capacitor dc-dc conversion for a SVD application. (b) Battery-
voltage range and the modes of operation.
Fig. 12. (a) Regulator and (b) load assemblies.
cyclic SCDCDC converter can be programmed to operate with
two or three levels. In the two-level mode, a clock generator
uses the master clock (clk in Fig. 12(a)) to generate two non-
overlapping clock phases with 50% duty cycle. For three-level
operation, three 33% duty-cycle non-overlapping signals are
generated. Based on the mode of operation, the linear regulator
can be enabled and connected in cascade with the cyclic
SCDCDC module. When enabled, the regulator maintains
2.4 V at its output. Due to time constraints of the test-chip
schedule, the load regulation loop could not be implemented.
Hence, the variable frequency clock input is provided off-chip.
We give more details about the clock input in section V.
Fig. 13 shows the simplified schematic of the three-level
cyclic SCDCDC converter. It consists of three identical switch-
capacitor unit cells, each driven by appropriate clock phases.
3233
Fig. 13. Simplified schematic of the 3-level cyclic SCDCDC converter.
B. Load Assembly
Fig. 12(b) shows the load assembly. Three loads are con-
nected to each other through a set of switches. When the PMIC
is operating in md3, the loads are arranged as a 3-level stack.
The loads are arranged as a 2-level stack in both md1 and
md2. Hence, the logical OR of md1 and md2, md1 + 2, is
used as the enable signal. In the 2-level stack, I2 forms the
upper level while the parallel combination of I1 and I3 form
the lower level.
C. PMIC Operation in Different Modes
Fig. 14 shows the three modes of operation. When 3.65 V ≥
VBAT > 3.5 V, the PMIC operates in md3, shown in Fig. 14(a).
The loads are arranged as a three-level stack, and the SCD-
CDC is operated as a three-level cyclic converter. The linear
regulator is disabled.
The PMIC operates in md2 when the battery voltage goes
lower (3.5 V ≥ VBAT > 2.5 V), and it is no longer possible to
configure the loads as a three-level stack. It is also not possible
to operate them as a two-level stack, since the voltage across
the loads can then exceed the limit of safe operation (1.32 V).
Thus, the linear regulator is turned on (see Fig. 14(b)), to
provide the requisite drop-out voltage, so that the top rail of
the 2-level stack is set to 2.4 V.
When 2.5 V ≥ VBAT > 2.35 V, the input voltage becomes
sufficiently low, so that a two-level load stack can be reliably
operated. This corresponds to md1 (Fig. 14(c)), where the
linear regulator is disabled, and the uppermost rail is directly
connected to the battery.
The component values of the SCDCDC converter were
chosen according to the following.
• The widths of the switch transistors were chosen so that
the worst-case voltage drop across them does not exceed
50 mV.
• Upon fixing switch sizes, the efficiency of the con-
verter can be maximized by reducing the switching
3234 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 66, NO. 8, AUGUST 2019
Fig. 14. Equivalent views of the SVD based PMIC in (a) md3 (b) md2 and
(c) md1.
frequency ( f s ). A lower f s not only reduces the power
needed to drive the gates of the switches, but also
reduces power lost in the switched parasitic of the flying
capacitors.
• The maximum area available for the flying capacitors and
the peak ripple voltage tolerable across the loads constrain
the lowest f s that can be used.
D. PMIC Efficiency in Various Operating Modes
The power efficiency of the PMIC is mode and load depen-
dent. In md3, where the loads are connected as a three-level
stack, a very high efficiency should be expected if the load
is balanced. With such a load stack, the switching frequency
can be reduced to a very low value, since the flying capacitors
only need to compensate for any (small) mismatch between
load currents.
Unbalanced load-stacks cause a reduction in efficiency due
to the increased conduction losses, and higher switching loss
(due to the increased f s needed to maintain the voltages across
the loads).
In md2, where the linear regulator is used to set the
voltage across the two-level stack to 2.4 V, efficiency is further
limited by the drop-out voltage of the regulator. In md1, the
efficiencies are comparable to md3 since the linear regulator
is turned off.
Fig. 15. Die micrograph of the fabricated PMIC.
V. E XPERIMENTAL R ESULTS
A PMIC test-chip was designed to test the cyclic SCDCDC
principle. It was fabricated in a 130 nm CMOS technology.
The die photograph is shown in Fig. 15. The area of the test
chip, including pads, is 6.25 mm2. The total flying capacitance,
which is about 2.96 nF, occupies an area of 1.7 × 1.5 mm2.
These capacitors are realized as MIM structures due to their
low bottom-plate parasitic capacitance (α ≈ 0.016). The active
area occupied by the PMIC is about 4 mm2 .
A peak power density of 2.7 mW/mm2 was achieved. The
low power-density versus good power-efficiency was the trade-
off faced in the design while choosing MIM capacitors. The
use of high-density thin-oxide MOS capacitors having low
bottom-plate parasitic was avoided due to reliability issues
during start-up of the PMIC. Alternatively, technology nodes
with ferro-electric capacitors could be used [18] to attain
good capacitance density with very low bottom-plate parasitic.
Unfortunately, at the time of the design, there was no test-chip
shuttle available for such technology nodes.
This PMIC is intended to power a set of three micro-
controller cores running in a lock-step fashion. The parasitic
supply-ground capacitances of the micro-controller cores, esti-
mated to be about 10 nF each, also serve as the decoupling
capacitors C D . However, since the micro-controllers were not
fabricated on the test chip, external 10 nF capacitors were
used during characterization. The worst-case current draw
of the cores is about 3 mA, which is mimicked off-chip by
programmable resistor banks and/or ring-oscillator loads.
The clock input to the PMIC (clk in Fig. 12(a)) was
provided using an external function generator. The frequency
was manually set to keep the voltages across the loads to
within 10% of their nominal values.
Several experiments were run to demonstrate the PMIC’s
performance. In the first test, I1 = 1.7 mA, I2 = 1.5 mA and
I3 varied. The switching frequency is set to 2.8 MHz. Recall
that each flying capacitor is C F ≈ 1 nF. Fig. 16 shows the
DATTA et al.: ANALYSIS AND DESIGN OF CYCLIC SWITCHED-CAPACITOR DC–DC CONVERTERS
Fig. 16. Cross-regulation due to a change in I3 . VL2 (blue) and VL1 (pink)
jump down by 110 mV and 85 mV respectively.
Fig. 17. Cross-regulation due to a change in I2 . VL2 (blue) and VL1 (pink)
jump by 120 mV and -15 mV respectively.
Fig. 18. Cross-regulation due to a change in I1 . VL2 (blue) and VL1 (pink)
jump up by 10 mV and 120 mV respectively.
measured VL1 and VL2 waveforms as I L3 changes from 2.5 mA
to 0 and back again to 2.5 mA. We see that they jump down by
85 mV and 110 mV respectively, in response to a 2.5 mA step
in I3 . Equations (6) and (7) predict that the changes should
be equal, and about 100 mV. The deviation from the values
predicted by our analytical expressions is due to the series
resistance of the switches.
Next, we keep I1 and I3 fixed at 1.7 mA and 1.5 mA, and
step I2 from 0 to 2.5 mA. The results are shown in Fig. 17.
We see that VL2 (blue) and VL1 (pink) jump by 120 mV and
-15 mV respectively, which are in good agreement with the
values predicted by (6) and (7).
Finally, we keep I2 and I3 fixed at 1.5 mA and 1.5 mA, and
step I1 from 0 to 2.5 mA. The results are shown in Fig. 18.
We see that VL2 (blue) and VL1 (pink) jump up by 10 mV and
120 mV respectively, again in good agreement with the values
predicted by (6) and (7).
If a supply brown-out occurs from 3.6 V to 2.6 V, we expect
the top-most load to come in parallel with lower-most load.
Hence, the upper rail of the top-most load, I3 , is expected to
3235
Fig. 19. The output voltage levels of the cyclic converter in brown-out.
Fig. 20. Measured efficiency, and switching frequency as a function of load
current mismatch in mode 3, with the battery voltage being 3.6 V. The nominal
load currents are chosen to be 1.5 mA.
Fig. 21. Measured efficiency, and switching frequency as a function of load
current mismatch in mode 1, with the battery voltage being 2.4 V. The nominal
load currents are chosen to be 1.5 mA.
transition from 3.6 V to 1.2 V, while its lower rail should go
from from 2.4 V to 0. This is indeed seen in measurements,
as shown in Fig. 19.
Figures 20 and 21 show the measured efficiency with
mismatched loads, in modes 3 and 1 respectively. These curves
were obtained in the following manner. The loads were first
made identical, with each drawing 1.5 mA. In this balanced
condition, the efficiency in mode 3 (with V B = 3.6 V)
should be close to 100%. A very small switching frequency
is necessary, and in our case, was chosen to be 1 kHz. Each
load current is modified (one at a time) from the nominal
value – this will cause the voltages VL1 and VL2 to change.
The switching frequency is increased to restore the voltages
across the loads to within 10% of their nominal values. As
expected from our analysis, the frequency needed to do this
has to increase with load current mismatch. This is confirmed
3236 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 66, NO. 8, AUGUST 2019
TABLE I
S UMMARY AND C OMPARISON W ITH R ECENT W ORKS
by measurements, shown in the lower part of Fig. 20. As
a consequence of the increased switching frequency, losses
increase, thereby degrading efficiency.
Fig. 21 shows the corresponding efficiency and switching
frequency curves for mode 1, with V B = 2.4 V. Recall that in
this mode, I1 and I3 are in parallel, with I2 stacked above. The
balanced load condition in this mode occurs when I2 = 3 mA,
and I1 = I2 = 1.5 mA. With a switching frequency of 1 kHz,
an efficiency of 97% was measured.
Table I summarizes the performance of our PMIC, and
compares it with some state-of-the-art designs. We see that our
design operates over a wide range of battery voltages, while
achieving good efficiency. This makes the PMIC suitable for
practical battery operated applications.
VI. C ONCLUSION
We introduced cyclic switched-capacitor dc-dc conversion,
which is particularly suited for efficient power delivery in
stacked voltage domain systems. As a proof of concept, we
demonstrated a two- and three-level cyclic SCDCDC power
conversion system to drive SVD-based loads. The cyclic con-
verter was shown to be an improvement over a ladder converter
on several fronts. For a given amount of flying capacitance,
the cyclic converter needs a much smaller switching frequency
when compared to a ladder. Further, the cyclic converter draws
a largely constant current from the battery, as opposed to a
ladder converter. Fundamentally, this is because the ladder
draws current from the battery only during one phase. A PMIC
incorporating a cyclic SCDCDC converter, designed to drive
three stacked loads, from a battery that can vary over a
2.35–3.65 V range achieves a performance comparable to the
state-of-the-art.
ACKNOWLEDGMENT
The authors thank Mahesh Mehendale and Manikandan
from Texas Instruments for useful discussions. The layout
support of Pankaj Kumar and Dinesh Hegde is gratefully
acknowledged.
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Kishalay Datta received the bachelor’s degree in
electronics and telecommunication engineering from
IIEST, Shibpur, India, in 2014. He then joined the
IIT-TII joint master’s program in analog mixed-
signal design with IIT Madras, Chennai. He was a
Research Intern with Texas Instruments, Bengaluru,
India, from 2015 to 2017, where he has been with
the Isolation Group since 2017. His current interests
include power management and high-voltage com-
munication circuits.
3237
Vinod Menezes received the B.E. degree from
the R V College of Engineering, Bengaluru, and
the M.Sc. degree in electrical and communication
engineering from the Indian Institute of Science,
Bengaluru. Subsequently, he joined Texas Instru-
ments, India, in 1990, and has worked on mem-
ory products spanning DRAM, FLASH, EPROM,
SRAM, TCAM, and ROM’s. He has worked on
ASIC digital and IO libraries down to 28 nm CMOS.
His more recent work is in mixed-signal designs
with a focus on ultra-low power.
Shanthi Pavan received the B.Tech. degree in elec-
tronics and communication engineering from IIT
Madras, Chennai, in 1995, and the M.S. and Sc.D.
degrees from Columbia University, New York, in
1997 and 1999, respectively. From 1997 to 2000,
he was with Texas Instruments, Warren, NJ, USA,
where he worked on high speed analog filters and
data converters. From 2000 to 2002, he worked on
microwave ICs for data communication at Bigbear
Networks, Sunnyvale, CA, USA. Since 2002, he
has been with IIT Madras, where he is currently a
Professor of electrical engineering. He has authored Understanding Delta-
Sigma Data Converters (Second Ed.), with R. Schreier and G. Temes. His
research interests are in the areas of high speed analog circuit design and
signal processing.
Dr. Pavan is a fellow of the Indian National Academy of Engineering.
He was a recipient of the Young Engineer Award from the Indian National
Academy of Engineering in 2006, the IEEE Circuits and Systems Society
Darlington Best Paper Award in 2009, the Swarnajayanthi Fellowship, Gov-
ernment of India, in 2009, the Shanti Swarup Bhatnagar Award in 2012, the
Mid-career Research Excellence Award, and the Young Faculty Recognition
Award from IIT Madras (for excellence in teaching), the Technomentor Award
from the India Semiconductor Association. He has served as the Editor-
in-Chief of the IEEE T RANSACTIONS ON C IRCUITS AND S YSTEMS : Part
I Regular Papers, and on the Editorial Boards of both parts of the IEEE
T RANSACTIONS ON C IRCUITS AND S YSTEMS . He has served on the technical
program committee of the International Solid State Circuits Conference, and
been a Distinguished Lecturer of the IEEE Solid-State Circuits Society. He is
a Distinguished Lecturer of the IEEE Circuits and Systems Society.