2.4-2.

5 GHz Fractional-N Frequency Synthesizer with

Integrated VCO in 0.18 um CMOS for RFID Systems
Denis B. Akhmetov1, Alexander S. Korotkov2, Ivan A. Rumyancev3
Institute of Physics, Nanotechnology and Telecommunications
Peter the Great St.Petersburg Polytechnic University
Saint Petersburg, Russia
1
akhmetov@spbstu.ru, 2korotkov@spbstu.ru, 3i.a.rumiantsev@spbstu.ru

Abstract—Paper presents simulation and measurement
results of 2.4-2.5 GHz fractional-N frequency synthesizer with
integrated voltage controlled oscillator, designed in a standard
0.18 um CMOS technology process, for RFID systems. Phase
noise of the designed synthesizer is below –117 dBc/Hz at 1 MHz
offset. The output power is –2 dBm, while spur level is below –
79 dBc. Chip area, occupied by the designed circuit, is
1.2 sq. mm.
Keywords—VCO, PLL, frequency synthesizer, CMOS
I. INTRODUCTION
Radio frequency identification (RFID) is widely used for
automatic objects identification. In general, the RFID system
consists of two main parts: a reader and RF tags. The reader
includes an antenna, a transceiver, a control unit and is
intended for reading, as well as, in some cases, recording
information to RF tags [1].
the reference oscillator. In synthesizers with an integer division
factor, the bandwidth is limited by the frequency tuning step.
On the contrary, in synthesizers with a fractional division
factor, the frequency of the reference signal can significantly
exceed the adjustment step, which determines their prospects.
GaAs technology shows good phase noise performance at
GHz frequencies, while Si based technologies are up to 10
times chipper in mass production and allow integration of
analog and digital blocks on the same die. This makes the latter
more promising for the design. At Russia 2.40-2.48 GHz
frequency band are not licensed, which makes it suitable for
various short range communication systems, such as RFID.
Thus, this work is devoted to the design of 2.4-2.5 GHz
synthesizer with integrated VCO, fabricated in CMOS
technology, for RFID systems.
II. CIRCUIT DESIGN

In transceivers frequency synthesizers are used for the A. VCO

generation of a stable RF signals from reference low frequency Since low phase noise of the oscillator is one of the criteria
signal. Normally, frequency synthesizer consists of a voltage ensuring reliable transmission of information, the harmonic
controlled oscillator (VCO), a phase locked loop (PLL) and a oscillator has been chosen to implement the VCO. The simplest
stable low frequency reference oscillator. harmonic oscillator, the circuit of which is shown in Fig. 1a,
The voltage controlled oscillator provides oscillation with a consists of an LC-tank, a cross-connected pair of N-type
required frequency and allows adjusting the oscillation transistors and a current source. The LC-tank determines the
frequency depending on the voltage at the control pin. operating frequency of the oscillator, the negative conductivity
According to the form of the generated oscillations, VCOs can of the cross-connected transistors compensates losses of
be divided into relaxation and harmonic. Relaxation oscillators reactive elements, and the current source sets operating points
form an output signal of a shape, different from sinusoidal, and, of the transistors.
as a rule, have small dimensions and high phase noise.
Harmonic generators form a sinusoidal output signal and have
low phase noise, but occupy significant chip area.
The PLL block is constructed using analog and digital
circuits, i.e. is a device with mixed type signals. With respect to
the frequency of the reference signal to the frequency of the
carrier wave, synthesizers with an integer division factor and
with a fractional one are distinguished. The closed loop
bandwidth f-3dB of PLL determines the characteristics of the
device in the time and frequency domains. Thus, an increase in
(a) (b)
the bandwidth makes it possible to reduce the phase noise level
and the frequency tuning time. On the other hand, the Fig. 1. (a) Schematic of the typical harmonic oscillator and (b) schematic of the
frequency band is limited by the required leakage level of the designed VCO.
reference frequency signal and other possible interference to
the input of the VCO. Together with the requirement for The schematic of the designed VCO is shown in Fig. 1b.
system stability, due to the presence of feedback, the Output frequency is adjusted by changing the control voltage
bandwidth is usually substantially lower than the frequency of

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Vctrl, which leads to a change of the capacitance of varactors D1
and D2. To expand frequency range Δf and compensate
deviations of component parameters from their nominal values
under process variations, a capacitor bank is added to the
circuit. The nominal capacitor value is controlled by signals on
terminals K1-K4. The output buffers on the transistors T4-T7
ensure the isolation of the VCOs from external circuits. An
active balun is used to convert differential output VCO signal
to single-ended , similar to that used in [2]. Layout of the
designed VCO is depicted in Fig. 2. The area of the crystal
occupied by the circuit, including electrostatic protection, is
about 1.3 sq. mm, core size is about 0.9 sq. mm.
Fig. 2. Layout of the designed VCO.
Fig. 3 shows the dependence of the VCO output frequency
on the value of the control voltage Vctrl. The linear part of the
VCO tuning characteristic is about 1.3 V. Frequency tuning is
performed in the range from 2.2 GHz to 2.6 GHz. Fig. 4
depicts the phase noise dependence on the offset frequency
from the carrier. At operating frequency of 2.4 GHz and
1 MHz offset, the phase noise is less than minus 117 dBc/Hz.
Fig. 3. VCO output frequency versus control voltage and K1-K4.
Fig. 4. VCO phase noise.
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B. PLL
The block diagram of the typical frequency synthesizer is
shown in Fig. 5 and includes: a reference frequency oscillator
(RFO), a phase detector (PD), a charge pumping circuit (CP), a
low-pass filter (LPF), a voltage controlled oscillator, a
frequency divider (FD) and delta-sigma modulator (DSM).
Fig. 5. Block diagram of the designed frequency synthesizer.
As the RFO, quartz generators are used in practice. RFO’s
output signal Uref(t) with frequency fref is determined by the
circuitry and usually has a sinusoidal or rectangular shape. The
phase detector is usually based on D flip-flops. The device can
be in three states: both outputs are in a high-resistance state,
one of the outputs of the device is in a high-resistance state, i.e.
there is only one of the output signals Uup(t) or Udw(t), there are
two output signals Uup(t) and Udw(t) at the same time.
The feature of this type of detector is that the operating
mode of the PD depends on the current state of the PLL loop. If
compared frequencies of the input signals are differ, i.e. the
loop is in capture mode, only one of the detector outputs is in a
high-resistance state. In the hold mode, on the contrary, the
outputs are in the active state one tenth or one hundredth of the
reference signal period, after which they go into high resistance
state. This behavior is caused by the fact that the loop tends to
maintain a phase difference close to zero, with the signals
Uup(t) and Udw(t) being proportional to the phase difference. In
any case, Uup(t) and Udw(t), are pulse signals.
As the next block, a CP is usually installed, which converts
the voltage output pulses Uup(t) and Udw(t) of the PD into
current pulses of Icp(t) of different polarity, i.e. Icp(t) is correctly
represented as the sum of two impulse signals:
Icp(t)= Iup(t) + Idw(t)
In the ideal case, when absolute values of amplitudes Iup(t)
and Idw(t) are equal and are not displaced relative to each other
in time, Icp(t) will be rectangular pulses of different polarity. In
the general case, the form of Icp(t) will be complicated.
The LPF, following the CP, is responsible for the
transformation of the current pulses Icp(t) into the voltage
ULPF(t), controlling the VCO. It should be noted that even in
the hold mode when operating at a constant frequency due to
the influence of phase noise of the VCO, the PLL loop will
tend to compensate for the phase shifts of the VCO signal. This
effect leads to the fact that ULPF(t) varies with time, but it’s
average value, i.e. the constant part of ULPF(t) determines the
synthesizer frequency.
 Fig. 6 shows the spectrum of the frequency synthesizer
output signal at 2.4 GHz, obtained during the functional
simulation in MATLAB with characteristics of the VCO,
obtained during transistor level simulation in Cadence
Virtuoso. As can be seen from the data, the level of reference
spurs at frequencies fc ± fref is less than –88.5 dBc.

Fig. 8. Voltage ULPF(t) during tuning from 2.44 GHz to 2.40 GHz.

Fig. 6.
Frequency synthesizer output signal spectrum in MATLAB.

Fig. 7 shows the phase noise at 2.44 GHz, obtained as a

result of functional simulation in the MATLAB, and using
numerical calculation based on analytical expressions from [3].
Analytical expressions are derived on the assumption of
linearity of the VCO characteristics. In addition, symbolic
Fig. 9. Frequency synthesizer output signal spectrum in Cadence.
analysis does not take into account the noise of the charge
pump circuit.
III. EXPERIMENTAL RESULTS
The proposed frequency synthesizer with integrated VCO
has been fabricated in a standard 1P6M 0.18 um CMOS
technology. The chip microphotograph is shown in Fig. 10.
Core area is about 1.2 sq. mm, where VCO occupies
approximately 75% of the area.

Fig. 7. Frequency synthesizer phase noise.

After functional simulation all blocks of the PLL have been

designed and simulated on transistor level including parasitic
elements of the layout in Cadence Virtuoso. Fig. 8 shows the
time dependence of the control voltage ULPF(t) during tuning
from 2.44 GHz to 2.40 GHz. The output power spectrum of the
synthesizer is shown in Fig. 9.
Fig. 10. The chip microphotograph.

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 Measurement of the frequency synthesizer characteristics in
the time domain was carried out using the Agilent MSO 7032B
digital oscillograph. When measuring in the frequency domain,
the output signal of the frequency synthesizer was fed to the
input of a Rohde & Schwarz signal source analyzer FSUP26.
The measured phase noise of the VCO and the frequency
synthesizer at 2.44 GHz are depicted in Fig. 11 and Fig. 12,
respectively. Fig. 13 shows the measured time dependence of
the control voltage ULPF(t) during tuning from 2.44 GHz to
2.40 GHz. The tuning time is about 12 μs.
Table 1 compare phase noise simulation and measurement
results of the VCO and synthesizer. Key parameters
comparison of the designed frequency synthesizer with other
known solutions is presented in Table 2.
R&S FS UP S ignal S ourc e A nalyzer S WE E PING
S ettings Res idual Nois e [T 1 w/o s purs ] S pur Lis t
Signal Frequenc y: 2.447 815 GHz Int P HN (100.0 .. 100.0 M) 27.9 dBc 12.6 17 MHz -9 0.07 dBc
Signal Level: -1 .94 dBm Residual P M 20 17.429 ° 20.0 00 MHz -8 3.65 dBc Fig. 13. Voltage ULPF(t) during tuning from 2.44 GHz to 2.40 GHz
Cross C orr+Sweep Harmonic 1 Residual FM 22 .451 kHz 49.8 55 MHz -7 5.36 dBc
Internal Ref Tuned Internal P has e Det RMS Jitter 22 89.405 7 ps 77.4 29 MHz -7 9.75 dBc
Phas e Noise [dBc /Hz]
RF A tten 0 dB
Top 20 dBc/Hz TABLE I. PHASE NOISE SIMULATION AND MEASUREMENT RESULTS
Spot Noise [T1 w/o spurs]
LoopBW 1.000 kHz -30.67 dBc/Hz
0 10.000 kHz -60.65 dBc/Hz
VCO Synthesizer
100.000 kHz
1.000 MHz
-88.24 dBc/Hz
-117.75 dBc/Hz A Frequency
-20 10.000 MHz -143.86 dBc/Hz Sim. Meas. Sim. Meas.
1 CLRWR
SMTH 1% -40
1 kHz -30 -30 –80 –81
2 CLRWR 10 kHz -59 -60 –88 –88
-60
100 kHz -88 -88 –88 –86
-80
1 MHz -117 -117 –120 –116
-100 10 MHz -143 -143 –150 –145
-120

-140
SPR OFF
TH 0dB
TABLE II. KEY PARAMETERS COMPARISON
-160
References
100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 100 MHz Parameter
Frequency Offset
[4] [5] [6] [7] Work
Fig. 11. VCO phase noise.
Technology
0.18 0.18 0.15 0.13 0.18
Resolution, um
R&S FSUP Signal Source Analyzer LOCKED

Settings Residual Noise [T1 w/o spurs] Spur List f-3dB, kHz 400 – 100 200 150
Signal Frequency: 2.440024 GHz Int PHN (1.0 k .. 30.0 M) -33.1 dBc 20.000 MHz -79.10 dBc
Signal Level: -1.25 dBm Residual PM 1.788 °
Cross Corr Mode Harmonic 1 Residual FM 6.24 kHz Δf, GHz 2.2-2.6 2.4-2.5 2.4-2.5 2.0-2.5 2.4-2.5
Internal Ref Tuned Internal Phase Det RMS Jitter 2.0351 ps
Phase Noise [dBc/Hz] Phase Noise @
RF Atten 0 dB –90 –109 –107 –112 –114
Top -70 dBc/Hz 1MHz, dBc/Hz
Spot Noise [T1 w/o spurs]
1.000 kHz -80.89 dBc/Hz Reference
LoopBW
10.000 kHz -88.24 dBc/Hz -80 –39 –64 – –50 –79
-80
100.000 kHz -85.67 dBc/Hz
A
Spur, dBc
1.000 MHz -116.50 dBc/Hz
-90 10.000 MHz -144.99 dBc/Hz -90

1CLRWR
SMTH 1% -100 -100
IV. CONCLUSION
Simulation and measurement results of 2.4-2.5 GHz
2CLRWR
-110 -110

-120 -120
fractional-N frequency synthesizer with integrated voltage
controlled oscillator for RFID systems designed in a standard
-130 -130
0.18 um CMOS technology are presented. Phase noise of the
-140 -140
designed synthesizer is below –117 dBc/Hz at 1 MHz offset.
-150 -150
SPR OFF
TH 0dB Output power –2 dBm. Reference spur level is below minus
-160 -160 79 dBc.
1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 30 MHz
Frequency Offset REFERENCES
Fig. 12. Frequency synthesizer phase noise.
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