INTRODUCTION TO NANOSCIENCE AND NANO TECHNOLOGY

ECE1006

SINGLE ELECTRON TANSISTOR

FACULTY COORDINATOR:
Prof. MUTHURAJ.S

SUBMITTED BY:
T. USHA SREE – 18BEC0206
J. GOVINDA LAHARI – 18BEC0226
ABSTRACT:
Single-electron transistor (SET) is a key element of current research area of nanotechnology
which can offer low power consumption and high operating speed. Single electron transistor
[SET] is a new nano scaled switching device because single electron transistor retains its
scalability even on an atomic scale and besides this; it can control the motion of a single
electron. In this project we are going to discuss about the basic physics of nano electronic
device ‘Single electron transistor [SET]’ which is capable of controlling the transport of only
one electron and focuses on some basic device characteristics like tunnelling effect and the
Coulomb blockade, Quantum Dot & Coulomb staircase on which this Single electron transistor
[SET] works. Simulation methodology of the single electron transistor is discussed along with
the tools available like MATLAB. The physics underlying the operation of SET is explained.

HISTORY:
In his famous 1911 experiments, Millikan observed the effects of single electrons on the falling
rate of oil drops. The effects of charge quantization were first observed in tunnel junctions
containing metal particles as early as 1968. Soon after the idea of overcoming the Columbic
Blockade can be prevail with the use of gate electrode came to many scientists. And later Kulik
and Shechter they came up with the theory of Coulomb-blockade oscillations, which is the
periodic variation of conductance as a function of the applied gate voltage. In the year 1987
Fulton and Dolan successfully made the first SET which was entirely made up of metals, and
they obtained the same result as predicted earlier by Fulton and Dolan i.e., they observed the
periodic oscillation. They used Metal particle which is connected to two metal leads by the
tunnel junction. Which is mounted on the insulator and Gate was underneath it. Shortly
thereafter Meir vet al made controlled devices of the kind, albeit with an unusual
heterostructure with AL GaAs on the bottom instead of the top. In these and similar devices
the effects of energy quantization were easily observed. During the year 1989 first
Semiconductor SET was accidentally fabricated by Scott-Thomas in a narrow Si field effect
transistor, for this case tunnel barrier was obtained by interface charge in this case the tunnel
barriers were produced by interface charges.

INTRODUCTION:
Transistors are the building blocks of the electronic devices that power the digital world, and
much of the growth in computing power over the past many decades has been made possible
by increases in the number of transistors that can be packed onto silicon chips. But that growth,
if left to current technology, may soon be coming to an end. Many in the semiconductor field
think that the industry is fast approaching the physical limits of transistor miniaturization. The
major problem in modern transistors is power leakage leading to the generation of excessive
heat from billions of transistors in close proximity. Only one thing is certain: if the pace of
miniaturization continues unabated, the quantum properties of electrons will become crucial in
determining the design of electronic devices. SET has become the famous due to its size and
operation. Single-electron transistor (SET) is very popular in the field of nanoelectronics since
a decade. Single electron transistor (SET) is the most fundamental three-terminal single
electron device (SED) which is capable of offering low power consumption and high operating
speed. Since the technology reaches nano size, the behaviour of a nano electronic single
electron transistor (SET) is controlled by the quantum mechanical effects. Main are advantages
that makes us to use SET are
• ultra-low-power consumption is one of the main research topics into the current
electronics world.
• high device integration level.
• Faster and more information processing.

DATA COLLECTED AND ANALYSIS:

A SET consists of one small island connected to two electrodes (a source and a drain) through
two tunnel barriers and capacitively coupled to a nearby third electrode (gate electrode) A
Small Island is there between the source and the drain called as quantum dot. The resistance
between the island and each of the electrodes must be larger than the quantum resistance. In
this case, the number of electrons on the island is well defined. Therefore, the current flowing
through the island can only occur by successive addition and removal of single electrons to and
from the island a single electron would tunnel from the source to the island and subsequently
from island to drain. The tunnelling of electrons can5 | P a g e be blocked at low bias voltage
due to the Coulomb repulsive interaction until enough energy is provided by applying a voltage
difference between the source and drain electrodes. A gate voltage is applied to the gate
electrode and tunes the electrostatic potential of the island. Controlling the gate voltage
regulates the number of electrons tunnelling on or off the island, one at a time. SET is a three-
electrode tunnelling device that consists of a conductive island with low self-capacitance
connected to source and drain electrodes by low-capacitance and low conductance tunnel
junctions and having a capacitive coupling with the gate electrode.

Coulomb Blockade:
Coulomb blockade is defined as the effect of blocking the electron tunnelling through the
tunnel junction or a tunnel system due to the repulsion of the electrons in the electrode by the
Coulomb field of the electron that was the last to pass the junction. This effect is characterized
by the size of the area with zero tunnelling conductance at the origin of the junction current-
voltage characteristic curve. This area is called the Coulomb blockade voltage or critical
voltage or threshold voltage or just the Coulomb blockade. To achieve the Coulomb blockade,
three criteria have to be met:
• The bias voltage must be lower than the elementary charge divided by the self-
capacitance of the island Vbias<e/c where C=e2/∇
• Coulomb energy must be greater than the thermal fluctuation; EC= (e^2/2C) > kBT.
Where kB is Boltzmann’s constant and T is temperature in Kelvin.
• Electrons should be localized only on the island and all tunnel junctions should be
opaque for electrons to confine them to the islands. RT = h/e^2 =25.813 KΩ.
Quantum Dot:
Quantum Dot is a semiconductor whose excitations are confined in all three dimensions. As a
result, they have properties that are between bulk semiconductors and discrete molecules. It is
weakly coupled by tunnel barriers to two electron reservoirs. Advantage of Quantum Dot is
that because of the high level of control possible over the size of crystals produced, it is possible
to have very precise control over the conductive properties of the material.

This is the basic structural diagram of the Single Electron Transistor.

This is Single Electron Transistor circuit diagram with the single island of one Quantum dot.

FABRICATION:
One of the main requirements to fabricate single electronics is to achieve capacitance in atom
farad or less, which can be achieved by making structure less than 100nm. Optical lithography
is being used in industries for mass fabrication of semiconductors is limited to feature sizes
greater than 100nm if we use very sophisticated aligners. Christoph Wass Huber mentioned
two approaches as top down and bottom up. In former, one starts with wafer, define structures
using lithography, etch, deposit layers if required. This is the conventional approach used in
semiconductor industry and we process complete wafer at one time. Most widely used
approach is top down. Bottom-up approach involves building of small molecules and then
assembling them on top of the substrate. These molecules include nanoparticles of gold or
quantum dots, this is a slow step but we can achieve high precision.
MASTER EQUATION METHOD:
Master equation is a method for modelling all states of electron tunnelling process uniquely
and treating their transition probabilistically. This method can describe the time evolution
probabilities system in occupying discrete state [18]. Hence, master equation can be used to
calculate probabilities of electron tunnelling which is used to determine current flow in SET.
Before calculation, components of SET must be well-defined. Those components include gate
capacitance (Cg), capacitances (C1 and C2) and resistances (R1 and R2) in tunnel junctions. In
addition, we also have to specify several input parameters including Boltzmann constant (kB)
and charge of carrier (e), and some external parameters such as voltage source drain (Vsd), gate
voltage (VG), temperature (T), charge in quantum dot (N), and background charge (Q0). The
iterative algorithm of a master equation method as shown in the flow chart.
By basing on that flow chat, we can prepare the MATLAB code that shows the I_V
characteristic of the SET.
MATLAB CODE:
% Matlab program source for numerical simulation of Master equation
% in single electron transistor
% This program code is made by Dr. Ratno Nuryadi, Jakarta, Indonesia
clear all;
% Definition of Physical constant q=1.602e-19;
% electronic charge (C) kb=1.381e-23; % Boltzman constant (J/K)
% Definition of Device parameters
c1=1.0e-20; % tunnel capacitor C1 (F)
c2=2.1e-19; % tunnel capacitor C2 (F)
cg=1.0e-18; % gate capacitor Cg (F)
ctotal=c1+c2+cg; % total capacitance (F)
mega=1000000; % definition of mega=106
r1=15*mega; % tunnel resistance R1 (Ohm)
r2=250*mega; % tunnel resistance R2 (Ohm)
Vg=0; % gate voltage (V)
q0=0; % background charge q0 is assumed to be zero
temp=10; % temperature T (K)
vmin=-0.5; % drain voltage minimum Vmin (V)
vmax=0.5; % drain voltage maximum Vmax (V)
NV=1000; % number of grid from Vmin to Vmax
dV=(vmax-vmin)/NV; % drain voltage increment of each grid point
for iv=1:NV % loop start for drain voltage
V(iv)=vmin+iv*dV; % drain voltage in each grid point
% Note that loop end for drain voltage is located in the end of this program
Nmin=-20; % minimum number of N (charge number in dot)
Nmax=20; % maximum number of N (charge number in dot)
for ne=1:Nmax-Nmin % loop start for N
n=Nmin+ne; % N charge number in dot
% Calculation of ?? in equations (25a) and (25b)
dF1p=q/ctotal*(0.5*q+(n*q-q0)-(c2+cg)*V(iv)+cg*Vg);
dF1n=q/ctotal*(0.5*q-(n*q-q0)+(c2+cg)*V(iv)-cg*Vg);
dF2p=q/ctotal*(0.5*q-(n*q-q0)-c1*V(iv)-cg*Vg);
dF2n=q/ctotal*(0.5*q+(n*q-q0)+c1*V(iv)+cg*Vg);
% Noted that loop end for N is located after calculation of ?
if dF1p<0
T1p(ne)=1/(r1*q*q)*(-dF1p)/(1-exp(dF1p/(kb*temp)));
% ? positive in equation (26a)
else
T1p(ne)=1e-1; % ? positive is assumed to be very small
end
if dF2p<0
T2p(ne)=1/(r2*q*q)*(-dF2p)/(1-exp(dF2p/(kb*temp)));
% ? positive in equation (26b)
else
T2p(ne)=1e-1; % ? positive is assumed to be very small
end
if dF2n<0
T2n(ne)=1/(r2*q*q)*(-dF2n)/(1-exp(dF2n/(kb*temp)));
% ? negative in equation (26b)
else
T2n(ne)=1e-1;
end
end % loop end for N
p(1)=0.001; % ?(Nmin) is assumed to be 0.01
p(Nmax-Nmin)=0.001;
sum=0; % sum=0 is initial value to calculate ?
for ne=2:Nmax-Nmin
p(ne)=p(ne-1)*(T2n(ne-1)+T1p(ne-1))/(T2p(ne)+T1n(ne));
% calculation of ?(N) in equation (28)
% The conditions below are used to avoid divergence of Matlab calculation
if p(ne)>1e250
p(ne)=1e250;
end
if p(ne)<1e-250
p(ne)=1e-250;
end
%
sum=sum+p(ne);
end
for ne=2:Nmax-Nmin
p(ne)=p(ne)/sum; % Normalization in equation (31b)
end
sumI=0; % sumI=0 is initial condition
for ne=2:Nmax-Nmin
sumI=sumI+p(ne)*(T2p(ne)-T2n(ne));
end
I(iv)=q*sumI; % I in equation (32b)
end % end of drain voltage loop
plot(V,I); % plot of I vs V
for iv=1:NV-1
dIdV(iv)=(I(iv+1)-I(iv))/dV; % calculation of dIdV
end
figure;
plot(V(1,1:NV-1),dIdV); % plot of dIdV vs V
OUTPUT OF SIMUALTION CHARACTERISTICS:
It gives information about the best simulation model to describe experimental result. I-V
characteristic simulation of SET with Master Equation provides a better result than Monte
Carlo method. With the same input parameters, Master Equation can depict the staircase pattern
from experimental result, while Monte Carlo method does not.

The effect of resistance variation to I-V characteristic of SET. The value of drain and source
resistance do not affect the threshold voltage. In every variation of drain and source resistances,
the value15 | P a g e of threshold voltage is always 0.13 V. When the drain resistance is lower
than source resistance, higher current will flow and coulomb blockade effect occur. It can be
seen from staircase pattern of I-V characteristic in SET. If drain resistance higher than source
resistance, staircase effect will decrease and finally disappeared.
The effect of gate voltage variation to I-V characteristic of SET can be seen at Figure 5. The
value of threshold voltage is 0.13 V in every variation of gate voltage. Hence, the value of gate
voltage is not affected by threshold voltage value, but higher gate voltage will make SET works
dominantly in forward bias. In addition, increasing gate voltage will promote higher current
density. Moreover, coulomb blockade effect will be reduced when gate voltage is increased.

It shows the effect of temperature variation for I-V characteristic of SET. The threshold voltage
in every temperature variation is always constant, which is 0.13 V. Moreover, increasing
temperature will promote higher current density. There are no significant current differences
because numbers of carriers in the dot are exact for certain density of states. So, higher
temperature only creates a small thermal vibration of carriers.
 The graph of the dl/dv curve with device parameters.

ELECTRONS IN DOT:
dI/dV vs. drain voltage

COULOMB BLOCKADE:
Comparison between Monte Carlo and master equation
Tunneling rate

Charge density for different drain voltages

Drain current vs. drain voltage at fixed gate voltage:

Charge density for different gate voltages

Drain current vs. gate voltage at fixed drain voltage

Sum of the number of charges that arrived and left the drain
Number of charges arrived at the drain at fixed gate voltage:

Number of charges that left at the drain at fixed gate voltage

Drain current vs. time at fixed drain voltage:

Drain current vs. time at fixed gate voltage:

Drain current vs. drain voltage at fixed gate voltage comparison between
Monte Carlo and master equation:

Drain current vs. gate voltage at fixed drain voltage comparison between
Monte Carlo and master equation:
APPLICATIONS OF SET:
➢ Charge Sensor
The Single-electron transistors (SETs) are efficient charge sensors for reading out spin or
charge qubits confined in quantum dots (QDs). To investigate their capacitive parameters,
which are related to the signal-to-noise ratio (SNR) during qubit readout, twin silicon single
QDs were fabricated using a lithographic process on a silicon-on-insulator substrate. Since the
configuration and dimensions of the QDs could be determined by direct imaging, the
theoretical capacitive parameters could be compared to the measured values. Good agreement
was found between the calculated and measured value, which confirms the validity of the
calculation method. The results indicated that decreasing the SET diameter reduces the
capacitive coupling between qubits but increases the signal-to-noise ratio for both dc and radio
frequency single-shot measurements. Since these results are independent of the device
materials, they are useful for establishing guidelines for the design of SET charge sensors in
lateral QD-SET structures based on a two-dimensional electron gas.
➢ Detection of Infrared Radiation
The single-electron transistor can also be used to detect infrared signals at room temperature.
By exciting electrons over an electrically induced energy barrier, both the range of detectable
wavelengths and the sensitivity of the device can be controlled. The sensor works when an
infrared signal excites conduction-band electrons in a 25 -nm-deep electron reservoir. A silicon
insulator channel measuring 40 × 400 nm is placed next to the reservoir to increase the number
of excited electrons. A poly-silicon lower gate then turns off the transistor and electrically
forms an energy barrier, creating a storage node on the other side. Electrons with energy greater
than the height of the barrier are injected into the storage node, where they are read as changes
in current flowing through the transistor.
➢ Ultrasensitive Microwave Detector
Another application of Single Electron Transistor can be as an Ultrasensitive Microwave
Detector; island is weakly coupled to a bias circuit through two small-capacitance tunnel
junctions and a capacitive gate. At low bias voltages and temperatures, a single quasiparticle
may only be introduced to the island through photonassisted tunnelling. Once this occurs, the
quasiparticle is trapped on the island because it takes a relatively long time for this specific
quasiparticle to tunnel off. While it is trapped, charge is transported through the system two
electrons at a time. Since the photonassisted transition merely switches the detector current on,
this device is not limited to one electron tunnelled through the system per absorbed photon.
This makes the device an extremely sensitive and potentially useful detector of microwave
radiation.
➢ Single-Electron Spectroscopy
Another application of single-electron electrometry is the possibility of measuring the electron
addition energies (and hence the energy level distribution) in quantum dots and other nanoscale
objects. There are two natural ways to carry out such measurements. The first is to use the
quantum dot as the island of the single-electron box, capacitively coupled to the single electron
transistor or other sensitive electrometer. The second is to use the quantum dot directly as the
island of a weakly biased single-electron transistor and measure the gate voltages providing
the sharp increase of the source-drain conductance.
LIMITATIONS:
➢ Back Ground Charge
The first major problem with the single electron logic circuits is the infamous randomness of
the background charge. A single charged impurity trapped in the insulating environment
polarizes the island, creating on its surface an image charge Q0 of the order of e. This charge
is effectively subtracted from the external charge Qe.
➢ Room Temperature
Another big problem with all the known types of single electron logic devices is the
requirement Ec~100kB T, which in practice means sub-nano meter island size for room
temperature operation. In such small conductors the quantum kinetic energy gives a dominant
contribution to the electron additional energy even small variations in island shape will lead to
unpredictable and rather substantial variations in the spectrum of energy levels and hence in
the device switching threshold.
➢ Out Side Environment Linking with SETs
The individual structures patterns which function as logic circuits must be arranged in to larger
2D patterns. There are two ideas, first20 | P a g e is to integrate SET as well as related equipment
with the existing MOSFET, this is attractive because it can increase the integrating density.
The second option is to give up linking by wire, instead utilizing the static electronic force
between the basic clusters to form a circuit linked by cluster, which is called quantum cellular
automata (QCA). The advantage of QCA is its first information transfer velocity between cells
via electrostatic interaction only, no wire is needed between arrays and the size of each cell can
be as small as 2.5 nm, this made them very suitable for high density memory and next
generation quantum computer.
➢ Lithography Technique
Another major problem with single electron devices is the requirement Ec~100kB T, which in
practice means sub-nano meter island size for room temperature operation. In VLSI circuits,
this fabrication technology level is very difficult. Moreover, even if these islands are fabricated
by any sort of nanolithography, their shape will hardly be absolutely regular.
➢ Co-tunnelling
The pressure essence of the effect is that the tunnelling of several electrons through different
barriers at the same time is possible as a single coherent quantum mechanical process. The rate
of the process is crudely less than that for the single electron tunnelling.
CONCLUSION
In conclusion, Single Electronic Transistor (SET) has proved their value as tool in scientific
research. Resistance of SET is determined by the electron tunnelling and the capacitance
depends on the size of the nanoparticle. A SET is a three-terminal device in which electrons
are transferred one by one using columbic blockade effect. we have demonstrated the electrical
characteristic of SET by using21 | P a g e Master Equation approach and show a fairly accurate
result with experimental data. Evidently, staircase pattern of I-V characteristic are clearly
obtained as the main role of coulomb blockade effect in the SET system. Based on various
parameter inputs, current density will be higher if the temperature or gate voltage is increased.
This is because carriers will vibrate rapidly in these conditions. In our simulation, coulomb
blockade effect could be reduced when we apply gate voltage higher than 3V and set a higher
resistance for drain than source. So, the staircase pattern, as main characteristic of SET, will be
lost.

REFERENCES:
1. Master Equation - Based Numerical Simulation in a Single Electron Transistor Using
Matlab Ratno Nuryadi Center for Material Technology Agency for Assessment
andApplication of Technology, Jakarta Indonesia.
2. Single Electron Transistor and its Simulation methods,Pankaj Kumar Sinha1, Sanjay
S2 1Centre for Nanotechnology Research, VIT University, Vellore, Tamil Nadu, India.
IJEDR 2014,Volume 2.
3. I-V Characteristics of Single Electron Transistor, U. Swetha Sree, M.Tech (VLSI &
Embedded Systems), Sree Nidhi Institute of Science & Technology, International
Journal of Engineering Trends and Technology (IJETT) Volume 4 Issue 8- August
2013.
4. Modeling and simulation of single electron transistor with master equation approach
Frans Willy and Yudi Darma Physics of Material Electronics Research Division, Dept.
of Physics, Institute Teknologi Bandung, Ganesa 10 Bandung, Indonesia.
5. A Study of Single Electron Transistor (SET), MonikaGupta, New Horizon College of
Engineering, Bangalore, India, Published in International Journal of Science and
Research (IJSR) in January 2016, Volume 5.
6. Single Electron Transistor: Applications and Limitations,Anil Kumar and Dharmender
Dubey, Bhagwant University, Ajmer, India. ISSN 2231-1297, Volume 3, Number 1,
2013.