Digital Design with the Verilog HDL

Chapter 1: Digital Design Review

Binh Tran-Thanh

Department of Computer Engineering

Faculty of Computer Science and Engineering
Ho Chi Minh City University of Technology

January 5, 2022

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Technology Tradeoffs

Full-Custom
Market Volume IC
to Amortize
Standard Cells
Time to Prototype
FPGAs, Gate
Arrays

PLDs

Non-Recurring Engineering (NRE) Cost

Process complexity
Density, speed, complexity

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Design Methodology

Design Integration Post-Synthesis

Design Specification Extract Parasitics
and Verification Timing Verification
1 5 9 13

Pre-Synthesis Test Generation and

Design Partition Design Sign-Off
Sign-Off Fault Simulation
2 6 10 14

Design Entry: Cell Placement, Scan

Synthesize and Map Production-Ready
Verilog Behavioral Chain and Clock Tree
Gate-Level Netlist Masks
3 Modeling 7 11 Insertion, Cell Routing

Simulation /
Post-Synthesis Verify Physical and
Functional
Design Validation Electrical Design Rules
4 Verification 8 12
Verilog-based

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Combinational – Sequential Logic

Combinational logic:
The outputs at any time, t,
are a function of only the
inputs at time t
Sequential logic:
The outputs at time t are a
function of the inputs at time
t and the outputs at time
t-1
a y1
Combinational
b y2
Logic
c y3
a y1
Sequential
b y2
Circuit
y3

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Transistor

nMos
S G=0 G=1
S S
G
OFF ON
D D D
pMos
S G=0 G=1
S S
G
ON OFF
D D D

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CMOS Technology
pMos
Pull-up
network
Complementary metal-oxide Input
semiconductor Output

Outputs are always either 0 or 1 nMos

Pull-down
network

VDD
A
Y
A Y A B
Y
B
GND
Inverter NAND gate NOR gate
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Parallel and Serial

nMOS: 1 = ON
pMOS: 0 = ON
a
a a a a Series: all transistors are on
g1 Parallel: at least one transistor
0 0 1 1
is on
a
a a a a
g2 0 1 0 1
g1 g2
0 0 0 1 1 0 1 1
b b b b b
b
OFF OFF OFF ON b b b b
OFF ON ON ON
a a
a a a a a a a a

g1 g1 g2
0 0 1 1 0 0 0 1 1 0 1 1

b
b b b b
g2 0 1 0 1 ON ON ON OFF

b b b b b
ON OFF OFF OFF 7 / 26
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The “Conduction Complement” Rule

Y
CMOS gate’s output is always either 0 or 1 A
For example: NAND
Y=0 if and only if both inputs are 1 B
Y=1 if and only at least one input is 0
pMos transistors are parallel while nMos transistors are serial
The “Conduction Complements” rule
The pull-up network always complements the pull-down network
Parallel → Serial, Serial → Parallel

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CMOS Inverter

VDD
A Y
0
1
A Y
A Y

GND
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CMOS Inverter

VDD
A Y
0 1
ON
1
A=0 Y=1

A Y OFF

GND
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CMOS Inverter

VDD
A
0
Y
1
OFF
1 0
A=1 Y=0

A Y ON

GND
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CMOS NAND Gate

A B Y
0
0
0
1 Y
1 0
1 1 A
B

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CMOS NAND Gate

A B Y ON ON
0 0 1
0 1 Y=1
1 0 A=0
1 1 OFF
B=0
OFF

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CMOS NAND Gate

A B Y
OFF ON
0 0 1
0 1 1 Y=1
1 0
A=0
1 1 OFF
B=1
ON

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CMOS NAND Gate

A B Y
ON OFF
0 0 1
0 1 1 Y=1
1 0 1
A=1
1 1 ON
B=0
OFF

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CMOS NAND Gate

A B Y
0 0 1 OFF OFF
0 1 1
1 0 1
Y=0
1 1 0 A=1
ON
B=1
ON

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CMOS NOR Gate

A B Y
0 0 1
A
0 1 0
1
1
0
1
0
0
B
Y

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3-input NAND Gate

Y is 0 if and only if ALL inputs are 1

Y is 1 if and only if AT LEAST one input is 0

Y
A
B
C

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Design CMOS Gates

Example
Using the CMOS Technology, draw transistor structure of a 4-input NOR
gate

A
B
C
D
Y

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Design CMOS Gate (cont.)

Example 2 (Homework)
Using the CMOS Technology, draw transistor structure of a 4-input NAND
gate

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Compound Gates

Compound gates: can describe any inverter function (not function)

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Example: AOI22
Y = (A • B) + (C • D)
A C A C
B D B D
(a) (b)

C D
A B C D
A B
(c)
(d)

C D
A
A B
B
Y Y
C
A C
D
B D
(f)

(e)
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AOI22

Use AND/OR gate to implement?

20 transistors

A
B 4 2
4 2 2 Y
C
D 4 2
OR
AND

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Example: O3AI

Y = (A + B + C ) • D

A
B
C D
Y
D
A B C

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Standard Cells

Library of common gates and structures (cells)

Decompose hardware in terms of these cells
Arrange the cells on the chip
Connect them using metal wiring

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FPGAs

”Programmable” hardware
Use small memories as truth tables of functions
Decompose circuit into these blocks
Connect using programmable routing
SRAM bits control functionality

FPGA Tiles P1
P2
P P3 OUT
P4
P5
P6
P7
P8
I1 I2 I3

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