Hardware-Efficient Linear Algebra for Radar and 5G
© 2021 The MathWorks, Inc.
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Agenda
▪ Introduction
– Applications: Radar, Comms and Wireless
– Hardware Prototyping – live demo
▪ Theory and Implementation
– Linear algebra
– Matrix decomposition: QR vs Cholesky
– Latency vs. area tradeoffs
▪ HDL Coder Implementation
– HDL Coder implementation
– Resource mapping and utilization
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Adaptive Beamforming
• Algorithm chooses optimal weights
Signal of
interest based on receive data statistics
w1 • Improve SNR by automatically
placing nulls at interference angles
w2
+
w3
Interferer w4
Adaptive
Algorithm
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Applications: Radar
• Increase angular resolution
• Suppress interference
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Applications: 5G
• Increase number of simultaneous users
• Improve throughput and coverage
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Beamforming Demonstration
Test Setup
ZU28DR RFSoC
Apply
Signal of interest Signal of
Steering Angle Beam Steer
Interest Weights
4 ADC and DAC
+ channel loopback
Interference Apply
Steering Angle Interference Beam Steer
FPGA IO
TCP/IP:
Weights
MVDR
Data Capture
MVDR
Signal of interest Algorithm
Steering Angle
MATLAB
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Agenda
▪ Introduction
– Applications: Radar, Comms and Wireless
– Hardware Prototyping – live demo
▪ Theory and Implementation
– Linear algebra
– Matrix decomposition: QR vs Cholesky
– Latency vs. area tradeoffs
▪ HDL Coder Implementation
– HDL Coder implementation
– Resource mapping and utilization
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Agenda
▪ Introduction
– Applications: Radar, Comms and Wireless
– Hardware Prototyping – live demo
▪ Theory and Implementation
– Linear algebra
– Matrix decomposition: QR vs Cholesky
– Latency vs. area tradeoffs
▪ HDL Coder Implementation
– HDL Coder implementation
– Resource mapping and utilization
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FPGA Implementation Challenges
▪ Fixed-Point Math
▪ Performance vs Area tradeoffs
▪ Data Rate vs Clock Rate
▪ Project Timeline
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HDL Implementation Workflow
MATLAB
Reference
MATLAB
Hardware
Architecture Fixed Point
Designer
Fixed-point Simulink
Implementation
HDL Coder
HDL Code Generation
and Optimization
Integrated Verification
HDL Verification
and Targeting
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MATLAB MVDR reference code
function Y = mvdr_beamform(X, sv)
% form covariance matrix
Ecx = X.'*conj(X);
% compute weight vector 100+ hours of
wp = Ecx\sv; design time saved!
% normalize response
w = wp/(sv'*wp);
% form output beam
Y = X*conj(w);
end
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HDL Implementation of MVDR Beamforming
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HDL Implementation of MVDR Beamforming
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Form Covariance Matrix
▪ For Each subsystem % form covariance matrix
– Process elements independently Ecx = X.'*conj(X);
– Concatenate results into outputs
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Moving Average
▪ Use HDL Implementation properties
to map large delays to Block RAM
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Compute Weight Vector
▪ Use Complex Matrix Solve block from
Fixed-Point Matrix Linear Algebra Library % compute weight vector
wp = Ecx\sv;
100+ hours of
design time saved!
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Normalize Response
▪ Perform divide using reciprocal and multiply
▪ Fixed-point CORDIC reciprocal “just works” % normalize response
w = wp/(sv'*wp);
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Implementation Results
Xilinx ZCU111 RFSoC Eval Board
MATLAB
Simulink Ethernet
▪ Device: xczu28dr (ZCU111)
▪ Maximum frequency: 452 MHz
▪ Resource utilization: Resource Utilization (%)
LUT 47K 11.13
LUTRAM 989 0.5
FF 40K 4.7
BRAM 2 0.2
URAM 10 12.5
DSP 92 3.5
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Resources to Get Started and Speed Adoption
▪ Getting started:
– MATLAB Onramp
– Simulink Onramp
– HDL pulse detector self-guided tutorial and videos
▪ Proof-of-concept guided evaluations
– FREE support via weekly WebEx meetings using custom sample designs
– MathWorks coaches customers on “how to fish” through weekly WebEx sessions
▪ Training & consulting services
– HDL code generation, FPGA signal processing & Zynq programming training courses
– Consulting service on deep technical coaching, custom design / hardware and more
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Beamforming Demonstration
▪ ZCU111 RFSoC Adaptive Beamformer demo for 4x4 matrix solve for 4 channel ADC/DAC
▪ Places nulls in interference locations and maximizes beam pattern for steering direction
▪ Interactively steer angles for interference and beam pattern at run-time
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File Exchange
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