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4. Sequential Logic circuits

Chapter Outline
• Introduction
• Latches
• Flip-Flops
• Types of Flip-flops
• One Shots
• The 555 Timer

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4. Sequential Logic circuits 4. Sequential Logic circuits

Introduction Introduction
• A sequential circuit consists of a feedback path, and • Based on timing signal sequential circuits can be
employs some memory elements. classified into
Combinational
outputs Memory outputs
I. Asynchronous sequential circuit and
II. Synchronous sequential circuits
Combinational Memory
logic elements

External inputs
Sequential circuit = Combinational logic + Memory Elements

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4. Sequential Logic circuits 4. Sequential Logic circuits

Introduction
I. Asynchronous SLC
• A sequential logic whose behavior can be defined from
the knowledge of its signal at discrete time.
• Its behavior depends upon the input signal at any instant
of time and the order in which the inputs changes
• The storage element is time delay element whose storage
capacity is due to the time required for signal to
propagate through the device.
• Also called a combinational logic circuit with feedback
loop.
Introduction
II. Synchronous SLC
• Employs signals that affect the storage element at
discrete instants of time.
• Synchronization is achieved by a clock generator
that provides a periodic train of clock pulses which
are applied with other signals that specify the
required change in the storage element.
• Some times clocked sequential circuits
• The common storage element is Flip – Flops

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4. Sequential Logic circuits 4. Sequential Logic circuits

Introduction LATCHES AND FLIP-FLOPS
• To remember the past inputs and state of logic, sequential • A single latch or flip-flop can store only one bit of
logic circuits require memory element. information. This bit of information that is stored in a latch
• Memory element is just like CLC but differ only in there or flip-flop is referred to as the state of the latch or flip-
requirement of feedback loop circuits and it forms the basis flop.
for all memory elements. • Hence, a single latch or flip-flop can be in either one of
• The basic memory element to store information two states: 0 or 1. This state value is always available at
i. Latches the output.
ii. Flip - Flops • Consequently, the content of a latch or a flip-flop is the
state value, and is always equal to its output value.
• Hence, they are the fundamental building blocks for all
sequential circuits • We say that a latch or a flip-flop changes state when its
content changes from a 0 to a 1 or vice versa.

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4. Sequential Logic circuits
LATCHES AND FLIP-FLOPS
The main difference between a latch and a flip-flop
• for a Latch, its state or output is constantly affected by
its input as long as its enable signal is asserted.
• In other words, when a latch is enabled, its state
changes immediately when its input changes.
• When a latch is disabled, its state remains constant,
thereby, remembering its previous value.
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4. Sequential Logic circuits
LATCHES AND FLIP-FLOPS
• In a microprocessor system, changes usually occur at
precisely the same moment.
• Hence, flip-flops are used more often than latches,
since they can all be synchronized to change only at
the active edge of the enable signal.
• This enable signal for the flip-flops is usually the
global controlling clock signal.
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4. Sequential Logic circuits
LATCHES AND FLIP-FLOPS
The main difference between a latch and a flip-flop
• On the other hand, a Flip – Flop changes state only at
the active edge of its enable signal i.e., at precisely the
moment when either its enable signal rises from a 0 to
a 1 (rising edge), or from a 1 to a 0 (the falling edge).
• However, after the rising or falling edge of the enable
signal, and during the time when the enable signal is at
a constant 1 or 0, the flip-flop’s state remains constant
even if the input changes.
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4. Sequential Logic circuits
LATCHES AND FLIP-FLOPS
• Basically, there are four main types of flip-flops
• SR, D, JK, and T
• The major differences between them are the number of
inputs they have and how their contents change.
• Today, sequential circuits are designed mainly with D
flip-flops because of their ease of use
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4. Sequential Logic circuits 4. Sequential Logic circuits

Bistable element Bistable element
• The simplest memory circuit constructed by • Bistable element circuit and state table are shown
connecting two inverters in series, bellow
• Has two symmetrical nodes labeled Q and Q' both
which can serve as either an input or an output signal.
• the circuit has two stable states: Q= 0 and Q= 1; hence,
the name ―Bistable.‖
• Q is the state variable, so that the state of the circuit is
• The state equation for bistable element is
the value at Q.
• 𝑄𝑖 𝑄𝑖
+1 =

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4. Sequential Logic circuits 4. Sequential Logic circuits

SR Latch
SR Latch
• Active – LOW input 𝑆’𝑅’ Latch
• A circuit with two cross coupled NAND gate or NOR
gate
• Is of two type
• Active – HIGH input SR Latch and
• i.e., a 1 asserts them, and a 0 de-asserts them
• Active – LOW input 𝑆’𝑅’ Latch • Active – HIGH input SR Latch
• i.e., a 0 asserts them, and a 1 de-asserts them
• The circuit diagram and the sate table are shown
bellow.

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4. Sequential Logic circuits 4. Sequential Logic circuits

Clocked S - R Latch D LATCH
• Adding two NAND gates to the basic S - R NAND latch gives
• Eliminates the undesirable condition of the
the clocked S – R latch:
indeterminate state in SR – Latch.
• C is ―control‖ or ―clock‖.
• Achieved by adding an inverter to SR – Latch
• Behavior similar to the basic S-R latch except that the
S and R inputs are only observed when the line C is high.

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4. Sequential Logic circuits 4. Sequential Logic circuits

Flip – Flops Flip – Flops
• Flip-flops: synchronous bistable devices • S-R, D and J-K edge-triggered flip-flops. Note the ―>‖
• Output changes state at a specified point on a symbol at the clock input.
triggering input called the clock.
• Change state either at the positive edge (rising edge) or
at the negative edge (falling edge) of the clock signal.

Clock signal

Positive edges Negative edges

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4. Sequential Logic circuits 4. Sequential Logic circuits

S-R Flip – Flops S-R Flip – Flops
 S-R flip-flop: on the triggering edge of the clock pulse,  It comprises 3 parts:
S=HIGH (and R=LOW) a SET state a basic NAND latch
R=HIGH (and S=LOW) a RESET state a pulse-steering circuit
both inputs LOW a no change
a pulse transition detector (or edge detector) circuit
both inputs HIGH a invalid
 The pulse transition detector detects a rising (or falling) edge and produces a
 Characteristic table of positive edge-triggered S-R flip-flop: very short-duration spike.

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4. Sequential Logic circuits 4. Sequential Logic circuits

D Flip – Flops D Flip – Flop
 D flip-flop: single input D (data)  Application: Parallel data transfer.
D=HIGH a SET state To transfer logic-circuit outputs X, Y, Z to flip-flops Q1, Q2 and
D=LOW a RESET state Q3 for storage.
 Q follows D at the clock edge.
 Convert S-R flip-flop into a D flip-flop: add an inverter.

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4. Sequential Logic circuits 4. Sequential Logic circuits

J-K Flip-flop J-K Flip-flop
J-K flip-flop: Q and Q' are fed back to the pulse-
steering NAND gates.
No invalid state.
Include a toggle state.
J=HIGH (and K=LOW) a SET state
K=HIGH (and J=LOW) a RESET state
both inputs LOW a no change
both inputs HIGH a toggle

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4. Sequential Logic circuits 4. Sequential Logic circuits

T Flip-flop T Flip – Flop

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4. Sequential Logic circuits 4. Sequential Logic circuits

S-R Master-Slave Flip-Flop SR Master – slave Flip – Flops
• The change in the flip-flop output is delayed by the pulse
• Consists of two clocked width which makes the circuit slower or
S-R latches in series • S and/or R are permitted to change while C = 1
with the clock on the • Suppose Q = 0 and S goes to 1 and then back to 0 with R remaining
second latch inverted at 0
• The master latch sets to 1
• The input is observed • A 1 is transferred to the slave
by the first latch with C = 1 • Suppose Q = 0 and S goes to 1 and back to 0 and R goes to 1 and
back to 0
• The output is changed by the second latch with C = 0
• The master latch sets and then resets
• The path from input to output is broken by the • A 0 is transferred to the slave

difference in clocking values (C = 1 and C = 0). • This behavior is called 1s catching

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4. Sequential Logic circuits 4. Sequential Logic circuits

SR Master – slave Flip – Flops
• Use edge-triggering instead of master-slave
• An edge-triggered flip-flop ignores the pulse while it
is at a constant level and triggers only during a
transition of the clock signal
• Edge-triggered flip-flops can be built directly at the
electronic circuit level, or
• A master-slave D flip-flop which also exhibits edge-
triggered behavior can be used.
Edge-Triggered D Flip-Flop
• The edge-triggered D flip-flop is the
same as the master-slave D flip-flop
• It can be formed by:
• Replacing the first clocked S-R latch with a clocked D latch or
• Adding a D input and inverter to a master-slave S-R flip-flop
• The delay of the S-R master-slave flip-flop can be avoided since
the 1s-catching behavior is not present with D replacing S and R
inputs
• The change of the D flip-flop output is associated with the
negative edge at the end of the pulse
• It is called a negative-edge triggered flip-flop

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4. Sequential Logic circuits 4. Sequential Logic circuits

Positive Edge-Triggered D Flip-Flop Flip – Flops with Asynchronous Inputs
• Formed by S-R, D and J-K inputs are synchronous inputs, as data
adding inverter on these inputs are transferred to the flip-flop’s output
only on the triggered edge of the clock pulse.
to clock input
Asynchronous inputs affect the state of the flip-flop
independent of the clock; example: preset (PRE) and
clear (CLR) [or direct set (SD) and direct reset (RD)]
• Q changes to the value on D applied at the positive When PRE=HIGH, Q is immediately set to HIGH.
clock edge within timing constraints to be specified When CLR=HIGH, Q is immediately cleared to LOW.
• Our choice as the standard flip-flop for most sequential Flip-flop in normal operation mode when both PRE
circuits and CLR are LOW.

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4. Sequential Logic circuits 4. Sequential Logic circuits

Flip – Flops with Asynchronous Inputs Flip – Flops with Asynchronous Inputs
• A J-K flip-flop with active-LOW preset and clear inputs • Example showing how a clocked flip-flop responds to asynchronous inputs.

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4. Sequential Logic circuits 4. Sequential Logic circuits

Analysis of clocked sequential logic circuits
• Example: construct the following sequential logic
circuit sing D flip flop
• 𝐷𝐴 = 𝐴 ⊗ 𝑥 ⊗ 𝑦
Multivibrator
• It is an electronic circuit used to implement a variety of simple two-state systems
such as oscillators, timers and flip-flops. It is characterized by two amplifying
devices (transistors, electron tubes or other devices) cross-coupled by resistors and
capacitors.
• There are three types of multivibrator circuit:
• Astable, in which the circuit is not stable in either state—it continuously oscillates
from one state to the other. Due to this, it does not require a input (Clock pulse or
other).
• Monostable or One Shot, in which one of the states is stable, but the other is not—
the circuit will flip into the unstable state for a determined period, but will eventually
return to the stable state. Such a circuit is useful for creating a timing period of fixed
duration in response to some external event. A common application is in eliminating
switch bounce.
• Bistable, in which the circuit will remain in either state indefinitely. The circuit can
be flipped from one state to the other by an external event or trigger. Such a circuit is
important as the fundamental building block of a register or memory device. This
circuit is also known as a latch or a flip-flop.

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4. Sequential Logic circuits 4. Sequential Logic circuits

• Astable/Monostable Multivibrators
Astable Multivibrator:
• An astable multivibrators is also called a free-running
multivibrators.
• The astable multivibrators generates a continuous flow
of pulse.
• The versatile 555 Timer IC can be used to implement
an astable multivibrators.
• The output frequency of the multivibrator can be
increased by decreasing the value of the resistors
and/or capacitor.

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4. Sequential Logic circuits 4. Sequential Logic circuits

• Astable Multivibrators
• 555 timer IC wired as a astable multivibrator
Monostable Multivibrator or one-shot :
• A monostable multivibrator is also called a one-shot
multivibrator.
• When the one-shot is triggered, the multivibrator
generates a single short pulse.
• The input trigger may be an entire pulse, a L-to-H or
H-to-L transition of the trigger pulse.
• The output pulse may be either a positive or a negative
pulse.
• The time duration of the output pulse can be adjusted
by using different resistor-capacitor combinations.

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4. Sequential Logic circuits 4. Sequential Logic circuits

Monostable Multivibrator: Monostable Multivibrator
• 74121 IC wired to generate single clock pulse
• 555 timer IC wired as a one shot

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