UNIT 4

SYNCHRONOUS
SEQUENTIAL LOGIC
 In this chapter you will learn about:
◦ Difference between combinational and
sequential circuits
◦ Latches ( SR Latch using NOR , SR Latch
using NAND gates)
◦ Types of Flip flop
◦ Characteristic equation of Flip flops
◦ Flip flop conversions
Sequential Circuits
Combinational Vs Sequential Circuits
Combinational Vs Sequential Circuits
Combinational Circuits
1. Output is only pure function of the
present input.
2. Do not have memory element.
3. Time independent.
4. Faster in speed.
5. Easy to design.
6.Elementary building blocks:
Logic gates.
7. No need of triggering.
8. Eg: decoder, encoder, mux, demux,
code converter,compaarators,….etc
Sequential Circuits
1. Output depends not only on the
present input but also on past history
of inputs and outputs.
2. Memory element to store the
intermediate results.
3. Time dependent.
4. Slower in speed
5.Computationally harder to design.
6. Elementary building blocks:
Flip Flops.
7. Need triggering since it is clock
dependent.
88.Eg: FF’s, Counters,…..etc.
SR Latch Using NOR Gates
SR Latch Using NOR Gates
SR Latch Using NOR Gates
SR Latch Using NOR Gates
SR Latch Using NAND Gates
 Flip Flop
• A Flip-flop (FF) is an electronic circuit that stores digital information, i.e.,
a single bit, when a specific type of edge (rising or falling) of a clock signal
is detected.
The pins of a FF are divided in 3 parts:
• Inputs - one or more inputs containing the data to be stored
• Clock - a specific edge (rising or falling) triggers the storage of the
information
• Outputs - one output (and maybe its complement) that depends on
the inputs and optionally on the current state
 Types of Flip Flop
• SR Flip Flop
• JK Flip Flop
• D Flip Flop
• T Flip Flop
 SR Flip Flop
( Positive edge triggered SR FF)
JK Flip Flop
D Flip Flop
T Flip Flop
 Race around condition
• For JK FF, if J = K = 1, output keeps on toggling,
which leads to uncertainty in determining the
output of flip flop.

Methods to eliminate Race around condition

• 1. Increasing the delay of flip flop
• 2. Use of edge triggered flip flop
• 3. Use of master slave JK flip flop
 Symbol, Charactristic Equation ,
Excitation Table for SR FlipFlop & JK FlipFlop
 Symbol, Charactristic Equation ,
Excitation Table for D FlipFlop & T FlipFlop
 flip-flop conversions
Steps for converting one flip-flop to the other.
1. Consider the  Characteristic Table of desired flip-flop.
2. Fill the excitation values (inputs) of given flip-flop for each combination of
present state and next state. The  Excitation Table for all flip-flops is shown
below.

3. Get the Simplified Expressions for each excitation input.

If necessary, use K-maps for simplifying.
4. Draw the Circuit Diagram of desired flip-flop according to the simplified expressions
using given flip-flop and necessary logic gates .
SR Flip-Flop to D Flip-Flop
D Flip-Flop to T Flip-Flop
JK Flip-Flop to T Flip-Flop
T Flip-Flop to D Flip-Flop
SR Flip-Flop to JK Flip-Flop
SR Flip-Flop to T Flip-Flop
JK Flip-Flop to D Flip-Flop
JK Flip-Flop to SR Flip-Flop
 Latch Vs Flip-Flop
Latches
1. It is based on enable signal
2. Level sensitive device
3. Latch continuously checks its inputs
and changes its output correspondingly
4. Latch is asynchronous device.
5. Can not be used as a register
6. Works with only binary inputs
7. Operation of a latch is faster
Flip Flops
1. It is based on clock signal
2. Edge sensitive device
3. Flip Flop continuously checks its
inputs and checks its output
correspondingly only at times
determined by clocking signal
4. FF is synchronous device.
5. Can be used as a register
6. Works with binary inputs as well as
the clock signal
7. FFs are comparatively slower than
latches due to clock signal