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Introduction
• So far we have seen Combinational Logic
– The output(s) depends only on the current values of the input
variables
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General Digital System dce
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Synchronous and Asynchronous
Sequential Logic
• Synchronous
– The timing of all state transitions is controlled by a common
clock
– Changes in all variables occur simultaneously
• Asynchronous
– State transitions occur independently of any clock and normally
dependent on the timing of transitions in the input variables
– Changes in more than one output do not necessarily occur
simultaneously
• Clock
– A clock signal is a square wave of fixed frequency
– Often, transitions will occur on one of the edges of clock pulses
• i.e. the rising edge or the falling edge
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Digital Systems 1
dce General flip-flop symbol and definition of its two dce
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A NAND latch is an example of a bistable device 2019
Setting the NAND Flip-Flop
NAND
001
011
101
110
NAND
001
011
101
110
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Digital Systems 2
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Resetting the NAND Flip-Flop 2019
Function table of a NAND latch
NAND
001
011
101
110
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Digital Systems 3
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Determine Q 2019 A example of NAND latch Application
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Digital Systems 4
dce SR latch useful when temporary setting is used to dce
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activate switch
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Digital Pulses
The NAND FF is used to • The transition from low to high on a positive
provide a bounce free switch pulse is called rise time (tr).
so that the 1 KHz pulse can
propagate to the output – Rise time is measured between the 10% and 90%
without distortion. points on the leading edge of the voltage waveform.
• The transition from high to low on a positive
pulse is called fall time (tf).
– Fall time is measured between the 90% and 10%
points on the trailing edge of the voltage waveform.
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Rise and Fall times 2019
Rise and Fall times
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Digital Systems 5
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Digital Systems 6
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Clocked SR Flip-Flop 2019 Clocked SR Flip-Flop
• Clocked S-R flip-flop that triggers only on negative-going • Implementation of edge-detector circuits used in edge-
transitions. triggered flip-flops: (a) PGT; (b) NGT. The duration of the
CLK* pulses is typically 2–5 ns.
• Simplified version of
the internal circuitry
for an edge-
triggered S-R flip-
flop.
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Digital Systems 7
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Edge-triggered J-K flip-flop 2019
Clocked D Flip-Flop
• One data input.
• The output changes to the value of the input at
either the positive going or negative going clock
trigger.
Digital Systems 8
dce Edge-triggered D flip-flop dce
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Parallel transfer of binary data using D flip-flops
implementation from a J-K flip-flop
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Digital Systems 9
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D Latch 2019
Asynchronous Inputs
• Waveforms showing the two modes of operation of the
transparent D latch. • Inputs that depend on the clock are synchronous.
• Most clocked FFs have asynchronous inputs that
do not depend on the clock.
• The labels PRE and CLR are used for
asynchronous inputs.
• Active low asynchronous inputs will have a bar
over the labels and inversion bubbles.
• If the asynchronous inputs are not used they will
be tied to their inactive state.
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2019 Clocked J-K flip-flop with asynchronous inputs
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Digital Systems 10
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Flip–Flop Propagation Delays
Flip-Flop Timing Considerations
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Clock LOW and HIGH time
Potential Timing Problems in FF Circuits
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Digital Systems 11
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Propagation Delay in Synchronous Circuits 2019
Flip-Flop Synchronization
• Most systems are primarily synchronous
in operation, in that changes depend on
the clock.
•The input (J2) to Q2 must • Asynchronous and synchronous
be held for tH after the operations are often combined.
clock edge.
• The random nature of asynchronous
•This will occur only if tPHL inputs can result in unpredictable results.
> tH.
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Digital Systems 12
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A =0, EN =1, CLR = 0, sets B = 0 50
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2019 Synchronous transfer of contents of register X into 2019
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Digital Systems 13
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Serial Data Transfer: Shift Registers 2019
Four-bit Shift Register
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Serial transfer from X register into Y register
Frequency Division and Counting
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Digital Systems 14
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MOD-8 Asynchronous Counter 2019
State Table & Diagram of MOD-8 Asynchronous Counter
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Example of Microprocessor Interfacing
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Digital Systems 15
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Schmitt-Trigger Response (two thresholds)
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Schmitt-Trigger Response (two thresholds) 2019
Digital Systems 16
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One-shot 2019
Retriggerable and Nonretriggerable Operation
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one-shot
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Digital Systems 17
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Clock Generator Circuit: Schmitt-trigger Oscillator 2019 Clock Generator Circuit: 555 Timer
555 timer IC used astable multivibrator.
Schmitt-trigger oscillator using a 7414 INVERTER. A 7413
Schmitt-trigger NAND may also be used.
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Digital Systems 18