Lecture 2

GEL314: Digital Electronics
Lecture 2: Storage Elements and Analysis
Professor Charbel Fares

charbelfares@usek.edu.lb
2
Overview
§ Storage Elements and Analysis
s
• Introduction to sequential circuits
• Types of sequential circuits
ar e
• Storage elements
§ Latches
el F
§ Flip-flops
ar b
h
• Sequential circuit analysis
C
f.
§ State tables
Pr o §
§
§
State diagrams
Equivalent states
Moore and Mealy Models
GEL 314 - Lecture 2 Prof. Charbel Fares

3
Introduction to Sequential Circuits
Inputs Outputs
Combina-
§ A Sequential
circuit contains:
r
Storage
es tional
a
Logic
F
Elements
• Storage elements:
Latches or Flip-Flops
bel State
Next
State
• Combinational Logic:
har
§ Implements a multiple-output
f. C
switching function
§ Inputs are signals from the outside.
Pr o§ Outputs are signals to the outside.

§ Other inputs, State or Present State, are
signals from storage elements.
§ The remaining outputs, Next State are
inputs to storage elements.
4
Introduction to Sequential Circuits
Inputs Outputs
Combina-
r es
Storage
tional
a
Logic
F
Elements
§ Combinatorial Logic
bel State
Next
State
r
• Next state function
a
Next State = f(Inputs, State)
h
C
• Output function (Mealy)
r of.
Outputs = g(Inputs, State)
• Output function (Moore)
P Outputs = h(State)
§ Output function type depends on specification and affects
the design significantly

5
Types of Sequential Circuits
§ Depends on the times at which:

• storage elements observe their inputs, and
es
• storage elements change their state
r
a
§ Synchronous
l F
• Behavior defined from knowledge of its signals at discrete
instances of time
e
r b
• Storage elements observe inputs and can change state only in
a
relation to a timing signal (clock pulses from a clock)
§ Asynchronous
C h
r of.
• Behavior defined from knowledge of inputs at any instant of
time and the order in continuous time in which inputs change
P • If clock just regarded as another input, all circuits are

asynchronous!
• Nevertheless, the synchronous abstraction makes complex
designs tractable!

6
Discrete Event Simulation
§ To understand the time behavior of a sequential

circuit we use discrete event simulation.
§ Rules:
r es
Fa
• Gates modeled by an ideal (instantaneous) function
l
e
and a fixed gate delay
r b
• Any change in input values is evaluated to see if it
a
causes a change in output value
C h
• Changes in output values are scheduled for the fixed
r of.
gate delay after the input change
• At the time for a scheduled output change, the
P output value is changed along with any inputs it
drives

7
Simulated NAND Gate
§ Example: A 2-Input NAND gate with a 0.5 ns. delay:

F(Instantaneous)
s
A
r e
DELAY 0.5 ns. F
a
B
el F
§ Assume A and B have been 1 for a long time
§ At time t=0, A changes to a 0 at t= 0.8 ns, back to 1.
ar b
t (ns) A B
h
F(I)
C
F Comment
.
–¥
f
1 1 0 0 A=B=1 for a long time
0
Pr
0.5 o
1Þ 0 1
0 1
1Ü 0
1
0 F(I) changes to 1
1Ü 0 F changes to 1 after a 0.5 ns delay
0.8 1Ü 0 1 1Þ 0 1 F(Instantaneous) changes to 0
0.13 1 1 0 1Þ 0 F changes to 0 after a 0.5 ns delay
8
Gate Delay Models
§ Suppose gates with delay n ns are
r es
represented for n = 0.2 ns, n = 0.4 ns,
n = 0.5 ns, respectively:
l Fa
0.2
r be
0.4 0.5
ha
f. C
Pr o
9
Circuit Delay Model
§ Consider a simple A
2-input multiplexer: 0.4
§ With function: 0.2
r es 0.5
Y
a
• Y = A for S = 0
S
• Y = B for S = 1
B
el F 0.4
ar b
h
A
B
f. C
o
S
S
Y Pr
§ “Glitch” is due to delay of inverter
10
Storing State
§ What if A con-
nected to Y? 0.4
§ Circuit becomes:
r es
0.2
0.5
a
§ With function:
S
• Y = B for S = 1, and
Y(t) dependent on
el
B F 0.4
Y
B r
Y(t – 0.9) for S = 0
a b
S
C h
S
r of.
Y
P
§ The simple combinational circuit has now become a
sequential circuit because its output is a function of a time
sequence of input signals!
GEL 314 - Lecture 2 Y is stored value in shaded area
Prof. Charbel Fares
11
Storing State
§ Simulation example as input signals change with time.

Changes occur every 100 ns, so that the tenths of ns delays
are negligible.
r es
Time B
1
S
0
Y
0
F
Comment
l a
Y “remembers” 0
1
1
1
0
1
1
r be
Y = B when S = 1
Now Y “remembers” B = 1 for S = 0
0 0 1
haNo change in Y when B changes
C
0 1 0 Y = B when S = 1
r of. 0
1
0
0
0
0
Y “remembers” B = 0 for S = 0
No change in Y when B changes
P
§ Y represent the state of the circuit, not just an output.

12
Storing State
§ Suppose we place
an inverter in the
0.4
0.2
“feedback path.”
0.2
S
ar e 0.5
B
el F 0.4
Y
ar b
§ The following behavior results:
§ The circuit is said
C h B S Y Comment
.
to be unstable. 0 1 0 Y = B when S = 1
r of
§ For S = 0, the 1
1
1
0
1
1 Now Y “remembers” A
P
circuit has become 1 0 0 Y, 1.1 ns later
what is called an 1 0 1 Y, 1.1 ns later
oscillator. Can be 1 0 0 Y, 1.1 ns later
used as basic clock.
13
Basic (NAND) S – R Latch
§ “Cross-Coupling” S (set)
Q
two NAND gates gives
the S -R Latch:
r es
§ Which has the time
l Fa R (reset) Q
sequence behavior:
r be Time R S Q Q Comment
ha 1 1 ? ? Stored state unknown
C 1 0 1 0 “Set” Q to 1
depends on previous state of Q and Q bar
r of.
§ S = 0, R = 0 is
1
0
1
1
1
0
0
1
Now Q “remembers” 1
“Reset” Q to 0
P
forbidden as
input pattern
1
0
1
1
0
1
0
1
?
1
1
?
Both go high
Unstable!

14
Basic (NOR) S – R Latch
§ Cross-coupling two R (reset)

Q
s
NOR gates gives the
S – R Latch:
ar e
§ Which has the time
el F
S (set) Q
b
sequence
behavior:
Time R S
0
har
0
Q
?
Q
?
Comment
Stored state unknown
f. C0
0
1
0
1
1
0
0
“Set” Q to 1
Pr o 1
0
1
0
0
1
0
0
0
1
1
0
“Reset” Q to 0
Both go low
0 0 ? ? Unstable!

15
Clocked S - R Latch
§ Adding two NAND S

gates to the basic Q
S - R NAND latch C
r es
gives the clocked
Fa
C is the enable
l
S – R latch: Q
r be R
a
§ Has a time sequence behavior similar to the basic S-R
h
C
latch except that the S and R inputs are only observed
r of.
when the line C is high.
§ C means “control” or “clock”.
P
16
Clocked S - R Latch
§ The Clocked S-R Latch can be described by a table:

Q(t) S R Q(t+1) Comment
s
S
e
Q 0 0 0 0 No change
C
Far 0 0 1 0 Clear Q
l
0 1 0 1 Set Q
e
Q
b
R 0 1 1 ??? Indeterminate
r
when C is 1 it S and R come into play otherwise useless
a
1 0 0 1 No change
§ The table describes
what happens after the
C h 1 0 1 0 Clear Q
f.
1 1 0 1 Set Q
P o
clock [at time (t+1)]
r
based on:
• current inputs (S,R) and
1 1 1 ??? Indeterminate
the previous state is Q(t) and we took C as 1 for this truth table
• current state Q(t).

17
D Latch
§ Adding an inverter D
Q
s
to the S-R Latch,
gives the D Latch: C
ar e
§ Note that there are
no “indeterminate”
el F Q
states!
ar b
h
The graphic symbol for a
C
C D Q(t+1) Comment D Latch is:
0 0
r of. 0 No change
I am storing D here, if D changes
D Q
P
0 1 1 Set Q and C is on, the new value of D
is stored, otherwise it will not
1 0 0 Clear Q store the new data
C Q
1 1 1 No Change

18
Flip-Flops
§ The latch timing problem

§ Master-slave flip-flop
r es
§ Edge-triggered flip-flop
l Fa
r be
§ Standard symbols for storage elements
ha
§ Direct inputs to flip-flops
f. C
Pr o
19
The Latch Timing Problem
§ In a sequential circuit, paths may exist through
s
combinational logic:
r e
• From one storage element to another
a
element
el F
• From a storage element back to the same storage
ar b
§ The combinational logic between a latch output
h
and a latch input may be as simple as an
C
f.
interconnect
r o
P
§ For a clocked D-latch, the output Q depends on
the input D whenever the clock input C has
value 1
20
§ Consider the following circuit:
Y
s
D Q
ar e
Clock
e l
§ Suppose that initially Y = 0. F C Q
Clock
ar b
Y
C h in loop since the inverter exists on the input D
r of.
§ As long as C = 1, the value of Y continues to change!
§ The changes are based on the delay present on the loop
P
through the connection from Y back to Y.
§ This behavior is clearly unacceptable.
§ Desired behavior: Y changes only once per clock pulse
21
§ A solution to the latch timing problem is
r es
to break the closed path from Y to Y
within the storage element
l Fa
§ The commonly-used, path-breaking
r be
solutions replace the clocked D-latch
with:
ha
f. C
• a master-slave flip-flop or
Pr o
• an edge-triggered flip-flop

22
S-R Master-Slave Flip-Flop
§ Consists of two clocked S S Q S Q Q
S-R latches in series C
s
C C
with the clock on the
r e
R R Q R Q
Q
a
second latch inverted
§ The input is observed
el F clock 1, first latch reading 2nd

not, when clock becomes 0, the
b
by the first latch with C = 1
r
2nd latch turns on and takes the
value of the first latch.
a
§ The output is changed by the second latch with C = 0
h
sometimes a
C
§ The path from input to output is broken by the glitch may
f.
occur, since the
difference in clocking values (C = 1 and C = 0). set and reset
r o
may both occur
§ The behavior demonstrated by the example with D inin the
P
same time
small pulses
driven by Y given previously is prevented since the
clock must change from 1 to 0 before a change in Y
based on D can occur.
23
Flip-Flop Problem
§ The change in the flip-flop output is delayed by
the pulse width which makes the circuit slower
r es
§ S and/or R are permitted to change while C = 1
Fa
• Suppose Q = 0 and S goes to 1 and then back to 0 with
l
e
R remaining at 0
r b
§ The master latch sets to 1
a
h
§ A 1 is transferred to the slave
. C
• Suppose Q = 0 and S goes to 1 and back to 0 and R
f
o
goes to 1 and back to 0
Pr § The master latch sets and then resets

§ A 0 is transferred to the slave
• This behavior is called 1s catching

24
Flip-Flop Solution
§ Use edge-triggering instead of master-slave
r es
§ An edge-triggered flip-flop ignores the pulse
while it is at a constant level and triggers only
during a transition of the clock signal
l Fa
be
§ Edge-triggered flip-flops can be built directly at
r
the electronic circuit level, or
ha
. C
§ A master-slave D flip-flop which also exhibits
f
Pr o
edge-triggered behavior can be used.
Edge triggering means it will only read the first pulse after the edge rise, no matter what is after it

25
Edge-Triggered D Flip-Flop
§ The edge-triggered D D S
Q Q Q
D flip-flop is the
s
C
same as the master-
e
C C
r
Q R Q Q
slave D flip-flop
§ It can be formed by:
l Fa
r be
• Replacing the first clocked S-R latch with a clocked D latch
a
§ The delay of the S-R master-slave flip-flop can be
h
C
avoided since the 1s-catching behavior is not present
r of.
with D replacing S and R inputs
§ The change of the D flip-flop output is associated with
P
the negative edge at the end of the pulse
§ It is called a negative-edge triggered flip-flop
Leh esma negative edge ?
26
Positive-Edge Triggered D Flip-Flop
§ Formed by D D Q S Q
Q
adding inverter
s
C
to clock input
r e
C C Q R Q Q
l Fa
r be
a
§ Q changes to the value on D applied at the
h
f.
be specified C
positive clock edge within timing constraints to
Pr o
§ Our choice as the standard flip-flop for most
sequential circuits

Standard Symbols for Storage 27
Elements
S S D D
Latches
R
r es R C C
a
SR SR D with 1 Control D with 0 Control
F
(a) Latches
§ Master-Slave:
Postponed output
bel
S S D D
indicators
har C
R
C
R C C
f.
§ Edge-Triggered: C Triggered SR Triggered SR Triggered D Triggered D
o
(b) Master-Slave Flip-Flops
Pr
Dynamic
indicator negative edge
D
C
D
C
positive edge
D flip flops
Triggered D Triggered D
(c) Edge-Triggered Flip-Flops
28
Direct Inputs
§ At power up or at reset, all or part

of a sequential circuit usually is S
e
initialized to a known state before
r s D Q
a
it begins operation
el F
§ This initialization is often done C
R
Q
b
outside of the clocked behavior
ar
of the circuit, i.e., asynchronously.
h
C
§ Direct R and/or S inputs that control the state of the
r of.
latches within the flip-flops are used for this
initialization.
P
§ For the example flip-flop shown
• 0 applied to R resets the flip-flop to the 0 state
• 0 applied to S sets the flip-flop to the 1 state
29
Sequential Circuit Analysis
§ General Model
Inputs Outputs
• Current State
s
Combina-
at time (t) is
stored in an Storage
ar e tional
F
Logic
l
array of Elements
flip-flops.
r be State
Next
State
ha
• Next State at time (t+1)
f. C
is a Boolean function of CLK
o
State and Inputs.
Pr• Outputs at time (t) are a Boolean function of

State (t) and (sometimes) Inputs (t).

30
Example 1
§ Input: x(t) x
s D Q A
§ Output: y(t)
ar e C Q A
§ State: (A(t), B(t))
el F
§ What is the Output
ar b
h
Function? D Q B
§ Whato f. C CP C Q
P r is the Next State

Function?
y

31
Example 1
§ Boolean equations
for the functions:
r es x
D Q A
a
• A(t+1) = A(t)x(t)
F
C Q A
l
+ B(t)x(t) Next State
A
r be
• B(t+1) = (t)x(t)
ha
• y(t) = x(t)(B(t) + A(t)) Q B
C
D
r of. CP C Q'
P Output
y

32
Example 1
§ Where in time are inputs, outputs and
states defined?
r es
l Fa
r be
1
ha
C
0
r of. 1
0 0
P 0
0
1

33
State Table Characteristics
§ State table – a multiple variable table with the

following four sections:
r es
• Present State – the values of the state variables for
each allowed state.
l Fa
• Input – the input combinations allowed.
r be
• Next-state – the value of the state at time (t+1) based
a
on the present state and the input.
h
C
• Output – the value of the output as a function of the
r of.
present state and (sometimes) the input.
§ From the viewpoint of a truth table:
P • the inputs are Input, Present State
• and the outputs are Output, Next State

34
Example 1: State Table

§ The state table can be filled in using the next state and
output equations: A(t+1) = A(t)x(t) + B(t)x(t)
§ B(t+1) =`A (t)x(t)
r es
§ y(t) =`x (t)(B(t) + A(t))
l Fa
b
Present State Input
r e Next State Output
a
A(t) B(t) x(t) A(t+1) B(t+1) y(t)
0
0
0
0
C h 0
1
0
0
0
1
0
0
r of. 0
0
1
1
0
1
0
1
0
1
1
0
P 1
1
1
0
0
1
0
1
0
0
1
0
0
0
0
1
0
1
1 1 1 1 0 0
35
Example 1: Alternate State Table
§ 2-dimensional table that matches well to a K-map.

Present state rows and input columns in Gray code
order.
r es
• B(t+1) =`A (t)x(t)
l Fa
• A(t+1) = A(t)x(t) + B(t)x(t)
be
• y(t) =`x (t)(B(t) + A(t))
r
Present
ha
Next State Output
State
f. C
x(t)=0 x(t)=1 x(t)=0 x(t)=1
o
A(t) B(t) A(t+1)B(t+1) A(t+1)B(t+1) y(t) y(t)
Pr 0 0
0 1
0 0
0 0
0 1
1 1
0
1
0
0
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 0
36
State Diagrams
§ The sequential circuit function can be

represented in graphical form as a state
es
diagram with the following components:
r
l Fa
• A circle with the state name in it for each state
• A directed arc from the Present State to the Next
be
State for each state transition
r
a
• A label on each directed arc with the Input values
h
C
which causes the state transition, and
r of.
• A label:
§ On each circle with the output value produced,
P or
§ On each directed arc with the output value
produced.
37
State Diagrams
§ Label form:
• On circle with output included:
r es
§ state/output
l F a
r b e
§ Moore type output depends only on state
included: ha
• On directed arc with the output
f. C
P r o § input/output
§ Mealy type output depends on state and
input

38
Example 1: State Diagram
x=0/y=0 x=0/y=1 x=1/y=0

§ Which type?
§ Diagram gets AB
r es x=0/y=1 1 0
a
00
confusing for
large circuits
el
x=1/y=0
F
a
§ For small circuits,
r b x=0/y=1
x=1/y=0
usually easier to
C h
r of.
understand than
the state table
01
x=1/y=0
11
P
39
Equivalent State Definitions
§ Two states are equivalent if their response
r es
for each possible input sequence is an
identical output sequence.
l Fa
§ Alternatively, two states are equivalent if
r be
their outputs produced for each input
ha
symbol is identical and their next states
f. C
for each input symbol are the same or
Pr o
equivalent.

40
Equivalent State Example
0
§ For states S3 and S2, 1
• the output for input

s
S0/0 S1
0 is 1 and input 1 is 0,
ar e 0/1
and
el F 0/1
0/1 1/0
a b
• the next state for input
r
0 is S0 and for input 1/0
h S2 S3
1 is S2.
f. C 1/0
Pr o
• By the alternative definition, states S3 and
S2 are equivalent.

41
Equivalent State Example
0/0 1/0
§ Replacing S3 and S2
by a single state gives
state diagram:
r es
S0
0/1
S1
§ Examining the new diagram,
l Fa
states S1 and S2 are equivalent since 0/1 1/0
b
• their outputs for input
r e
0 is 1 and input 1 is 0,
and
ha S2
C
• their next state for input
r of.
0 is S0 and for input
1 is S2,
0/0 1/0
1/0
P
§ Replacing S1 and S2 by a
single state gives state
diagram:
S0
0/1 S1
1/0
42
Moore and Mealy Models
§ Sequential Circuits or Sequential
r es
Machines are also called Finite State
exist:
l Fa
Machines (FSMs). Two formal models
§ Moore Model
r be § Mealy Model
ha
• Named after E.F. Moore • Named after G. Mealy
. C
• Outputs are a function
f
• Outputs are a function
of inputs AND states
o
ONLY of states
Pr
• Usually specified on the
states.
• Usually specified on the
state transition arcs.

43
Moore and Mealy Example Diagrams
§ Mealy Model State Diagram

x=1/y=0
s
maps inputs and state to outputs
ar
x=0/y=0
e 0 1
el F x=0/y=0 x=1/y=1
b
§ Moore Model State Diagram x=0
ar
maps states to outputs
h
C
0/0
.
x=0
r of
P
x=1 x=1
x=0
1/0 2/1
x=1
44
Moore and Mealy Example Tables
§ Moore Model state table maps state to

outputs
s
Present Next State Output
r e
a
State x=0 x=1
0
1
e l F0 1
0 2
0
0
ar b2 0 2 1
C h
§ Mealy Model state table maps inputs and
r o f .
state to outputs Present
State
Next State
x=0 x=1
Output
x=0 x=1
P 0
1
0 1
0 1
0 0
0 1

45
Mixed Moore and Mealy Outputs
§ In real designs, some outputs may be Moore
s
type and other outputs may be Mealy type.
r e
§ Example: the previous example can be modified
a
to illustrate this
el F0 1
b
• State 00: Moore
• States 01, 10,
har 00/0
0/1
01
C
and 11: Mealy
.
0/1
f
§ Simplifies output
r o
0/1 1/0
P
specification
1/0
10 11
1/0

46
Example 2: Sequential Circuit Analysis
A
§ Logic Diagram: D Q Z
r es C RQ
l Fa B
e
D Q
ar b
h
C RQ
f. C C
o
D Q
Pr Clock CR Q
Reset

47
Example 2: Flip-Flop Input Equations
§ Variables
• Inputs: None
r es
• Outputs: Z
l Fa
e
• State Variables: A, B, C
§ Initialization: Reset tob
h a r (0,0,0)
§ Equations
f. C
P r o
• A(t+1) =
• B(t+1) =
Z=
• C(t+1) =
48
Example 2: State Table
X’ = X(t+1) ABC A’B’C’ Z

0 0 0
r es
0 0 1
l Fa
e
0 1 0
ar
0 1 1 b
C h
1 0 0
r of. 1 0 1
P 1 1 0
1 1 1

49
Example 2: State Diagram
ABC
Reset 000
r es
111 100
l Fa 001
r be
ha
f . C
011 010 101
P r o
§ Which states are used?
§ What is the function of 110
the circuit?

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GEL314: Digital Electronics

Lecture 2: Storage Elements and Analysis

Professor Charbel Fares

§ Storage Elements and Analysis

GEL 314 - Lecture 2 Prof. Charbel Fares

Pr o§ Outputs are signals to the outside.

GEL 314 - Lecture 2 Prof. Charbel Fares

§ Depends on the times at which:

P • If clock just regarded as another input, all circuits are

GEL 314 - Lecture 2 Prof. Charbel Fares

§ To understand the time behavior of a sequential

GEL 314 - Lecture 2 Prof. Charbel Fares

§ Example: A 2-Input NAND gate with a 0.5 ns. delay:

§ Suppose gates with delay n ns are

§ Simulation example as input signals change with time.

haNo change in Y when B changes

GEL 314 - Lecture 2 Prof. Charbel Fares

ha 1 1 ? ? Stored state unknown

GEL 314 - Lecture 2 Prof. Charbel Fares

§ Cross-coupling two R (reset)

GEL 314 - Lecture 2 Prof. Charbel Fares

§ Adding two NAND S

§ The Clocked S-R Latch can be described by a table:

• current state Q(t).

1 0 0 Clear Q store the new data

GEL 314 - Lecture 2 Prof. Charbel Fares

§ The latch timing problem

§ In a sequential circuit, paths may exist through

§ A solution to the latch timing problem is

GEL 314 - Lecture 2 Prof. Charbel Fares

el F clock 1, first latch reading 2nd

Pr § The master latch sets and then resets

GEL 314 - Lecture 2 Prof. Charbel Fares

§ Use edge-triggering instead of master-slave

GEL 314 - Lecture 2 Prof. Charbel Fares

GEL 314 - Lecture 2 Prof. Charbel Fares

§ At power up or at reset, all or part

Pr• Outputs at time (t) are a Boolean function of

GEL 314 - Lecture 2 Prof. Charbel Fares

P r is the Next State

GEL 314 - Lecture 2 Prof. Charbel Fares

GEL 314 - Lecture 2 Prof. Charbel Fares

GEL 314 - Lecture 2 Prof. Charbel Fares

§ State table – a multiple variable table with the

GEL 314 - Lecture 2 Prof. Charbel Fares

Example 1: State Table

r e Next State Output

§ 2-dimensional table that matches well to a K-map.

§ The sequential circuit function can be

GEL 314 - Lecture 2 Prof. Charbel Fares

x=0/y=0 x=0/y=1 x=1/y=0

§ Two states are equivalent if their response

GEL 314 - Lecture 2 Prof. Charbel Fares

• the output for input

GEL 314 - Lecture 2 Prof. Charbel Fares

§ Examining the new diagram,

§ Sequential Circuits or Sequential

GEL 314 - Lecture 2 Prof. Charbel Fares

Moore and Mealy Example Diagrams

§ Mealy Model State Diagram

Moore and Mealy Example Tables

§ Moore Model state table maps state to

GEL 314 - Lecture 2 Prof. Charbel Fares