8 - Latches and Flip-Flops

VOLKAN KURSUN Bilkent University VOLKAN KURSUN Bilkent University
Outline
Storage Elements
Latches and Basic Latch
Flip-Flops
Gated SR Latch
Gated D Latch
Edge-Triggered D Flip-Flop
VOLKAN KURSUN T Flip-Flop

Some material from McGraw Hill
JK Flip-Flop
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Storage Elements Sequence of States

 In combinational circuits, the value of each  When the inputs change values, the new
output depends solely on the present inputs either leave the circuit in the same
values of signals applied to the inputs state or cause the circuit to change to a
 In sequential circuits, the values of outputs new state
depend not only on the present values of  Over time, a circuit with storage elements
the inputs but also on the past behavior moves through a sequence of states in
of the circuit (past inputs and outputs) response to the changes in the inputs:
 Sequential circuits include storage sequential circuits (state machines)
elements that store the values of logic
signals: the contents of storage elements
represent the state of the circuit
Simple Memory Element
Outline
Storage Elements  Consists of a loop with two inverters (cross-coupled
inverter pair)
Basic Latch  Circuit will maintain its state as long as the power
supply is applied
Gated SR Latch  The circuit has two states (AB = 0b01 or AB = 0b10)
 The simple memory element does not provide the
Gated D Latch means to control these two states: circuit needs to
be expanded to provide the capability to change
Edge-Triggered D Flip-Flop state
A B
T Flip-Flop
JK Flip-Flop
Basic Latch Basic Latch

 A memory element built with two NOR gates: inputs  When Set and Reset are both 0, the latch
Set and Reset provide the means to change state maintains its state
Reset Reset
0
Set Qa Set Qa
0
Qb QQab’
R S R Qa Qb R S R Qa Qb
Qa Qa
0 0 0/1 1/0 0 0 0/1 1/0

(no
0 1 0 1 0 1 0 1
Qb Qb
change
1 0 1 0 1 0 1 0
S S
of state)
A more common way to draw the basic latch 1 1 0 0 A more common way to draw the basic latch 1 1 0 0
Basic Latch Basic Latch
 When Set = 0 and Reset = 1, the latch is reset (Qa  When Set = 1 and Reset = 0, the latch is set (Qa =
= 0) 1)
Reset Reset
1 0
0 1
Set Qa Set Qa
0 1
Qb Q=b 1 Qb Q=b 0
R S R Qa Qb R S R Qa Qb
Qa Qa
0 0 0/1 1/0 0 0 0/1 1/0

0 1 0 1 Reset 0 1 0 1
S
Qb 1 0 1 0 S
Qb 1 0 1 0 Set
A more common way to draw the basic latch 1 1 0 0 A more common way to draw the basic latch 1 1 0 0
Basic Latch
Basic Latch Oscillation and Uncertainty
 After Set and Reset are both 1 and both outputs are
 When Set and Reset are both 1, both outputs are
zero: Qa = Qb = 0, what if both Set and Reset
zero: Qa = Qb = 0
transition to 0 at the same time?
Reset
1 Reset 0→1→0
1→0
0 →1…
Set Qa Set Qa
1 1→0
Qb Q=b 0 Qbb
Q Qa and
Qb
0→1→0→1… oscillate
S R Qa Qb
R
Qa R
S R Qa Qb between
Qa
0 0 0/1 1/0 Q a = Qb
Both 0 0 0/1 1/0
0 1 0 1 = 1 and
0 1 0 1
Qb 1 0 1 0 outputs Q a = Qb
S Qb 1 0 1 0
A more common way to draw the basic latch 1 1 0 0 are 0 S =0
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Basic Latch Timing Diagram
Basic Latch Oscillation and Uncertainty
 Qa and Qb oscillate between Qa = Qb = 1 and Qa = Qb = R S R Qa Qb
Qa
0 0 0 0/1 1/0 (no change)
0 1 0 1 Qa and Qb
 If the delays through the two NOR gates are identical, 1 0 1 0 oscillate between
the oscillation will continue indefinitely Qb 1 1 0 0
Qa = Qb = 1 and
S Q a = Qb = 0
 In a real circuit, the delays of the two NOR gates will be t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10
different and the latch will eventually settle down to one 1
of its two stable states: however, the final state would R
0
be unknown (uncertain)
Reset 0→1→0 1
1→0
S
0
→1… 1
Set Qa Qa ?
1→0 0
Qbb
Q Qb
1
?
0→1→0→1… 0
Time
Gated SR Latch
Outline
Storage Elements  In the basic SR latch, the state changes occur
anytime that the set and reset inputs change
Basic Latch  Add an enable signal that would allow controlling
when the latch would respond to the changes in its
Gated SR Latch set and reset inputs: when disabled, the changes in
the set and reset signals would be ignored by the
Gated D Latch latch and the existing state would be maintained
Rint
T Flip-Flop
JK Flip-Flop Sint
Gated SR Latch Gated SR Latch: Level-Sensitive
 When clk = 0, the latch is disabled: the changes in  When clk = 1, the latch is enabled: Rint = R and Sint =
the set and reset signals would be ignored by the S and the latch behaves like the basic SR latch
latch and the existing state would be maintained  If S = R = 0, the latch maintains its state
Rint 0 0
Rint 0
(no
change (no
0 of 1
change
state) of
state)
Sint 0 0 Sint 0
Gated SR Latch: Level-Sensitive Gated SR Latch: Level-Sensitive

 When clk = 1, the latch is enabled: Rint = R and Sint =  When clk = 1, the latch is enabled: Rint = R and Sint =
S and the latch behaves like the basic SR latch S and the latch behaves like the basic SR latch
 If S = 0 and R = 1, the latch is reset  If S = 1 and R = 0, the latch is set
1
Rint 1 0
Rint 0
0 1
1 1
reset
1 0 set
0 Sint 0 1 Sint 1
Gated SR Latch: Level-Sensitive
SR Latch Oscillation and Uncertainty
 When clk = 1, the latch is enabled: Rint = R and Sint =  If S = R = 1, Q = Q’ = 0. If S and R transition from 1 to 0
at the same time, Q and Q’ oscillate between Q = Q’ = 0
S and the latch behaves like the basic SR latch
and Q = Q’ = 1
 If S = 1 and R = 1, both outputs are 0 1→0
Rint 0→1→0
1
Rint 1 →1…
0 1→0
1 1
Undefined Undefined
if both R if both R
and S and S
0 transition to transition to
1→0 0→1→0
1 Sint 1
0 afterwards 1→0
Sint →1…
0 afterwards

SR Latch Oscillation and Uncertainty SR Latch Oscillation and Uncertainty
 Q and Q’ oscillate between Q = Q’ = 1 and Q = Q’ = 0  Similarly, if Clk transitions from 1 to 0 while S = R = 1,
 If the delays through the two NOR gates are identical, Q and Q’ oscillate between Q = Q’ = 0 and Q = Q’ = 1
the oscillation will continue indefinitely
 In a real circuit, the delays of the two NOR gates will be 1 Rint 0→1→0
different and the latch will eventually settle down to one →1…
of its two stable states: however, the final state would
1→0
be unknown (uncertain)
1→0 1→0 0→1→0 1→0
→1…
Rint
Undefined Undefined
1 if both R if Clk
and S transitions
transition to to 0 while S
0 afterwards 1→0 0→1→0 =R=1
1→0
1→0 0→1→0 1 →1…
Sint Sint
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SR Latch Timing Diagram Gated SR Latch with NAND
Rint  S and R assignments have been reversed as

compared to the AND-NOR implementation
When Clk
transitions from
S
1 to 0 while S = R
= 1, Q and Q’
oscillate between
Q
Q = Q’ = 1 and Q
Sint = Q’ = 0
Clk
Q
R
Gated D Latch
Outline
Storage Elements  Stores the value of single data input (bit storage)
 Data is stored under the control of a clock signal:
Basic Latch level-sensitive

 Unlike an SR latch with separate Set and Reset
Gated SR Latch inputs, there is only one data input in a D latch: S = D,
R = D’
Gated D Latch  Clk = 1 and D = 1: S = 1, R = 0, set the latch, Q = 1
 Clk = 1 and D = 0: S = 0, R = 1, reset the latch, Q = 0
T Flip-Flop
JK Flip-Flop
Gated D Latch Gated D Latch Operation
 Since S = D and R = D’, the troublesome situation where  As long as Clk = 1, the Q output follows the D input
S = R = 1 cannot occur in a D latch: no output  When Clk = 0, the Q output cannot change: maintains
uncertainty in a D latch state
 The output Q tracks the input D as long as Clk = 1 (latch
is transparent when Clk = 1): level-sensitive behavior
 D latch stores the value of D shortly before the Clk
transitions from 1 to 0
 When Clk = 0, the latch is opaque and maintains state
Gated D Latch Timing Diagram

Positive Latch Timing Definitions

 As long as Clk = 1, the Q output follows the D input  Positive latch
 Transparent when the clock is positive: Stores the value of D input that is
 When Clk = 0, the Q output cannot change: maintains
present before the Clk 1 to 0 transition
state  Opaque when the clock is negative
 Set-up time
 Valid data must arrive by set-up time before the negative edge of the
clock (before the latch becomes opaque – end of the sampling period)
 Hold-time
 Valid data must stay until hold time after the negative edge of the clock
Positive latch
CLK
t
tsetup thold D Q
D DATA CLK
STABLE t
td to q
Q OUTPUT
STABLE t
Gated D Latch VHDL
Negative Latch Timing Definitions

 Negative latch LIBRARY ieee ;
 Transparent when the clock is negative
USE ieee.std_logic_1164.all ;
 Samples the input
 Opaque when the clock is positive ENTITY latch IS
 Set-up time PORT ( D, Clk : IN STD_LOGIC ;
 Valid data must arrive by set-up time before the positive edge of the Q : OUT STD_LOGIC) ;
clock (before the latch becomes opaque - end of the sampling period) END latch ;
 Hold-time
 Valid data must stay until hold time after the positive edge of the clock ARCHITECTURE Behavior OF latch IS
Negative latch BEGIN The code does not specify what
CLK
t PROCESS ( D, Clk ) Q should be assigned when the
D Q
tsetup thold
BEGIN
condition for the if statement is
D DATA IF Clk = '1' THEN
STABLE t
CLK
Q <= D ; not satisfied: implies that the Q
t d to q
END IF ; should maintain its value.
Q OUTPUT END PROCESS ; IMPLIED MEMORY
STABLE t
END Behavior ;
Edge-Sensitive Data Storage

Outline
Storage Elements  Level-sensitive behavior: the state of the latch changes
according to the values of the input signals during the
Basic Latch period when the clock signal is high
 The output state may change multiple times during the
Gated SR Latch high phase of the clock signal in a level sensitive latch
 Edge-sensitive behavior: the state of a storage element
Gated D Latch cannot change more than once in a clock cycle
 Positive edge triggered flip-flop: the data is sampled
Edge-Triggered D Flip-Flop and the output state may change only with the positive
edges of the clock
T Flip-Flop  Negative edge triggered flip-flop: the data is sampled
and the output state may change only with the negative
JK Flip-Flop edges of the clock
Master-Slave D Flip-Flop Master-Slave D Flip-Flop
 Consists of two gated (level sensitive) D  When Clock = 1: the master stage tracks the value of
latches: master and slave the D input while the slave stage does not change
 When Clock transitions from 1 to 0: master stage stops
 Master stage: changes its state while Clock = 1
following the changes in the D input while the slave
 Slave stage: changes it state while Clock = 0 stage stores the value of the signal Qm
M S  Since Qm does not change while Clock = 0, the slave
Qm stage can undergo only one change of state (output
D D Q D Q Q switching) during a clock cycle: the slave stage changes
state only at the negative edge of the clock signal
Clock Clk Q Clk Q Q  Regardless of the number of changes in the D input to
the master stage during one clock cycle, there may be
only one change at the Q output that corresponds to
the D input stored at the negative edge of the clock
signal: negative edge triggered
Master-Slave D Flip-Flop
Edge-Triggered versus Level-Sensitive

M S
Qm
Clock D D Q Qa
D D Q D Q Q D Q Level-sensitive
D latch
Clock Clk Q Clk Q Q

Clock Clk Q Qa
Q
D
Bubble indicates negative-
edge-triggered D Q Qb
Positive edge--
Clock Qa triggered D flip-

flop
Q Qb
D
Qb
Qm D Q Qc
Negative edge-
triggered D flip-
flop
Q Qc Q Qc
D Flip-Flop Timing
Edge-Triggered D: Alternative Design

 Clock-to-Q propagation delay: tcQ  Master-Slave D: requires 2*4*2-input NAND gates and
3 inverters
 Setup time: D signal must be stable by at least the
setup time before the Clk transitions from 0 to 1  Alternative design (positive edge triggered): with only
5*2-input NAND gates and 1*3-input NAND gate
 Hold time: D signal must remain stable by at least 1 P3
the hold time after the Clk 0 to 1 transition
P1
2
5 Q
Clock
P2 6 Q
3
D Q
4 P4 Clock
Q
D
Edge-Triggered D: Alternative Design Edge-Triggered D: Alternative Design

 When Clock = 0: the flip-flop maintains its state  When Clock transitions from 0 to 1: the data is stored
(no D
1 P3
D’ 1 P3
change (Data is
1 P1
of state) 1→D’
P1
stored)
2 2
5 Q 5 Q
0→1 D
Clock
0 Clock
P2 6 Q P2 6 D’ Q
3 3
1 1→D
4 P4 4 P4
D
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D
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 Setup time: P3 MUST be stable when the positive clock  Hold time: Once D is transferred onto the P2 node and P2 is stable,
edge arrives which requires the input D to be stable by the changes in the D input no longer matter. Since P1 is already 1
even before the positive edge of the clock arrives, the transfer of D
at least the setup time before the positive clock edge, onto P2 starts immediately with the positive edge of the clock:
setup time = DelayNAND4 + DelayNAND1
Hold time = DelayNAND3
D P3 must be
(Data is D (Data is
D’ 1 P3 stable when
the positive D’ 1 P3
clock edge
arrives
stored) stored)
2
1→D’
P1
5
D Q
2
1→D’
P1
5
D Q
0→1
Clock
0→1
Clock
3
P2 6
D’ Q
3
P2 6
D’ Q
D must be stable by at least

1→D D must remain stable by at
1→D D must remain stable after the
the setup time before the least the hold time after the positive clock edge and until D
positive clock edge arrives positive clock edge arrives is transferred onto P2. Once D
4 P4 4 P4 is transferred onto P2, changes
D
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D
EEE 102 Introduction to Digital Circuit Design D’ in D do not matter. VOLKAN KURSUN

 Hold time scenario-1: Assume D is 0 when the positive  Hold time scenario-2: Assume D is 1 when the positive clock
clock edge arrives. Once D (0) is transferred onto P2, P2 edge arrives. When the positive clock edge arrives, D is already
will keep P4 at 1 regardless of the subsequent changes transferred onto P3. Once the clock transitions from 0 to 1, D’
(0) is transferred onto P1 and P1 keeps P2 and P3 stable at 1
in the D input: Hold time = DelayNAND3
regardless of the subsequent changes in the D input and P4.
0 (Output latch is
0→1 1 (Output latch is
1 1 P3
RESET: Data is
1 P3
SET: Data is
stored) stored)
1 1→0
2
P1
5
0 Q
2
P1
5
1 Q
0→1
Clock
0→1
Clock
3
P2 6
1 Q
3
P2 6
0 Q
1→0 D must remain stable after the

positive clock edge and until D
1 D must remain stable after the
positive clock edge and until D
0→1 4 P4
is transferred onto P2. Once D
is transferred onto P2, changes 1→0 4 P4
is transferred onto P2. Once D
is transferred onto P2, changes
D
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Edge-Triggered D VHDL Edge-Triggered D VHDL Code -2
LIBRARY ieee ; LIBRARY ieee;

USE ieee.std_logic_1164.all ; USE ieee.std_logic_1164.all;
ENTITY flipflop IS ENTITY flipflop IS

PORT ( D, Clock : IN STD_LOGIC ; PORT ( D, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC) ; Q : OUT STD_LOGIC ) ;
END flipflop ; Sensitivity list contains only the END flipflop ;
clock signal because clock is the
ARCHITECTURE Behavior OF flipflop IS only signal that can trigger an
ARCHITECTURE Behavior OF flipflop IS
BEGIN
output change
BEGIN Sensitivity list is omitted
PROCESS ( Clock ) ‘EVENT attribute refers to any change in the clock PROCESS WAIT UNTIL construct implies that the sensitivity
BEGIN signal list includes only the Clock signal
BEGIN
IF Clock'EVENT AND Clock = '1' THEN WAIT UNTIL Clock'EVENT AND Clock = '1' ;
Q <= D ; Q <= D ;
END IF ; If Clock‘EVENT AND Clock = ‘1’ checks if the clock has END PROCESS ; WAIT UNTIL Clock‘EVENT AND Clock = ‘1’ to make an
END PROCESS ; changed and if it has a value of 1 after the change: END Behavior ; assignment to the Q output: indicates a positive clock
END Behavior ; indicates a positive clock edge edge
D Flip-Flop with Clear and Preset D Flip-Flop with Clear and Preset
 Typically, it is necessary to be able to initialize sequential  Preset_n = 0, Clear_n = 1: Preset the Q output to 1
circuits to a specific state Preset_n Clear_n Q Q’  Asynchronous preset: Preset_n signal is used to preset the
0 1 1 0 flip-flop regardless of the clock signal
 Clear = 0: Clear the Q output to 0
 Preset = 0: Set the Q output to 1
1
1
0
1
0
Normal op.
1
0
 Example: master-slave flip-flop based on NAND gates
with active-low asynchronous clear and preset 1 1
0
1 0 1 0
1
 Preset_n = 0, Clear_n = 1: Preset the Q output to 1  Clear_n = 0, Preset_n = 1: Clear the Q output to 0
 Asynchronous preset: Preset_n signal is used to preset the  Asynchronous clear: Clear_n signal is used to clear the flip-
flip-flop regardless of the clock signal flop regardless of the clock signal
0 1
1 1 1 0 1 0
1 0
0 1 0 1
D
D’ 1
0
1 0 0
 Clear_n = 0, Preset_n = 1: Clear the Q output to 0  Clear_n = 1, Preset_n = 1: clear and preset signals have no
 Asynchronous clear: Clear_n signal is used to clear the flip- effect on the circuit operation, normal negative edge-
flop regardless of the clock signal triggered master-slave flip-flop operation
1 1
D 1 1 1
D’ 0
1 0
1 1
D’ 0 1
0 0 1 1
Alternative D Flip-Flop with Clear and Preset Alternative D Flip-Flop with Clear and Preset
 Preset_n = 0, Clear_n = 1: Preset the Q output to 1  Preset_n = 0, Clear_n = 1: Preset the Q output to 1
 Asynchronous preset: Preset_n signal is used to preset the  Asynchronous preset: Preset_n signal is used to preset the
flip-flop regardless of the clock signal flip-flop regardless of the clock signal
0 0
1 1
0 1 1 0 0 1
0 1
1 0 1
0 0
1 1
Alternative D Flip-Flop with Clear and Preset Alternative D Flip-Flop with Clear and Preset
 Clear_n = 0, Preset_n = 1: Clear the Q output to 0  Clear_n = 0, Preset_n = 1: Clear the Q output to 0
 Asynchronous clear: Clear_n signal is used to clear the flip-  Asynchronous clear: Clear_n signal is used to clear the flip-
flop regardless of the clock signal flop regardless of the clock signal
1 1
1 1 0 1 1 0
0 0 1 0
1 1
0 0 0 0
D Flip-Flop with Synchronous Clear D Flip-Flop with Synchronous Clear

 Clear_n = 0: Clear the Q output to 0 when  When Clear_n = 1, the flip-flop operates normally
the positive edge of the clock signal arrives 1
0
D D
0 0
1 D’
Synchronous Clear and Preset Synchronous Clear and Preset

 When Clear_n = 1, Preset_n = 1, the flip-flop operates  When Clear_n = 0, Preset_n = 1, the flip-flop is cleared
normally with the positive edge of the clock (synchronous clear)
0 1 Clear_n’
1 0
Clear_n’
D’ Preset_n 1
Preset_n
1 D D 1 D 0 Q
0
Q D
1
D
Clear_n Clear_n
1
Clock
1
Clock
Preset_n’ Q Preset_n’ Q
0 0
 When Clear_n = 0, Preset_n = 0, the flip-flop operates  When Clear_n = 1, Preset_n = 0, the flip-flop is set with
normally the positive edge of the clock (synchronous preset)
Clear_n’
1 1 0 1
Preset_n D’ Clear_n’
D’
0 D D Preset_n
0 D 1
0
D Q Q
1
D
Clear_n Clear_n
1
Clock
0
Clock
Preset_n’ Q
Preset_n’ Q
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Asynchronous Reset VHDL Asynchronous Preset and Clear VHDL

LIBRARY ieee ;
ENTITY flipflop IS
PORT ( D, Resetn, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC) ;
END flipflop ;
Whenever the process is
triggered, check Resetn
BEGIN
PROCESS ( Resetn, Clock ) first (without checking the
BEGIN clock signal):
IF Resetn = '0' THEN asynchronous reset
Q <= '0' ;
ELSIF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
Synchronous Reset VHDL Synchronous Reset VHDL Code-2

LIBRARY ieee ;
ENTITY flipflop IS
PORT ( D, Resetn, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC) ;
END flipflop ;

BEGIN
PROCESS ( Clock ) IS RISING_EDGE(Clock)
BEGIN
IF RISING_EDGE ( Clock ) THEN
IF Resetn = '0‘ THEN
Q <= '0' ;
ELSE
Q <= D ;
WAIT UNTIL positive clock edge
END IF ;
before checking the Resetn signal END IF ;
and clearing the output if Resetn = END PROCESS ;
0: asynchronous reset END Behavior ;
Toggle (T) Flip-Flop
Outline
Storage Elements  The input signal D is equal to either Q or Q’ depending
on the control signal labeled T
Basic Latch  If T = 0, D = Q and the flip-flop will maintain its state
 If T = 1, D = Q’ and the flip-flop will toggle its state
Gated SR Latch T Q t + 1 
= T′Q + TQ
Gated D Latch D=T
0 Q t 
Edge-Triggered D Flip-Flop D Q Q 1 Q t 
T
T Flip-Flop Q Q T Q
JK Flip-Flop Clock Q

Toggle (T) Flip-Flop Toggle (T) Flip-Flop

 If T = 0, D = Q and the flip-flop will maintain its state  If t = 1, D = Q’ and the flip-flop will toggle state
Q(t) D=T D=T

1 0 0
Q(t) Q(t)’
D Q Q D Q Q
0 1
T 0 Q Q
T Q(t)’ Q Q
Clock Clock
Toggle (T) Flip-Flop Timing
Outline
T Q t + 1  Storage Elements
D=T 0 Q t  Basic Latch
D Q Q 1 Q t 
T
Q Q T Q
Gated SR Latch
Clock Q Gated D Latch
1 2 3 4
Clock Edge-Triggered D Flip-Flop
T T Flip-Flop
Q
JK Flip-Flop
JK Flip-Flop JK Flip-Flop
 Behaves as an SR flip-flop where J = S and K = R for all  When J = K = 0, JK flip-flop maintains state
input values except J = K = 1
 When J = K = 1, JK flip-flop toggles like a T flip-flop
0 0
J
Q(t) D Q
J Q
D Q Q
K 0 1
K Q Q
Q(t) Q Q
Clock Clock Q(t)

J K Q  t + 1 J K Q  t + 1
J Q J Q
0 0 Q t 0 0 Q t
0 1 0 0 1 0
1 0 1 1 0 1
1 1 Q t 
K Q 1 1 Q t 
K Q
JK Flip-Flop JK Flip-Flop
 When JK = 0b01, JK flip-flop clears the output  When JK = 0b10, JK flip-flop sets the output
0 0 1 Q(t)’
J J
0 D Q 0 Q
1 D Q Q(t)→1
Q
K 1 0 K 0 1
0 Q Q Q(t) Q Q
Clock Clock Q(t)

J K Q  t + 1 J K Q  t + 1
J Q J Q
0 0 Q t 0 0 Q t
0 1 0 0 1 0
1 0 1 1 0 1
1 1 Q t 
K Q 1 1 Q t 
K Q
JK Flip-Flop JK Flip-Flop VHDL

 When JK = 0b11, JK flip-flop toggles output

Describes the D flip-flop
1 Q(t)’ Q(t)→
Describes the
combinational
J circuit that
Q(t)’ D Q
Q(t)’ produces the
D input of the
Q D flip-flop
K 1 0 Q
0 Q
Clock
J K Q  t + 1 J K Q  t + 1
J Q J Q
0 0 Q t 0 0 Q t
0 1 0 0 1 0
1 0 1 1 0 1
1 1 Q t 
K Q 1 1 Q t 
K Q
JK Flip-Flop
VOLKAN KURSUN Bilkent University
 If J and K are tied together, a JK flip-flop turns

into a T flip-flop
J
D Q Q
K Q Q
Clock
J K Q  t + 1
J Q
0 0 Q t
0 1 0
1 0 1
1 1 Q t 
K Q
EEE 102 Introduction to Digital Circuit Design VOLKAN KURSUN

8 - Latches and Flip-Flops

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8 - Latches and Flip-Flops

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VOLKAN KURSUN Bilkent University VOLKAN KURSUN Bilkent University

Latches and Basic Latch

VOLKAN KURSUN T Flip-Flop

Storage Elements Sequence of States

Basic Latch Basic Latch

0 0 0/1 1/0 0 0 0/1 1/0

0 0 0/1 1/0 0 0 0/1 1/0

Gated SR Latch: Level-Sensitive Gated SR Latch: Level-Sensitive

VOLKAN KURSUN Bilkent University VOLKAN KURSUN Bilkent University

Rint  S and R assignments have been reversed as

Basic Latch level-sensitive

Gated D Latch Timing Diagram

Positive Latch Timing Definitions

Negative Latch Timing Definitions

Edge-Sensitive Data Storage

Edge-Triggered versus Level-Sensitive

Clock Clk Q Clk Q Q

Clock Qa triggered D flip-

Edge-Triggered D: Alternative Design

VOLKAN KURSUN Bilkent University VOLKAN KURSUN Bilkent University

Edge-Triggered D: Alternative Design Edge-Triggered D: Alternative Design

Edge-Triggered D: Alternative Design Edge-Triggered D: Alternative Design

D must be stable by at least

VOLKAN KURSUN Bilkent University VOLKAN KURSUN Bilkent University

Edge-Triggered D: Alternative Design Edge-Triggered D: Alternative Design

1→0 D must remain stable after the

LIBRARY ieee ; LIBRARY ieee;

ENTITY flipflop IS ENTITY flipflop IS

VOLKAN KURSUN Bilkent University VOLKAN KURSUN Bilkent University

VOLKAN KURSUN Bilkent University VOLKAN KURSUN Bilkent University

VOLKAN KURSUN Bilkent University VOLKAN KURSUN Bilkent University

D Flip-Flop with Synchronous Clear D Flip-Flop with Synchronous Clear

VOLKAN KURSUN Bilkent University VOLKAN KURSUN Bilkent University

Synchronous Clear and Preset Synchronous Clear and Preset

Asynchronous Reset VHDL Asynchronous Preset and Clear VHDL

VOLKAN KURSUN Bilkent University VOLKAN KURSUN Bilkent University

Synchronous Reset VHDL Synchronous Reset VHDL Code-2

ARCHITECTURE Behavior OF flipflop IS

JK Flip-Flop Clock Q

Toggle (T) Flip-Flop Toggle (T) Flip-Flop

Q(t) D=T D=T

Clock Clock Q(t)

Clock Clock Q(t)

JK Flip-Flop JK Flip-Flop VHDL

 When JK = 0b11, JK flip-flop toggles output

 If J and K are tied together, a JK flip-flop turns

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