Timing sign-off with Pri

meTime
Speaker: Bob Tsai
Advisor: Jie-Hong Roland Jiang
Outline
 Introduction
 Flow
 On Chip Variation (OCV)
 Manual/automated netlist editing
 Signal integrity and crosstalk
Introduction
 PrimeTime VX, PrimeTime SI

 Sign-off
◦ A collective name to a series of verification steps

 Standard Parasitic Exchange Format

◦ Represent parasitic data of wires in a chip in ASCII f
ormat
◦ Used for delay calculation and ensuring the signal i
ntegrity
Flow
Setup Design

Create CHIP constraints Update

Check setup RTL
Validate Prelayout
Constraints
Update
CHIP level STA
SDC
Timing fail
error?
Validate Constraints
Hand-off pass
Update
P&R
SDC
Validate Postlayout
Constraints

Timing
fail
error?

pass
Tape-out
On Chip Variation
 Models the small difference in operating para
meters across the chip

 Setup check: max delay for data path and min

delay for clock path

 Hold check: min delay for data path and max

delay for clock path
Setup Time Checking
  Clock path 1 + data path max – clock path 2 + setup clock period
max = 3.04/3.8

D Q logic D Q
0.48/0.6
min = 1.6/2.0
CT3

0.64/0.8
0.52/0.65 setup = 0.2
CLK CT1 CT2

Clock path 1 = 0.8+0.6 =1.4

Data path max = 3.8
Clock path 2 = 0.64+0.52=1.16
Setup = 0.2
=> The clock period must be at least 1.4+3.8-1.16+0.2=4.24
Hold Time Checking
  Clock path 1 + data path min – clock path 2 - hold 0
max = 3.04/3.8

D Q logic D Q
0.48/0.6
min = 1.6/2.0
CT3

0.64/0.8
0.52/0.65 hold = 0.1
CLK CT1 CT2

  Clock path 1 = 0.64+0.48 =1.12

Data path min = 1.6
Clock path 2 = 0.8+0.65=1.45
Hold = 0.1
=> No hold violation exists because 1.12+1.6-1.45-0.1=1.17 0
Functions for check and analysis
Commands Main functions
set_wire_load_model (before P&R)
read_sdf (after P&R)
read_parasitics (after P&R)
check_timing Checks for constraint problem such as
undefined clocking, input data arrival times,
and output data required times. (must-do)
report_design Lists the attributes of the design, including
the chosen operating conditions, wire load
information, and design rules.
report_clock Generates a report on the clocks defined for
the design, showing for each clock the
name, period, rise and fall times, and timing
characteristics such as latency and
Manual Netlist Editing
 size_cell

 insert_buffer | remove_buffer

 swap_cell

 Use write_change to output the changes

Automated Netlist Editing
 The design should be fully placed and routed,
including clock trees, but without corefiller
 fix_eco_timing –type {setup | hold}
 fix_drc_timing –type {max_transition | max_c

apacitance | max_fanout} –method {size_cell |

insert_buffer}

pt_shell> fix_drc_timing –type max_transition –method {size_cell} -verbose

pt_shell> fix_drc_timing –type max_transition –method {insert_buffer}

-buffer_list {BUFX1 BUFX2 BUFX3} -verbose
Signal Integrity and Crosstalk
 Signal integrity
◦ The ability of an electrical signal to carry informatio
n reliably and resist the effects of high-frequency el
ectromagnetic interference from nearby signals

 Crosstalk
◦ The undesirable electrical interaction between two
or more physically adjacent net due to capacitive cr
oss-coupling
Noise analysis flow
 Enable crosstalk analysis
set si_enable_analysis TRUE

 Read coupled parasitic data

read_parasitics -format spef -keep_capacitive_coupling [spef_filename]

 Do coupled delay analysis

update_timing

 Noise analysis
update_noise

 Generate noise report

report_noise
Thanks for your attention
Clock Setup
D Q logic D Q

CLK1 0 CLK3 0

CLK2 1 CLK4 1

SEL

set_false_path set_clock_group
set_false_path –from CLK1 –to CLK2 set_clock_groups \
set_false_path –from CLK2 –to CLK1 -logically_exclusive –name E1 \
set_false_path –from CLK3 –to CLK4 -group {CLK1 CLK3}
set_false_path –from CLK4 –to CLK3 -group {CLK2 CLK4}
set_false_path –from CLK1 –to CLK4 set_active_clock [all_clocks]
set_false_path –from CLK4 –to CLK1
set_false_path –from CLK2 –to CLK3
set_false_path –from CLK3 –to CLK2