Signal and Design Integrity

April 2002

Cadence Design Systems, Inc.

 Technical issues in Deep Sub-Micron Design
 Manufacturability (Chip can’t be built)
– Antenna rules
– Minimum area rules for stacked vias
– CMP (Chemical Mechanical Polishing) area fill rules
 Signal Integrity (failure to meet Performance targets)
– Crosstalk induced errors
– Timing dependence on crosstalk
– IR Drop on power supplies
– Substrate coupled noise
 Design Integrity (reliability failures in the field)
confidential

– Electromigration on power supplies

– Hot electron effects on devices
– Wire self heat effects on clocks and signals
2
 Why now?
 These effects have always existed, but become worse at deep sub-micron sizes
because of:
– Finer geometries
– Greater wire and via resistance
– Higher electric fields (if supply voltage not scaled)
– More metal layers
– Higher ratio of cross coupling to grounded capacitance
– Lower supply voltages
– More current for a given power
– Lower device thresholds
confidential

– Smaller noise margins

 Good news: Same solutions that work at 150 nm and 130 nm will work for next few
technology generations until << 100 nm
3
 Crosstalk induced errors
 Transition on an adjoining signal causes unintended logic
transition
 Symptom - chip fails (repeatably) on certain logic operations

Aggressor net

Coupling C
Victim net

Wire R
confidential

Drive R Grounded C Input Noise Tolerance

4
 Timing Dependence on Crosstalk
 Timing depends on behavior of adjoining signals
 Symptom - Timing predictions inaccurate compared to silicon.
Effect can be large: 3:1 on individual nets.

Delay here and here depends on the behavior of other nets

Wire R
confidential

Grounded C Coupling C (multiplied by Miller effect)

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Other logic net(s)
 Effect of Crosstalk on Delay
Thresholds
min nom max
1.20E+00

1.00E+00

8.00E-01 Series1
Series2
6.00E-01 nominal Series3
Voltage (v)

4.00E-01 Series4
Series5
2.00E-01
friendly Series6
confidential

0.00E+00 Series7
1

10

28

37
13

16

19

22

25

31

34

40

43

46

49

52

55

58

61
-2.00E-01
unfriendly
6 -4.00E-01
Time (ps)
 Electromigration
 Power supply lines fail due to excessive current
 Symptom: Chip eventually fails in the field when the wire
breaks Currents depend on driver type,
loads, and how often cell is
switched

Currents depend on currents

of other cells
confidential

Power supply
network consists Pad
of wires of varying
sizes; they must be big Current limit depends on wire size
7 enough, but too big wastes area
 IR Drop
 Voltage drop in supply lines from currents drawn by cells
 Symptom: chip malfunctions on certain vectors
 Biggest problem - what’s the worst case vector?
Currents depend on driver type,
loads, and how often cell is
switched

Voltages depend on currents

of other cells
Allowable
voltage
confidential

drop at pin

Power supply
Pad network consists
8 of wires of varying
sizes; they must be big
enough, but too big wastes area
 Hot Electron Effects
 May also be called short channel effect
 Caused by extremely high electric fields in the channel
– Occurs when voltages are not scaled as fast as dimensions
 Effect becomes worse as devices are turned on harder
 Symptom: Thresholds shift over time until chip fails
Oxide and/or interface
is damaged here
Gate
+++
confidential

+++

N+ diffusion
9
Electrons pick up speed in channel; Impact ionization occurs here
‘hot’ electrons are the fastest of a
statistically fast bunch
 Hot Electron Effect (cont)
Contours of constant
hot electron flux
 Depends on how hard device is driven (input slew rate)
 And on the size of the load

Vgs

Trajectory with large C, fast Tin

confidential

Trajectory with small C, slow Tin

10 Vds
 Wire Self Heat
 May also be called signal wire electromigration
 Wire heats above oxide temperature as pulses go through
 Symptom: Chip eventually fails when wire breaks
 Depends on metal composition, signal frequency, wire sizes,
slew rates, and amount of capacitance driven
 Requires different data/formulas from power supply EM
confidential

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Oxide Metal
 Substrate Noise
 Currents injected by high speed switching of digital devices
 Supply currents injected via substrate contacts

Package
confidential

12
 Analog Noise in Custom Digital ICs
Crosstalk

Supply Noise
Vdd1 Propagated Vdd2
Overshoot Noise
CLK (TDDB)

Undershoot
Charge
confidential

“0” (TDDB)
Sharing Gnd2
Leakage
13 Supply Noise
Gnd1
 What can tools do about these problems?
 Accurate Analysis
– Make sure real problems are caught
– Avoid fixing problems that aren’t really there
– For analog issues, such as substrate noise, this is about all we can
do. The user must decide how to fix the problem
 Tools can try to prevent or avoid errors
 Tools can try to fix errors once they have been found
 Can view two ways
confidential

– For a given problem (ie. crosstalk) what can each tool do?
14 – For a given tool (ie. synthesis), which problems can be alleviated?
– Following slides have a mixture of these analyses.
 Signal Integrity Flow- Full Chip Design
Floor Place & Chip
All Tools Verification
Planning Route Assembly

Design global Build Do global Re-verify Re-verify

wiring Blocks routing Sign-off
-Signal nets -Place blocks -implement -Re-extract -Re-extract
correct by -Place cells with wiring routing routing
construction Optimization strategy parasitics parasitics

-Push budgets - Re-check -Route with -Re-check - Re-check

into blocks loads, drives, variable width, loads, drives, loads, drives,
timing spacing, timing timing
shielding
confidential

 Signal Integrity Correction and Checking:

– Early and Often throughout the design flow
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– Fewer Signal Integrity issues at the end of the design flow
 Signal Integrity Flow- Block Design
 Signal Integrity issues fixed at each step in the Design Flow:
•Crosstalk
•Automatic Prevention •Shielded
Repeater Routing
•Signal •Crosstalk
Insertion Self Heat •Wire/Clk
•Clk Self Heat Delay
•Signal Hot Self Heat •
•Power: Power: •Post-Route
Electron
-PGP •Clk Hot EM & •Crosstalk Crosstalk
-EM •Power
Electron IR Drop Parasitics Fixing
-IR Drop Driven

Logical Floor Placement & Clock Parasitic Timing

Routing Delay
Simulation Planning Optimization Tree Extraction
confidential

Calc

New
Library
16 Data
 Controlling crosstalk
 Use timing windows
 Use a sensitivity-based noise check to minimize false failures
 Need fast analysis with SPICE-like distributed models
– Based on reduced order models
 Automatically fix functional noise failures via ECOs to P&R
 Support mixed flat and hierarchical analysis
 Special commands for fixing post-route crosstalk
confidential

– Needed for good flow convergence

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 Timing Windows for Crosstalk
 Only consider signals that can change at the same
time
 Data comes from static timing analysis

One clock cycle

B D STA
A Timing
C
Windows
confidential

Crosstalk
Magnitudes
18

Worst case occurs here, does not include signals A or D.

 Glitch Rejection
 Calculates the sensitivity of each receiver to noise at its input
 Accounts for the inherent glitch rejection of each receiver
 Depends on input waveform, input circuitry, and output load

Noise sensitivity IN
is dependent on
input waveform 0UT
confidential

shape and  vout

output loading  vin
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 DC Noise Peak Vs Noise Immunity

14%
12% % Nets with
12% Noise >30%
10% Vdd
8% 7%
6% % Nets with
4% Sensitivity
2% 0.25% 1.80% Failures
0.14%
0% 0.01%
CktA (0.25u) CktB (0.18u) CktC (0.15u)
confidential

 Using Sensitivity analysis (such as CeltIC) implies less rework!

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 Crosstalk Analysis – Accuracy Measurement
 Can reduced order models give accurate results?
 Worked through this with customers – it’s very difficult
 To determine error budget, need to understand each portion
separately
 Need to get LEF, TLF, and SPICE to exactly agree
– Need to run, and measure, SPICE simulations
– Slopes, normally a second order effect, are first order for crosstalk
confidential

checking
 Even SPICE analysis has ambiguities:
21 – Simultaneous Switching (SS) vs. Worst Case Alignment (WCA)
 Simultaneous switching is not worst delay
Thresholds
min nom max
1.20E+00

1.00E+00

8.00E-01 Series1
Series2
6.00E-01 nominal Series3
Voltage (v)

4.00E-01 Series4
Series5
2.00E-01
friendly Series6
confidential

0.00E+00 Series7
1

10

28

37
13

16

19

22

25

31

34

40

43

46

49

52

55

58

61
-2.00E-01
unfriendly
22 -4.00E-01
Time (ps)
 Crosstalk results – lumped vs distributed
 Glitch Noise
– Lumped analysis was about (-10%, +70%) for noise peak.
– CeltIC (distributed analysis) was (-9%, +4%) for noise peak
 Since most signals fail by only a few millivolts, using distributed
analysis results in many fewer reported errors.
confidential

23
 Glitch size with lumped model
Noise Error Rising

80.00

60.00
%Error

40.00
20.00

0.00

-20.00 0 0.2 0.4 0.6 0.8 1 1.2 1.4

XMC Noise (V)

confidential

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 Celtic (distributed) Noise Errors (note scale change)
Error Graph

6.00%

4.00%

2.00%

0.00%
0 0.2 0.4 0.6 0.8 1 1.2 1.4

-2.00%
Error %

Rise Error Graph

Fall Error Graph
-4.00%

-6.00%
confidential

-8.00%

-10.00%

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-12.00%
Celtic [V]
 Better prevention helps flow convergence
 Crosstalk prevention in synthesis
– Upgrade drivers of slow transition signals even if not needed for
timing
– Global slew limits
– Clock tree generator should include EM prevention for clocks
 Crosstalk prevention in routing
– Long parallel line avoidance
– Longer term, track assignment does even better
confidential

– Takes advantage of ‘free’ shielding by power supply grid

 Crosstalk timing prevention in synthesis (forward prediction)
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 Fixing errors after routing

 Fixing crosstalk errors after routing requires care

– Rip-up-and-reroute may change neighbors
– Making victims stronger makes them better aggressors
 Specific post-route heuristics are required for best convergence
– Insert/change components with minimal routing changes
– Change some marginal components preemptively to avoid
confidential

iterations
 These commands are also useful for other post route changes
27 – ECOs
 Strategy for Crosstalk Fixing
 From Post Route Analysis
– Create repair files for Post Route Crosstalk Fixing
– Apply repair file
– Buffer insertion
– Wide Space Routing
– Shielded Routing

Wide Space Routing

confidential

28 Buffer Shielded
Insertion Routing
 Timing Convergence
 Extremely few timing problems from crosstalk glitch fixing (none
in 20-30 large examples at 0.15 and 0.13 micron)
 If flow is timing driven, critical path has strong drivers, short nets
and good slopes -> few crosstalk problems
 Conversely, nets with problems tend to be long nets with weak
drivers, and buffer insertion helps these.
 Wire fixes (extra spacing/shielding) increase performance if
anything
confidential

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 Handling Timing Impact of Crosstalk
 Correct treatment of coupling has an effect even if there is no
noise!
 Need accurate analysis of effect
– Lumped models have large errors
– Distributed analysis is needed
– Reduced order models give good results
 Would like to avoid the need to iterate around timing windows
confidential

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 Even without noise, coupling is important
What existing timing verifiers see. Real circuit on silicon

Logic 0
Solid 0

victim in victim
in

True timing is about 15% faster

confidential

31
 Crosstalk results – lumped vs distributed
 Analysis of crosstalk induced delay
– Lumped analysis was about (-20%, +450%) on delay
– Spice has simultaneous switching; Lumped analysis used Worst
Case Alignment
– The delay measurement was interconnect delay – not stage delay
– A distributed analysis with reduced order models (CeltIC) was
(-16%, +10%) for delay
confidential

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 Lumped crosstalk delay
Early Rise Error

500.00
400.00
300.00
%Error

200.00
100.00
0.00
-1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2-100.00 0
confidential

XM C De lay (ns )

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 Distributed (CeltIC) Delay Errors Delay Error

15.00%

10.00%

5.00%

0.00% Late Fall Error

Error %

-1 -0.5 0 0.5 1 1.5 2 2.5 3 Late Rise Error

Early Fall Error
-5.00% Early Rise Error

-10.00%
confidential

-15.00%

-20.00%
Celtic [ns]

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 Noise Aware-Timing
 Internal iteration
Start

CeltIC Noise Aware

TW SDF Timer
STA
confidential

End

35
 Noise Aware Timing
 Avoids iteration between tools

Static Timing
Analysis
confidential

Detailed Crosstalk Delay

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Calculation
 Signal Integrity (SI) in Synthesis
 Synthesis with placement can help SI issues
– Crosstalk and EM prevention in placement/sizing
– Interface to detailed crosstalk analysis
– Generate timing windows, constraints, and clocks
– Generate maximum frequency for reliability checks
– Wire self heat and hot electron
– Post routing crosstalk correction
– Add buffers
confidential

– Size drivers
– Decision based on routing and cell congestion
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– Includes post route timing corrections
– Integrated clock tree generation supports EM prevention
 Signal Integrity Avoidance in Synthesis
 Other possible prevention options
– Global slew limit (can limit length as a function of driver size)
– Global length limits (per layer).
– Some customers have requested this for manufacturability, but it
can also be used for SI.
 Better correction options
– Decide bigger driver, inserted buffer, or extra spacing on a net by
net basis after routing.
confidential

38
 Controlling Wire Self Heat (also called Signal
Line Electromigration or Joule Heating)
 Need a maximum frequency for each net
– Timing analysis and/or synthesis can provide this
– Generated by propagating clocks forward to data signals
– Maximum frequency, times load, gives maximum possible current
 Clock nets are a particular concern
– Highest frequency operation, long wires, big loads
– Worst spot on net may not be at driver
– Vias may have tighter limits
confidential

– Specialized clock drivers may only have pins on the high metal
layers, leading to a good initial clock route, but….
39 – Router may change layers during rip-up and re-route
– Nets must be tapered (to reach pins), but only at input pins
  All wiring segments, vias, and cell I/O pins must be checked
 Frequency dependent Cload and/or Slew are calculated and checked.
 EM current density change on a wire path are measured and checked.

OK

4M

No Good
confidential

Buffer
OK
40
Buffer
 Signal Line Electromigration

 New Placement and Routing features

– Router must taper correctly (No taper at driver)
– Analysis must check correctly
– Tapered (input) pins are not checked
– All segments on net are checked
– All vias on the net are checked.
– Layers and vias that are in the routing rule, but not used, are not
confidential

checked.

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 Extract Improvements Needed for SI

 Accuracy for cross coupling

 Capacity
 Coupling capacitance reduction
confidential

42
 Extraction for Cross Coupling
 Fully distributed coupling reflects physical reality
– Files are huge (3GB for 100K instances) -> 300GB for 10M cells
 Need a reduction that reduces network size with an acceptable
degradation of accuracy.
– We believe a good compromise is possible here.
 When combined with delay calculation, can potentially regain
~15% timing margin associated with assuming coupling Cs are
truly grounded.
confidential

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 Intelligent Network Reduction
A very small example

6 shapes
9 inter-shape couplings

SPICE/DSPF require even more components

No native element for distributed RC
12 Rs, 9 Cs for T model,
confidential

6 Rs, 16Cs for Pi model

44
Net result: huge files
 Network Reduction (continued)

 Reduce number of components

 Preserve important properties
confidential

– Preserve moments (Elmore delay and higher order)

 Preserve cross-coupling properties
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 Hot Electron Degradation

 Most customers are designing their libraries such that the CAD
tools don’t need to check this.
 If needed, can be fixed by a combination of timing analysis and
placement, and pre-characterization of cells
– Timing analyzer computes input slope and max frequency
– Placement tool computes output load, then consults pre-
characterized table
confidential

– If load is too high for specified chip lifetime, upsizes driver or

inserts isolation buffer
46
 Power Supply Analysis

 IR drop analysis
– Static (uses average current)
– Dynamic (worst case stimulus)
 Most users use static analysis since worst case vectors are
unknown.
– This is an active research problem
confidential

 Important to do this early in the flow since widening the power

supplies later causes huge routing problems.
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 Power Calculation Flow
Average
Design -LEF, DEF
Power Characterization
Supply Voltages
RSPF parasitics
VCD file or freq +activity Triplet

Power Calc

Vectors PWL
confidential

48

Power Spec File

 Rail Analysis Flow
Design:
LEF, DEF

• Extract Power network

• Calculate IR Drop and EM SEDSM
through wire segments
• Display on physical design Rail
Analysis
Wire Seg File
confidential

Cell Seg File

49
 Rail Analysis
confidential

50
 Power supply analysis improvements
 Improve existing features
– Multi-Vcc -> Map to cell supply voltage
– Peak IR drop – try to make easier to use
 Hierarchical analysis
– Top down, enter estimates for uncompleted blocks
– Bottom up, analyze block and it builds a model for top analysis.
– Model has a current source per pin, and a matrix of pin
interconnection Rs.
confidential

– Similar to paper of Blaauw in DAC 2000.

 Better run times and higher capacity
51 – New matrix size reduction techniques can help
 Model for Cell Power Supply Network

 Model is exact for a linear system –works for transient response too

1 Z13 3
Z14
Z12 Z34
Z23
4
confidential

2 Z24

52
 Flow analysis/testing:
 There are many interactions within a place and route flow
 Must verify (for example) that fixing one violation does not cause
others (at least on the average)
 Crosstalk (for example) can be fixed in many places
– Aggressive sizing in synthesis/placement
– Post track assignment analysis
– Post detail routing analysis
 Which of these has minimum impact on chip performance and/or
confidential

time to market?
53
90nm and Beyond – Subwavelength Effects
What you draw is not what you Image!

 Widths and spacings affected by neighboring geometries

 OPC (Optical Proximity Correction) tries to fix this, but will not succeed
completely at small process sizes.
 Eventually will impact manufacturability and routing, and possibly placement
User Without Mask Silicon
draws OPC w/OPC fabbed
 90nm and Beyond – Inductance
 Inductance is required in some cases
– Package models, PC boards, MCMs, Flip-chip packages

 For on-chip wires, it is sometimes (rarely) required

– “Short” wires (compared to their rise time) are equipotential
– “Long” wires have an R that dominates their L
– In both these cases L is not needed*. Most nets meet one of these rules

 A physical prototype allows our analysis to determine on a net by net basis

whether L is needed. If not, we don’t extract it.
– For the remaining nets the extraction and timing infrastructure must support inductance
confidential

– Result: accurate analysis without a serious time penalty

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* “Figures of Merit to Characterize the Importance of On-Chip Inductance”, by

Ismail, Friedman, and Neves, IEEE Transactions on VLSI Systems, December 1999
 Summary
 Lots of activity in the area of Signal Integrity!
– Better analysis of all kinds of effects
– SI prevention features in synthesis
– Improvements to extraction
– Improved SI prevention in placement and routing
– Improved power supply analysis
 New problems coming at 90 nm and below!
confidential

 Will provide job security for years to come!

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