HANDBOOK OF DIGITAL

TECHNIQUES FOR
HIGH-SPEED DESIGN
Design Examples, Signaling and Memory
Technologies, Fiber Optics, Modeling and
Simulation to Ensure Signal Integrity

Tom Granberg, Ph.D .

PRENTICE HALL PTR

UPPER SADDLE RIVE NJ 07458
PRENTICE
HALL WWWIPHPTP.COM
PTR
CONTENTS

Preface xxxvii
How This Book Is Organized xxxvii
This Textbook Was Written with Educational Institutions in Mind xxxix
University Courses for Which This Book Is Suitable xl
Solutions Manual Is Available xl
Cash for Identifying Textbook Errors xl
How This Book Was Prepared x1i
Personal Acknowledgments x1i
Technical Acknowledgments xliii

Part -1 Introduction I

Chapter y Trends in High-Speed Design 3

1,1 Everything Keeps Getting Faster and Faster? 3
1.2 Emerging Technologies and Industry Trends 6
1 .2.1 Major Drivers of Printed Circuit Board (PCB) Technology 6
1 .2,2 Drivers of Innovation 6
1 .2.3 110 Signaling Standards 7
1 .2.4 Web Site as Retailer 8
1,2.5 Memories 8
1 .2.6 On-Die Terminations 9
1 .3 Trends in Bus Architecture 9
1 .3 .1 Moving from Parallel to Serial 10
1 .3 .2 The Power ofTools 11
1 .3 .3 ASSPs and ASMs 12
1 .4 High-Speed Design as an Offshoot from Microwave Theory 12
1 .5 Background Disciplines Needed for High-Speed Design 13
1 .5.1 High-Speed Conferences and Forums 13
1 .6 Book Organization 14
1.7 Exercises 15
 Contents

Chapter 2 ASICs, Backplane Configurations,

and SerDes Technology 17
2.1 Application-Specific Integrated Circuits (ASICs) 17
2.2 Bus Configurations 18
2.2.1 Single-Termination Multidrop 18
2.2.2 Double-Termination Multidrop 19
2.2.3 Data Distribution with Point-to-Point Links 19
2.2.4 Muitipoint 20
2.2.5 Switch Matrix 20
Mesh and Fabric Point-to-Point Bus Architeclures 21

2.3 SerDes Devices 21

2 .3.1 SerDes Device Fundamentals 21
2 .3.2 SerDes at 5 Gbps 24
2.3.3 SerDes Multibit Signal Encoding 26
2.4 Electrical Interconnects vs. Fiber Optics 26
2.5 Subtleties of Device Families 27
2.5.1 Logic vs, Interface Families 27
2 .5.2 Murky Device Categories 28
2 .5.3 Logic Family vs. Signaling Standard 28
2.6 EDN Magazine's Microprocessor Directory 28
2.7 Exercises 29

Chapter 3 A Few Basics on Signal Integrity 3x.

3.1 Transmission Lines and Termination 31
3.1 .1 Transmission Line Equations 31
3 .1 .2 Reflection Coefficients, Lattice Diagrams, and Termination 34
3.2 Important High-Speed Concepts 38
3.2.1 Rise Time and Edge Rate 38
3.2.2 Length of the Rising Edge 39
3.2.3 Knee Frequency 40
3.2.4 Single-Ended vs. Differential Transmission 40
3.2.5 Fast Edge Rate Effects 41
3 .2.6 Parasitics 42
3.3 High-Frequency Effects : Skin Effect, Crowding Effect, Return Path
Resistance, and Frequency-Dependent Dielectric Loss 42
3.4 Sitter Measurements Using Eye patterns 43
3.5 BER Testing 46
3.6 Exercises 47
Contents

Part 2 Signaling Technologies and Devices 49

Chapter 4 Gunning Transceiver Logic

(GTL, GTLP, GTL+, AGTL+) 51,
4.1 Evolution from Backplane Transceiver Logic (BTL) 51
4.2 Gunning Transceiver Logic (GTL) 53
4,3 Gunning Transceiver Logic Plus (GTLP) 54
4,3 .1 GTLP General Description and Applications 54
4.3.2 GTLP Throughput and Performance 56
4.3.3 GTLP Signaling Levels, Noise Margins, and Current Drive 56
4.3 .4 GTLP Device Features 58
Live Insertion and EStractioti 58
Controller) Edge Rates SS
Busltoid (A Port) 60
4.3 .5 GTLP Backplane Design Considerations 61
4,3 .6 GTLP Power Consumption 64
4,4 Intel's AGTL+ and GTL+ 65
4.5 GTLPIGTLIGTL+/AGTL+ Summary 67
4.6 Exercises 69

Chapter 5 Low Voltage Differential Signaling (LVDS) 71

5.1 Introduction to LVDS 71
5,1 .1 How LVDS Works 73
5.1 .2 Why Low Swing Differential? 77
5.1 .3 The LVDS and M-LVDS Standards 77
The TIAIEIA-644-A Standard 78
5.1 .4 Appearance of Laboratory LVDS Waveforms 80
More Discussion of the Evahiation Boairl 82
Conrnnon-Mode Noise 84
Probing ofHigh-Speed LVDS Signals 86
5.1 .5 Easy Termination 87
5,1 .6 Maximum Switching Speed 88
5.1 .7 Saving Power 88
5.1 .8 LVDS Configurations 88
5.1 .9 Low Voltage Differential Signaling (LVDS) Families 90
5,1 .10 LVDS as a Low-Cost Design Solution 91
5.1 .11 Example of the Wide Range of LVDS Solutions 92
A Contents

5.2 Comparison of LVDS to Other Signaling Technologies

Using Design Examples 93
5.2.1 LVDS Drivers and Receivers 94
5.2.2 100 Mbps Serial Interconnect 96
5.2.3 LVDS Channel Link Scrializers 98
5.2.4 1 Gbps 16-Bit Interconnect 98
5.2.5 1 .4 Gbps 56-Bit Backplane 100
5.3 Summary of LVDS Features and Applications 103
5 .4 Exercises 104

Chapter 6 Bus LVDS (BLVDS), LVDS Multipoint

(LVDM), and Multipoint LVDS (M-LVDS) 107
6.1 Justification for Enhanced Versions of LVDS 107
6.2 Bus LVDS (BLVDS) 108
6.2.1 System Benefits of Bus LVDS 109
6.2.2 High-Speed Capability 110
6.2 .3 Low Power 110
6.2.4 Low Swing, Low Noise, and Low EMI 1i1
6.2.5 Low System Cost 111
6.2.6 Bus Failsafe Biasing 112
6.2.7 Hot Plugging (Live Insertion) 113
6.3 LVDS Multipoint (LVDM) 114
6.4 Multipoint LVDS (M-LVDS) 117
6.4.1 The TIAIEIA-899 Standard 117
6.5 Selecting BLVDS, BLVM, and M-LVDS Devices 123
6.6 Exercises 125

Chapter 7 High-Speed Transceiver Logic (HSTL)

and Stub-Series Terminated Logic (SSTL) 129
7 .1 High-Speed Transceiver Logic (HSTL) 129
7.1 .1 The HSTL Standard 129
7.1 .2 Supply Voltages and Logic Levels 131
7.1 .3 Classes of HSTL Output Buffers 136
7.1 .4 FPGAs with HSTL 110s 138
7.1 .5 HSTL Summary 140
7 .2 Stub-Series Terminated Logic (SSTL) 141
7 .2.1 SSTL 3 142
Supply Voltage and Logic Input Levels 143
SSTL_3 Output Buffers 145
Contents x111

7.2 .2 SSTL 2 148

SSTL_2 for Single-Ended Inputs and Outputs 148
SSTL_2 for Differential Inputs and Outputs 150
Illustration of SSTL_2 Thresholds 151
Comparison of SSTL_2 with LVTTL 151
SSTL_2 Design Example -DDR SDRAM Memory Subsystem 155
7.2.3
SSTL 18 156
7 .2.4 Summary of SSTL 160
7.3 Exercises 161

Chapter a Emitter Coupled Logic (ECL, PECL,

LVPECL, ECLinPS Lite and Plus, SiGe,
ECL Pro, GigaPro and GigaComm) 165
8.1 A Fast Technology - Edge Rates of 20 ps at 12 Gbps? 165
8.1 .1 The ECL Families 167
8.1 .2 ECL Vendor Products 167
8.1 .3 Comparison of Several ECL Family Members 169
Power Consumption ofECL Family Devices 169
8.2 Basic Device Operation 171
8.3 The Two Major ECL Standards -10K and 100K 172
8.3.1 ECL Output Load Drive Characteristics 174
8.3 .2 The "10" and "100" Prefixes -Both Family and Standard 175
8.3.3 Five Kinds of ECL Family Outputs 175
8.4 Single-Ended and Differential Signaling 175
8.4.1 Standard ECL Interface: Differential Driver and Receiver 176
Advantages and Disadvantages of Single-Ended and
Differential Interconnects 176
8.4.2 Single-Ended Interface 176
VBB Reference 177
The Voltage Reference Source VBB 178
Dedicated Single-Ended Input Structure 178
Single-Ended Interface Between 10 and 100 Standards 179
Voltage Transfer Curves 179
8.4.3 Differential Interface 180
VIHCMR 181
Differential Interface Between 10 and 100 Standards 181
ECL Noise Margins 181
8,5 Component Nomenclature 183
8.6 The ECL Families and Their Characteristics 184
8.6.1 A Little MECL History 184
AV Contents

8.6 .2 10K 184

8.6.3 10H 185
Dual Meaning ofIOH Prefix 185
8.6.4 100K 185
8.6.5 100H 186
100H Used rrs Designation fir Clock Drivers/Translators 186
Caution : IOH and 10011 Devices with "L" Suffix
May Use OtherPower 0ptions 186
Micrel's 10H and 100H 187
8.6.6 ECL, PECL, Psuedo ECL, NECL, LVECL, LVPECL, and LVNECL 197
300 Series ECL 187
Super-300K L CL 188
9300 and 9400 Series ECLIPECL 1,48
ON Semiconductor's GigaConvn Family (SiGe) 188
Hot Ssmpping PECL Risk: Powered Driver and Unlrowered Receiver
189
8.6 .7 ECLinPS and Low Voltage ECLinPS 189
8.6.8 ECLinPS Lite, Low Voltage ECLinPs Lite, and ECL Lite 189
8.6.9 ECLinPS Plus, ECL Pro, ECLinPS Pro, and Low Voltage ECLinPS Plus 191
8.6 .10 Reduced Swing ECL (RSECL, RSPECL, RSNECL)
and Variable Outputs 191
Reduced-Swing ECL vs. Low Voltage ECL 193
8 .7 Summary of the ECL Families 193
8.8 Exercises l95

Chapter 9 Current-Mode Logic (CML) 199

9.1 CML Overview 199
9.2 CML Output Structure 202
9.3 CML Input Structure 203
9.4 ac- and dc-Coupled CML Circuits 204
9.5 XAUI Interface Standard 207
9.6 CML Design Considerations 211
9.6.1 Pre-Emphasis, De-Emphasis, Transmit Equalization,
and Receive Equalization 211
9.6.2 ac Coupling Requires 81311[}13 Encoding or de-Balanced Signal 213
9.7 How CML and ECL Differ 213
9.8 SuperLite CML and GigaPro"'M CML 218
9.9 Vendor-Specific CML Examples 219
9.9.1 Texas Instruments' SN65CMLIOO 218
9.9.2 Texas Instruments' TLK2501 1.5 to 2 .5 Gbps Transceiver 220
 9.9.3 Maxim's MAX3900 3 .2 Gbps Adaptive Equalizer and Cable Driver 223
Adaptive Equalization 225
9,10 Summary of Current-Mode Logic (CML) 226
9 .11 Exercises 227

Chapter y o FPGAs --- 3.1.25 Gasps RocketfOs and

HardCopy Devices 231
10.1 Industry Trends 231
10.2 Altera FPGAS and CPLDs 233
10.2 .1 Altera PPGAs with Embedded High-Speed Transceivers 234
Stratix GX FPGAs with tip to 20 Channels of 3.1825 Gbps SerDes 235
Meivury FPGAs with rip to 45 Gbps of Bandwidth 237
10.2.2 Altera HardCopy Devices 238
Elimination of ASIC Risk 239
HardCopy Devices Designed with Quartus 11 Software 240
HardCopy Stratix and APEX Devices 240
10.2.3 High-Density FPGAs 241
Stratix FPGAs 242
APEX FPGAs 243
10.2.4 Low-Cost/High-Volume FPGAs 244
Cyclone FPGAs 244
ACEX FPGAs 245
10.2.5 Altera FPGAs with Embedded Processors 245
Excalibur Devices 2,45
10.2.6 Altera CPLDs 246
MAX 3000 CPLDs 246
MAX 7000 CPLDs 246
MAX 7000AE CPLDs 246
MAX 7000B CPLDs 247
MAX 70005 CPLDs 247
10,2.7 Configuration Devices 247
10,3 Xilinx FPGAs and CPLDs 248
10.3 .1 Virtex FPGAs 248
10.3 .2 Spartan FPGAs 248
10,3 .3 CPLDs 248
CoolRuuner CPLDs 249
XC9500 249

10.3.4 More About the Virtex-II Pro FPGA 249

10.3.5 Virtex-11 Pro RocketIO Multi-Gigabit Transceiver 250
10.3.6 The Virtex-TI Pro PowerPC 405 Processor Core 251
PPC405x3 Hardware Organization 252
xvi Contents

10.3 .7 Applications of the Virtex-11 Pro 253

Data Pines 253
Reducing PCB Cotnplaxity 254
10.3.8 Support of Communications Standards 254
System-on-a-Chip (SOC) Designs 254
Network Processing 255
Protocol Bridges 255
10.3.9 Other Features of Virtex-11 Pro Devices 255
Global Clock Networks 255
Single-Ended SelectIOrh{-Ultra Resources 256
LVDS 1/0 256
LVPECL 1/0 256
Block SelecIRAW,' Memory 256
Distributed SelectRAM Memory 256
Bitstream Encryption 257
Loopback 257
Digital Clock Managers (DCMs) 257
Digitally Controlled Impedance (DCI) 258
Double-Data-Rate (DDR)1/0 258
10 .3.10 IBIS and SPICE Models for Xilinx Devices 258
10.3.11 Xilinx Intellectual Property (IP) Cores 259
10.4 Exercises 260

Chapter 11 Fiber-Optic Components 263

11,1 Getting On Board with Optics 263
11 .1 .1 The Rationale for Optical Interconnects 263
11,1 .2 Optics in the Physical Design 264
11,1 .3 Modeling Optical Interconnects 265
11,2 Comparison of Copper and Fiber Transmission Media 265
11 .3 Application Space for High-Speed Optical Data Link Modules 267
11 .4 Using Fiber for the Short Haul 268
11 .4.1 User Beware 271
11 .5 The 10 Gbps X-Modules 272
11,5.1 Xenpak 273
Xenpak MSA 275
11 .5.2 Xpak 276
11 .5.3 X2 Module 277
11 .5.4 XFP Module 278
11 .6 PAROLI 2 Parallel Optical Link Modules and Backplane Optical Interconnects 279
11 .7 Dense-Wavelength-Division Multiplexing (DWDM) 283
Contents XV11

11 .8 Trends in the Application of Fiber Optics 283

11 .8.1 Exciting Optical Devices 284
11 .8.2 PON Devices 286
11 .9 Optical Cable Applications 287
11 .10 Optical Internetworking Forum (OIF) 288
11 .11 Fiber-Optic Connectors 288
11 .11.1 Small Form Factor Connectors 288
11,11.2 InfiniBand Connectors 289
11 .12 Laser Safety 290
11 .13 Vendors and Organizations for Fiber-Optic Components 291
11 .14 Exercises 292

Chapter 12 High-Speed Interconnects and Cabling 295

12.1 SiliconPipe's 12 .8 GHz to 40 GHz Interconnect Solutions 295
12,1 .1 Yosemite - 40 Gbps Backplane Channel Technology 296
12.1 .2 Sequoia - 20 Gbps Chip-to-Chip Channel Technologies 297
12 .1 .3 Grand Canyon ---12 .8 Gbps Memory Channel Technologies 298
ChaniPlexer-High-Speed Menzoiy Channel 298
SeriPlexer-Next-Gen Meniony Channel Technology 298
12.1 .4 Limitations of Conventional Backplanes 298
12.1 .5 How SiliconPipe Technology Works 300
Backplanes 300
Mennony Interconnects 302
12.2 High-Speed Connectors 302
12.2.1 Teradyne VHDM-HSD Connector Example 303
12,2.2 XAUI Connectors 304
12.2.3 InfiniBand Connector 305
12.3 High-Speed Cabling 305
12.3.1 Copper Cable Applications 305
12.3.2 InfiniBand Cabling 305
12 .4 Cables and Connectors for LVDS 306
12,4.1 General Comments on Cables and Connectors 306
12,4.2 Cabling Suggestions 307
71visted Pair 307
Tvin-Ax Cables 307
Flex Circuit 308
Ribbon Cable 308
12.4.3 Connectors 308
12.4 .4 Cable Ground and Shield Connections 310
12.5 Exercises 311
 Contents

Part 3 High-Speed Memory

and Memory Interfaces 313

Chapter 13 Memory Device Overview and

Memory Signaling Technologies 315
13.1 Overview and Trends 315
13 .2 A Quick Review of Memory Basics 319
13.2.1 Read/Write Memory 319
13.2.2 Static RAM 320
Static RAM Inputs and Outputs 320
Static RAM Tining 321
Synchronous SRAM 323
13.2.3 Dynamic RAM (DRAM) 325
Dynamic RAM Structure: 325
Dynatnic RAM Tuning 327
Synchronous DRAMS 329
FPM (Fast Page Mode) DRAM 330
EDO DRAM (Extended Data Out DRAM) 331
RLDRAM (Reduced Latency DRAM) 331
13.2.4 Special Application Memory 331
Video RAM (VRAM) 331
Dual-Port Graphics Buffer 331
SGRAM (Synchronous Graphics RAM) 332
13.2.5 Read-Only Memory (ROM) 332
13 .2.6 Flash Memory 333
13 .2.7 ECC (Error-Correcting Code) Memory 333
13 .2.$ Banks and Ranks 334
Batiks 334
Ranks 334
13 .2.9 Memory Nomenclature 335
Speed Bin 336
13 .3 Memory Signaling Technologies 337
13 .3.1 SSTL_18, SSTL_2, and HSTL (Class 11) 337
13.3.2 RSL (Rambus Signaling Level) 337
13 .3.3 DRSL (Differential Rambus Signaling Levels) 338
13 .3.4 QRSL (Quad Rambus Signaling Levels) 339
13.3.5 Octal Data Rate (ODR) 340
13 .4 Design Considerations in Use of Memory 340
13 .4.1 Power Up and Initialization 340
 13 .4.2 Slew Rate Control 341
13 .4.3 Drive Capability 341
13 .4.4 On-Die Termination (ODT) 342
Modifying Terrninations "On-the-Fly" 343
13.4.5 Memory Power and Ground Planes 344
13.4.6 Memory Controllers 344
13.5 Summary of Memory Devices and Terminology 344
13 .6 Exercises 350

Chapter -14 Double Data Rate SDRAM (DDR, DDR2)

and SPICE Simulation 353
14.1 DDR (Double Data Rate) SDRAM 353
14.1 .1 Differences Between SDRAM and DDR SDRAM 354
Drferences in Functions and Specifications 354
Differences in Connnands 359
Dif ferences in Operation 7-aning 361
14.2 DDR2 (Double Data Rate 2, DDR-11) SDRAM 363
14.2.1 DRAM Architecture Changes 364
DDR2 Array Definition 364
DDR2 Page Size 364
DDR2 Bank Accesses 365
14.2.2 On-Die Termination 366
ODT WRITES 367
ODT READS 367
Termination Values 369
On-Die Termination Control in Active Mode 370
On-Die Termination Control in Porver-Dotim 370
On-Die Termination Control in SelfRefresh 371
Off-Chip Driver (OED) Calibration 371
14.2.3 Additional Mode Register Changes 373
Mode Register (MR) 373
CAS Latency 373
WRITE Latency 375
Sequential Interleave 376
Active Poiver-Down Mode 376
Write Recovery 377
&tendedMode Register (EMR) 378
Additive Latency 378
DQS Configuration 380
Single/Differential Data Strobe 381
Redundant DQS (RDQS) 381
Output Disable 381
 Contents

14.3 SPICE/IBIS Simulation of DDR-Ii SDRAM 382

14.3 .1 SPICEABIS Simulations of DQ and DQS Pins 382
14.3.2 Clock Signal Integrity 387
14 .4 Exercises 389

Chapter -i 5 GDDR3, ZBT, FCRAM, SigmaRAM,

RLDRAM, DDR SRAM, Flash, FeRAM,
and MRAM 391
15.1 Graphics Double Data Rate SDRAM (GDDR, GDDR2, GDDR3) 391
15.1.1 GDDR3 (Graphics DDR 3) 394
GDDR3 Derdce Operation 394
GDDR3 Power Consumption Calculations 395
15.1 .2 Terminology; GDDR SDRAM vs. DDR SDRAM 395
15.2 ZBT, NaBL, ZeroSB, and NtRAM SRAM 396
15.3 FCRAM (Fast Cycle RAM) 397
15.3.1 Network FCRAM 399
15.3.2 Mobile FCRAM 399
Stacked MCP (Multi-Grip Package) 400
15.3.3 Consumer FCRAM 400
The Low Ivtency of Consumer FCRAM 401
Consroner FCRAM for SiP (System-in-a-Package) 404
15.3 .4 Summary of FCRAM Features 404
15.4 SigmaRAM (IRAM) 405
15.4.1 The SigmaRAM Family 406
15.4.2 SigmaRAM Features 407
15,5 RLDRAM (Reduced Latency DRAM) 407
15 .5 .1 RLDRAM as a New Memory Standard for High-Speed Applications 408
Networking Requirements 408
Pmgrarnnrable ltnpedance Output Buffer 409
15 .5 .2 RLDRAM I and RLDRAM 11 409
15.6 DDR SRAM (Double Data Rate SRAM - DDR, DDRII SRAM) 410
15.6.1 DDRII SRAM Specified by QDR Consortium 411
15.6.2 Comparison of DDRII SRAM and DDR-II SDRAM IIOs 412
15.7 Flash Memory 412
15.7.1 Flash Densities, Access Tithes, and Other Features 413
15.7.2 Cell Phone Applications 414
15.7 .3 NOR vs. NAND Flash 415
15.7.4 Significance of Block Size 416
15.7 .5 Read-While-Write (RWW) Flash 417
Contents XXI

15.7.6 Page-Mode Flash Memory 417

Page Definition 418
How a Page-Mode Read Works 418
Conilmring a Page-Mode Device to a Standard Device 419
Requirements on a System Using Page-Mode Flash 420
15 .7 .7 Burst-Mode Flash Memory 420
15.7.8 MirrorFlash and Multi-Level Cell (MLC) 421
15 .7 .9 Role of Software 422
15.7.10 Flash Interfaces 422
15.7.11 Flash Cards 423
15 .8 FeRAM (Ferroelectric RAM) and MRAM (Magnetoresistive RAM) 424
15.9 Memory Selection Guide 425
15.10 Exercises 425

Chapter 16 Quad Data Rate (QDR, QDRI1) SRAM 429

16.1 Introduction to QDR 429
16.1.1 Choosing the Right SRAM 430
16.1.2 Address Rate 433
16.1.3 Write Data Placement 433
16.1.4 Clocking Design 434
16.2 QDR SRAM Clocking Scheme 435
16.2.1 The QDR Device 435
16.2.2 Using the Separate Input and Output Clocks 436
16.2,3 Latching Data at the Controller 437
16.3 Comparison of QDR with QDRII 438
16 .3.1 QDRII and QDR Functional Differences 440
16.3.2 QDRIJ Features 440
Data Valid Window 441
ECho Clocks 441
16.3.3 Negative Hold Times 441
16.3.4 Impact of DLL on the Operating Frequency Range 442
16.3.5 Choosing Between Burst of 2 and Burst of 4 443
16 .3 .6 Compatibility Considerations Between QDRII and QDR 443
16.3.7 Typical Implementation in a System 443
Write Tunings 444
Read Tanings 445
16.3.8 Package 447
16.3.9 Output Impedance Control 447
16.3.10 Data Line Terminations 447
QDR IBIS and HSPICE Models 448
 Contents

16.3.11 Clamshell Design 448

16.4 Exercises 449

Chapter -17 Direct Ramous DRAM (DRDRAM) 451

17.1 Direct Rambus DRAM""' (DRDRAM, RDRAM) 452
17.1 .1 RDRAM Memory 454
17.1 .2 The Memory Landscape 455
17.1 .3 Bandwidth and Latency 456
Comparing RDRAM with SDRAM and DDR SDRAM 456
Asstanptions for Comparisons 457
Recd-World Performance : Bandwidth 457
SDRAM Bank Conflict and Command Bus Bandwidth Limitations 458
Real-World Performance : Latency 459
17.1 .4
System Cost: Memory Granularity 459
17.1 .5
System Cost: Pincount and Bandwidth 460
17.1 .6 Motherboard Layers and Power Dissipation 460
17.2 Long-Channel Design 461
17.2.1 Rambus Memory System 461
17 .2.2 Schematics of a 16-Bit, Long-Channel Rambus System 463
17 .3 Exercises 468

Chapter -1 s Xtrerne Data Rate (XDR) DRAM,

FIexPhase and ODR 471
18 .1 Introduction to XDR 471
18.1 .1 XDR DRAM 472
18.1 .2 XDR DRAM Summary Table 473
18,1 .3 DRAM Block Diagram 473
18 .1 .4 XDR System Overview 475
18.2 XDR Physical Layer 476
18.2.1 Signaling 476
18 .2.2 Clocking 477
18,2.3 Data Transfers 478
18,2.4 Address/Control Transfers 479
18 .2.5 XDR 310 Cell (XID) 480
18.3 XDR Logical Layer 481
18 .3 .1 Write Transaction 482
18.3.2 Read Transaction 4.82
18.4 Applications 482
Contents XXIII

18 .4.1 The Gaming Console Solution 482

18.4.2 The HDTV/Consumer Solution 483
18.4.3 The PC Graphics Solution 484
18.4.4 The PC Main Memory Solution 484
18.5 Exercises 486

Part 4 Modeling, Simulation, and EDA Tools 489

Chapter -19 Differential and Mixed-Mode S-Parameters 491

19.1 S-Parameters Bridge the Gap Between Chips and Systems 492
19.2 The Rationale for Using S-Parameters 493
19.2.1 Package Measurements 494
19.3 Single-Ended S-Parameters 495
19 .3.1 Introduction 495
19.3.2 Two-Port Network Theory 495
19.3 .3
Using S-Parameters 496
Derivation 497
19 .3 .4 Smith Chart Transformation 499
19.3.5 Advantages of S-Parameters 500
19.4 Differential and Mixed-Mode S-Parameters, 501
19.4.1 The Need for Differential and Mixed-Mode S -Parameters 507
19.4.2 Return Loss Measurement Example 508
19.4 .3 Touchstone Format 510
19.5 Calibration 511
19.5 .1 Measurement Errors 511
19.5 .2 Removing Test Fixture Effects : Direct Measurement and De-Embedding 511
19.5 .3 Calibration Example: Using Direct Measurement to
Eliminate Test Fixture Effects 513
19 .6 Exercises 516

Chapter 20 Time Domain Reffectometry (TDR),

Time Domain Transmission (TDT), and VNAs 519
20.1 Time Domain Reflectometry (TDR) 519
20.1 .1 Introduction 519
20.1 .2 Single-Ended TDR Measurements 520
TDR and Luml)ed Element Analysis 522
TDR Resolxtion and Rise Time 522
XXIV Contents

20 .1.3 Differential TDR Measurements 524

Differential and Odd-, Common- and Even-Mode Impedances 525
20.1 .4 Cables, Connectors, and Probes 527
20.1.5 Multiple Reflections and the True Impedance Profile 528
20.1 .6 Other TDR Measurement Issues 531
Using Good Measurement Practices 531
TDR Measurements of "Splits" and "Stubs" 531
20.1 .7 Frequency Domain and TDR 532
20.1 .8 Static Discharge Precautions 534
20.1 .9 Controlling Rise Time 534
20.1 .10 Example ofTDR Oscilloscope 535
20.2 Time Domain Transmission (TDT) 536
20.3 TDR and TDT Simulations for a Loaded BLVDS Backplane 536
20.3 .1 Loading Effects of Connectors, Stubs, and ICs on the Backplane 536
20.3.2 Effect of Plug-In Card Stub Lengths 538
20.4 Vector Network Analyzer (VNA) 540
20.4.1 VNA Instrumentation Background 540
20.4.2Network Analyzer Terminology :
R, A, and B Channels vs. Port I and Port 2 541
20.4.3 The Differences Between VNAs, Scalar Network Analyzers
(SNAs), and Spectrum Analyzers 542
20.4.4 Vector Error Correction of Systematic Measurement Errors 544
20.4.5 The Mathematics of Time and Frequency 545
20.4.6 Practical Comparison of TDR and VNA Measurements 546
Frequency Domain Measurements Using TDR 549
20.4.7 VNAs with Time Domain Capability 550
20.4.8 Comparison, Summary, and Recommendations 550
20,5 Exercises 551

Chapter 2 -1 Modeling with IBIS 555

21 .1 An Introduction to IBIS (110 Buffer Information Specification) Modeling 555
21 .1 .1 Introduction 555
21 .1 .2 About IBIS 556
21 .1 .3 History of IBIS 556
21 .1 .4 Golden Parser 557
21 .1 .5 Advantages of IBIS 557
21 .1 .6 Input Structure Model 557
21 .1 .7 Output Structure Model 557
Contents XXV

21 .1 .8 The IBIS Model Generation Process 559

21 .1.9 IBIS Model Validation on a Simulator 559
21 .1 .10 Using SPICE to Model Multigigabit FPGA 110s and Pre"Emphasis 560
21 .1 .11 Future Trends of IBIS 561
21 .2 Example of an IBIS Model 561
21 .3 Exercises 569

Chapter 22 Mentor Graphics --- EDA Tools for

High-Speed Design, Simulation, Verification,
and Layout 571
22.1 Overview of Mentor Graphics High-Speed Tools 571
22.2 ICX 573
22.2.1 IS Analyzer 575
Hierarchical Rides Entry and Managenrew 57.5
Analysis and Verification 575
System-bevel Defin tion and Analysis 576
1$.-Analyzer Major Benefits 576
22.2.2 IS_Floorplanner 576
Ilierarclzical Rides Management 576
Hierarchical Floorplanning 577
A Complete Wlzat-fAnalysis Environment 577
Analysis and Verification 577
Major IS_Floorplanner Benefits 578
22.2.3 IS Multiboard 578
System-Level PCB Design 578
Systemi-Level Definition 578
Analysis and Verification 578
22.2.4 IS-Optimizer 580
Electrically Driven Interconnect Design 580
Hierarchical Rides Entry and Management 580
Interconnect Optunization 580
Interactive Syndiesis 581
Underlying Architecture 581
22.2.5 IS Synthesizer 581
Electrically Driven Interconnect Design 581
Hieranrldcal Rides Entry and Management 5231
Interconnect Optiuzizatiort 582
Interactive Synthesis 582
Powerful Underlying Teclinology 582
22 .3 Tau 583
22.3.1 Circuit Timing Methods and Symbolic Timing 583
Timing Methods 584
 xxvi Contents

Symbolic 7hning Analysis with 7itu 585

Timing Models 585
Using Tan in a Workflow 586
Conchrsion 587
22.4 HyperLynx 587
22.4.1 HyperLynx GHz 588
Complete S1 and EMC Analysis Suite 589
LineSbn GHz 589
22.4.2 HyperLynx EXT 589
Complete S1 and EMC Analysis Suite 590
LineShn EX7' 590
22.5 Mentor Graphics Field Solvers Used in ICX and HyperLynx 591
22.5.1 Introduction 591
22.5.2 Geometry Problem Entry and Discretization 592
22.5.3 Speed and Accuracy 593
22.5.4 The Method of Moment Technique 593
22.6 The Expedition Series and Design Flow 594
22 .6.1 DxDesigner 594
Design Reuse 595
Integration with the Enterprise 596
Constraint-Based Design. 596
Variant Managentent 596
22.6.2 Expedition PCB 596
AwoActive Technology 597
Dynanuc Area Fills 598
Rules by Area 598
Multiplow with Variable Via Patterns 598
Dynamic Hazard Review 599
ECOs with Expedition PCB and the Expedition Series 599
Constraint Definition 599
Net Tutting
599
Differential Pair Routing 599
Advanced Interconnect Routing 599
TeaniPCB 601
Design Reuse 601
DMS -- Design Data Management 601
22.6.3 FPGA BoardLink 601
FPGA On-Board 602
Reducing Design Times for FPGA/PCB hrtegration 602
FPGA Device Support 603
22.6.4 HDL Designer Series (FPGA Advantage) 603
The Design Manager Provides Complete Design Visibility 603
Tusks Support Repeatable Design Process 603
Contents xxvff

Mix Text, Tabular ; and Graphical Editors .for Varying Design Requirements 604
lrrrerfaced-Based Design Methodology Rapidly Defbres Design Structure 604
hrfuilive Graphical Editors 605
Flexible ModuleWare Logic Generator 605
Practical IP and Design Reuse 605
22 .6.5 ModelSim (FPGA Advantage) 606
High-Performance, Trilingual verification Environment 606
Verilog 2001/SysteniVerilog 607
22 .6.6 Quiet Expert 607
EMC-Based Design Ride Checker 607
Easy Viewing of Results 608
Custonrizable Flow Control 609
22.7 Signal Integrity and Timing Models 610
22.7.1 Signal Integrity Models 610
Isis 610
SPICE 610
VHDL-AMS 610
22 .7.2 Tinning Models 611
TDML 611
STAMP 612
TDML vs. STAMP 613
22,8 Use the Right Models for Simulation of Multigigabit Channels 613
22 .8.1 Introduction 613
22 .8.2 The Circuit under Study 614
22 .8.3 Model Reduction 616
22 .8.4 Package Model Simplification 617
Package Element Elimination 619
IBIS RLC Package 619
S-Paranreler Package Model 619
22 .8.5 Behavioral Modeling 620
22.8.6 Conclusion 622
22.9 Exercises 623

Part 5 Design Concepts and Examples 625

Chapter 23 Advances in Design, Modeling, Simulation,

and Measurement Validation of High-Performance
Board-to-Board 5-to-10 Gbps Interconnects 627
23.1 Introduction 627
23.2 Modeling Methodology 630
 Contents

23 .2.1 Major System Elements 630

PCB Trace Modeling 632
Connector Design 635
Breakout Region (BOR) Modeling 636
Was 639
23.3 Simulation 639
23 .3 .1 HSPICE W-Element Issues 640
Passivity in Frequency Domain Network Measurement and Simulation 640
Managing Error in Frequency Domain Network Parameters 641
Error-Induced Nonpassivity ofNetwork Parameters 642
Correcting ErrorInduced Nonpassivity in S-Parameter Network Models 644
23 .4 Measurement 648
23.4 .1 The Design and Need for High-Accuracy Test Boards 648
High-Bandwidth SMA Launch 648
Isolation of Traces Prior to Final Inch 649
Reference Structures 649
23 .5 Measurement Accuracy Issues 649
23.5 .1 SMA Launch 650
23.5 .2 Traces 652
23.5 .3 Measurements 652
23 .6 Frequency Domain Measurement 652
23 .6 .1 Calibration 652
23 .6 .2 Measurements 652
23 .6 .3 Time Domain Measurements 652
23 .6 .4 Application Proof 653
23.7 Validation of Material Parameters 653
23 .7 .1 Terms 654
23 .7 .2 Some Extracted Data 655
23 .7.3 Overview of Characterization Methods 655
23.8 Stripline Measurements 656
23 .8 .1 Stackup 656
23.8.2 de Resistance 656
23 .8 .3 Characteristic Impedance and Delay 658
23.9 Stripline Results 658
23,9.1 Effective Relative Dielectric Constant 658
23.9.2 Total Losses for Stripline 659
23 .9.3 Loss Tangent Estimation 660
23.10 Calculation Methods and Validation 664
23.10.1 Comparison of Connector Simulations with
and without Final Inch and Discussion of Advantages 665
Contents xxfx

23.10.2 SMA Test Trace Comparisons, Modeled vs . Measured 670

23.11 Conclusions 673
23.12 Exercises 674

Appendix 23.A Generalized N-Port, Mixed-Mode

S-Parameters 676
23.A.1 Why Do We Care? 676
23.A.2 Development of N-Port, Mixed-Mode S-Parameters 677

Chapter 24 IBIS Modeling and Simulation of

High-Speed Fiber-Optic Transceivers 681
24.1 Introduction 681
24.2 IBIS Models for High-Speed Fiber-Optic Transceivers 682
24.3 The Electrical Board Description (EBD) File 684
24.4 Verification of IBIS Models 685
24.5 IBIS Models in "Real-World" Circuits 687
24.6 Signal Integrity Case Study 690
24.7 Summary 692
24.8 Exercises 693

Chapter 25 Designing with LVDS 695

25.1 Layer Stack-Up and PCB Design 695
25.2 PCB Board Layout Tips 697
25.2.1 PC Board 698
25.2.2 Traces 699
25.2.3 Differential Traces 700
25.2.4 Termination 703
25 .2.5 Unused Pins 704
25.2.6 Probing LVDS Transmission Lines 705
25.2.7 Loading LVDS 110 - Preserving Balance 705
25.2.8 Results of Good vs. Bad Design Practices 705
httpedance Mismatches 705
25.2.9 Crosstalk Between TTL and LVDS Signals 706
25 .2.10 Lowering Electromagnetic Interference (EMI) 707
LVDS and Lmver EMI 707
Electromagnetic Radiation of Differential Signals 708
Design Practices for Lose EMI 710
EMI Test Results 713
xxx Contents

25 .2.11 Ground Return Paths 715

25 .2.12 Cable Shielding 716
25 .2.1 :3 Common-Mode Noise Rejection 716
25.3 LVDS Configurations 719
25 .4 Failsafe Biasing of LVDS 720
25 .4.1 LVDS Failsafe Conditions 720
25.4.2 Boosting Failsafe in Noisy Environments 721
25.4.3 Choosing External Failsafe Resistors 721
25.4 .4 Power-Off High Impedance Bus Pins 723
25.5 Bye Pattern Test Circuit 723
25.5 .1 Eye Pattern Test Procedure 723
25.5 .2 Eye Pattern Test Results and Data Points 725
25.6 BER Test Circuit 727
25.6.1 BER Test Procedure 728
25 .6 .2 BER Tests and Results 728
25.7 Exercises 729

Chapter 26 Designing to 10 Gbps Using SerDes

Transceivers, Serializers, and Deserializers 733
26.1 Introduction and the DS92LV 16 (2.56 Gbps) 733
26.2 Bus LVDS SerDes Architecture 735
26.3 Bus Topologies/Applications 736
26.3.1 Point-to-Point 738
26 .3.2 Multidrop 738
26.4 Backplanes 739
26 .4.1 Point-to-Point 739
26.4.2 Multidrop 739
26.4.3 Termination 739
26.5 PCB Recommendations 740
26 .6 Cables and Connectors
742
26.6.1 Cables 742
26.6.2 Connectors 743
26.7 Power and Ground 743
26.7.1 General Recommendations 743
26 .7.2 DS92LV l6 Bypassing Recommendations
744
PVDD/PGND PLL Supply
744
AVDD/AGND LVDS Supply
745
Comparing Power Consumption
745
Contents

DVDDIDGND Digital Supply 746

26.7 .3 Power-Up Sequencing 746
26 .8 Clocking 746
26 .8 .1 Transmit Clock (TCLK) 746
26 .8 .2 Receiver Reference Clock (RefCLK) 747
26.8 .3 Receiver Output Clock (RCLK) 747
Clock .litter 747
26.9 Inputs and Outputs 748
26.9 .1 Unused LVTTL Inputs 748
26.9 .2 Floating Bus LVDS Receiver Inputs and Failsafe 748
26 .9.3 Receiver CMOS Output Drive 748
26 .10 Evaluating the DS92LV 16 749
26 .10,1 Evaluation Board 749
26 .10.2 Probing Bus LVDS Signals 749
26.11 Loopback Testing 750
26.11,1 Local Loopback 750
26.11 .2 Line Loopback 751
26.12 Lock to Random Data vs. SYNC Patterns 751
26 .12.1 SYNC Patterns 751
26,12 .2 Lock to Random Data 751
26.12.3 Sending SYNC Patterns vs. Lock to Random Data 752
26.12.4 Once Lock Is Achieved 752
26.13 Interconnect Jitter Margin 752
26.13,1 Interconnect Jitter Mask 752
26 .13 .2 Validating Signal Quality 754
26 .13 .3 Steps to Construct a Jitter Mask 754
26 .13 .4 Alternative Jitter Estimates Using Only the Device Datasheet 758
26.14 Troubleshooting 759
26.15 Quad 2.5 Gbps (I0 Gbps) Serializer/Deserializer (SerDes) 760
26.15 .1 General Description 760
26 .15 .2 DS25C400 Features 761
26 .15 .3 Selectable Pre-Emphasis to Improve Signal Quality 761
26 .15.4 Equalization .Filtering at Receiver 762
26.16 Eight-Channel 10:1 Serializer for 5.28 Mbps 763
26.16 .1 Serializer General Description 763
26.16 .2 Serializer Features 763
26 .16.3 Serializer Functional Description 765
Initialization 765
XXXII Contents

Data Transfer 766

ResynclrronIzation 766
@Speed Test 767
Power-Down 768
TRI-STATE 768
26.16.4 Serializer Application Information 768
Using the DS92LV8028 768
Power Considerations 769
PC13 Layout and Power System Considerations 769
Transmission Media 770
Termination 770
DS92LV8028 BUDS Serializer Bypass Recommendations 770
Grounds 770
26 .17 Exercises 771

Chapter 27 WarpLink SerDes System Design Example 775

27.1 WarpLink Design Overview 775
27.2 Introduction 776
27.2.1 WarpLink 2.5 Quad Device 776
27 .2.2 WarpLink Reference Design Platform Goals 778
27 .2.3 WarpLink Reference Design Platform Overview 779
Areltitectural Overview 779
Backplane 781
Line Card 782
Switch Cant 783
Test Card 78,3
27.3 Detailed Design Descriptions 783
27.3, I WarpLink Reference Backplane 783
BackplanelCltassis Design Considerations 783
WarpLink Backplane Physical Description 786
Backplane Design Rules and Layer Stackup 787
27.3.2 Line, Switch, and Test Cards 788
Daughter Card Design Considerations 788
and
Test Card Line Card Layer Stackups 788
27.4 WarpLink Signal Integrity HSPICE Simulations 788
27 .4.1 WarpLink Gigabit Simulations 788
27 .4.2 WarpLink Interconnect Impedance Profile 792
27 .4.3 WarpLink Reference System Clock Simulations 795
27.5 Descriptions of Passive Signal Integrity Measurements 796
27.5.1 Time Domain Reflectometry (TDR) 796
Contents

27.5.2 Differential Time Domain CrosstaIk 797

27.5 .3 Eye Diagrams 797
27,5.4 Time Domain Test Equipment 797
27.6 Passive Measurement Results 798
27.6.1 TDR Results 798
27.6.2 Eye Diagram Measurement Results 798
27.7 Active Measurement Results 800
27.7.1 Test Setup 801
27,7.2 Eye Diagrams from Slot 8 to Slot 1 802
27.7 .3 Eye Diagrams from Slot 7 to Slot 1 802
27.8 Summary and Conclusions 803
27.9 Exercises 804

Part 6 Emerging Protocols and Technologies 80'7

Chapter 28 Electrical Optical Circuit Board (EOCB) 809

28.1 The Photonic PCB Industry and Development Programs 809
28.2 Optoelectronic Printed Circuits Based on HDI-Microvia Technology 810
28.2.1 Benefits ofHDI 811
28 .2.2 Microvia Technologies 811
28.2.3 Use of Microvias in PCBs 812
Better Electrical PerforniancelSignal Integrity 812
Improved RF11EMIlESD 812
28.2.4 Photonics and Electrical Performance 812
28.3 Photonics and Waveguides 813
28.3.1 Optical Waveguide Materials 815
28.3.2 31) Fabrication Techniques 817
Terahertz Photonics' Truemode Back-plane 818
Electrical Optical Circuit Board 819
PolyGuide 821
Tppcat 823
28.33 New Components 824
28 .3 .4 3D Assembly Techniques 825
28.3 .5 NTT, University of Texas, and REP 825
28 .4 Conclusion 827
28.5 Exercises 828
XX%Iv Contents

Chapter 29 RapidlO 829

29.1 Rapidl0; The Interconnect Architecture for High-Performance
Embedded Systems 829
29.2 RapidlO Is Now an International Standard 830
29.3 Embedded System Development 830
29.3.1 Why RapidIO? 831
29.3.2 Interconnect Landscape 832
29.3.3 Where Will It Be Used? 833
29.3 .4 Philosophy 835
29.4 RapidlO Protocol Overview 836
29.4.1 Packets and Control Symbols 836
29.4.2 Packet Format 837
29.4.3 Transaction Formats and Types 838
29.4.4 Message Passing 839
29.4.5 Globally Shared Memory 840
29.4.6 Future Extensions 840
29.4.7 Flow Control 841
29.5 Physical interface 842
29.5.1 Parallel Electrical Interface 842
29.5.2 The Serial RapidIO Controller 843
29.5.3 Link Protocol 843
29.5 .4 Enhanced Flow Control 844
29.5 .5 PCS and PMA Layers 844
29.5.6 Electrical Interface 845
29.6 Maintenance and Error Management 845
29.6.1 Maintenance 845
29 .6.2 System Discovery 84.5
29.6 .3 Error Coverage 846
29 .6.4 Error Recovery 846
29 .7 Performance 846
29.7.1 Packet Structures 846
29 .7.2 Source Routing and Concurrency 847
29 .7 .3 Packet Overhead 847
29.7.4 Bandwidth 847
29.7.5 Operation Latency 849
29 .8 Summary 849
29.9 Exercises 849
Contents xxxv

Chapter 30 PCt Express and ExpressCard 851.

30.1 PCI Express as Next-Generation 1/0 851
30.2 PCI Express Architecture Overview 854
30.3 PCI Express Architecture 857
30.3.1 Physical Layer 857
30.3.2 Link Layer 858
30.3.3 Transaction Layer 859
30.3.4 Software Layers 859
30.3.5 Mechanical Form Factors 860
ExpressCard 860
30 .4 Development Timeline 862
34.5 Summary 862
30 .6 Exercises 862

Part 7 Lab and Test Instrumentation 865

Chapter 31 Electrical and Optical Test Equipment 867

31 .1 Oscilloscopes 868
31 .1.1 Classes of Oscilloscopes- Real-Time vs. Equivalent-Time 868
31 .1.2 Real-Time Oscilloscopes 868
31 .1 .3 Equivalent-Time Oscilloscopes 870
31 .2 Bit Error Ratio Testers (BERTs) 873
31 .3 Pulse Generators 876
31 .4 Jitter Analyzers 877
31 .5 Logic Analyzers 879
31 .6 Characterizing Optical Systems 880
31 .6.1 Optical Spectrum Analyzer (OSA) 880
31 .6.2 Photodetection Using Equivalent-Time Oscilloscope 881
31 .6.3 Optical Modulation Amplitude (OMA) and Extinction Ratio 882
31 .6.4 Power Meters 882
31 .6.5 Characterizing Fiber Properties 882
31 .6.6 Optical Receiver Sensitivity 882
31 .6.7 Optical Amplifiers 883
31 .6.8 Multi-Wavelength Meter 883
31 .6.9 Reference Receiver 884
31 .7 Test Equipment Specifications 885
31 .8 Exercises 885
 Contents

Acronyms 887
References 893
About the Author 908
Index 909