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• Pre-layout (LineSim):
• Post-layout (BoardSim):
... a great tool for emergencies when we found a problem in production ... It let me try a number
of solutions quickly... and reduce the time it took to get the fix done.... I proved the accuracy to
myself and others by comparing LineSim results to actual measured waveforms. Even our
consultant was so impressed that he bought it for himself.
- Technical Specialist/Manager, Fortune 500 Office Equipment Manufacturer
The rapid prototyping capabilities and ease-of-use of the tool (LineSim) allowed multiple
topologies to be tried and simulated ... Without this tool, the circuit would have failed in the lab,
and ... would not have been able to be corrected without a board re-spin. With the rising cost of
board re-spins and the need to shrink a product's time to market, it is essential that a tool of this
nature be employed ... in order to get new designs and upgrades right the first time.
- Hardware Engineer, Computer Systems Manufacturer
Introduction
Some designers assume that signal-integrity, crosstalk, and EMC analysis begin after a PCB is laid out. But
one of the HyperLynx tools — LineSim – allows you to consider all of these effects much earlier in the design
process, before layout even starts. Working at this early stage, you can develop constraints for PCB
placement and routing that will give you the greatest chance of producing a successful first-prototype board.
Why initiate signal-integrity, crosstalk, and EMC analysis early in the design process? Because, the
earlier you begin, the earlier you catch mistakes; and the sooner you catch mistakes, the less time and
money you spend fixing them. It's been estimated that it costs 10 times more to fix a mistake after PCB
layout than before, and another 10 times more to fix it after prototyping than before. That's a factor of 100
— in terms of real, total cost – you can save by starting early.
Why does LineSim work from a special "interconnect" or "transmission-line" schematic rather than
an ordinary PCB schematic? Because ordinary PCB schematics do not contain the physical information
needed for signal-integrity, crosstalk, GHz-level, and EMC analysis.
Consider a clock net on a PCB schematic: it is drawn as a "wire" that connects a driver IC to several
receiver ICs. However, the schematic tells nothing about how the "wire" is actually constructed. For
example, is it a simple PCB trace on a board's outer layer, or a more-complex trace that uses outer and
inner layers, and passes through one or more vias? These kinds of physical details determine how the
clock net behaves from a signal-integrity and EMC standpoint.
LineSim is optimized for efficient input of physical schematics, allowing easy what-if analysis. Circuit
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elements – transmission lines, ICs, and passive components – are added with a simple click of the mouse
button. Physical parameters – including coupled cross sections for transmission lines – are modeled by
right-clicking on any element.
1. On the File menu, select Open LineSim Schematic. A dialog box opens.
2. Double-click on the file name "Clock.tln". (Schematics drawn with the cell-based editor use the .TLN
extension.) The dialog box closes and a schematic appears in LineSim's editor.
The schematic is drawn vertically to fit better in LineSim's half window for this demo. The triangular symbol at
the top represents a driver IC. Next are two transmission-line symbols, one labeled as "microstrip" and one as
"stripline." In the middle and at the bottom are more triangular symbols, representing receiver ICs. Together,
these make up a schematic of a simple clock net with a driver IC, a PCB trace routed on a board's outer layer
(the "microstrip") to a receiver IC, and a trace routed on an inner layer (the "stripline") to another receiver.
In a moment, we'll see how this schematic was drawn. But first, let's run a quick simulation to see how this
hypothetical daisy-chained clock net would behave if you actually built it on a board.
1. On the Simulate menu, select Run Interactive Simulation. The Digital Oscilloscope dialog box opens; you
can increase its size by dragging its corners with the mouse.
2. In the Driver Waveform area, select the Oscillator radio button.
3. In the MHz box, type "50".
4. In the Horizontal Scale area, click the up arrow button twice to change the timebase to 5 nsec/div.
5. Click the Start Simulation button.
Unless your computer is quite slow, the simulation should take only a few seconds or so to complete.
The waveforms on the screen are the actual voltages you'd see if you built the clock net described on the
schematic. Notice that the voltages at the receiver ICs (the yellow and purple oscilloscope traces) show a
large amount of overshoot / undershoot – so much that the receiver ICs "see" at least one extra clock edge
per cycle. To view this problem more clearly, let’s plot the receiver ICs' thresholds in the oscilloscope.
Display a receiver’s threshold by choosing component U(A1) in the Thresholds For combo box:
z In the oscilloscope, pull down the Threshold For combo box and select component U(A1).
Notice that two dashed, dark blue horizontal lines appear in the oscilloscope; these are the receiver ICs’ 0.8-V
and 2.0-V input thresholds (Vil and Vih). (They were read automatically by LineSim from the receiver’s IC
models.) Sure enough, the falling-edge waveform crosses the Vil threshold three times, which could cause
double-clocking. (If you built this clock net, your board would probably fail.)
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Also, there is considerable high-frequency content in the waveform; that is a likely source of serious EMC
trouble (more on that later).
This demonstrates how schematics are created in LineSim’s fast, cell-based editor:
z left-click on grayed-out elements (transmission lines, ICs, terminating components) to activate them and
add them to the schematic
z right-click on an element to model its physical characteristics (select an IC model, specify an impedance,
change a value, and so forth)
Notice how fast this is: there are no symbols to select and even no wiring to perform.
The 50-ohm value for the terminating resistor is a guess based on the fact that a terminator should match the
impedance of the transmission line it's terminating (note that the second line in the schematic has an
impedance of about 50 ohms). The capacitor value is also a guess; generally, the longer the line being
terminated, the larger the capacitor should be. (Later, we'll see how LineSim can automatically find the best
terminating-component values, so you don't have to make guesses.)
About modeling transmission lines and ICs: If you want more information about modeling transmission
lines (as PCB cross sections, as part of a stackup, with connector models, etc.) or modeling ICs, click one
of the topics below.
- Click here for more information on how transmission lines are modeled (cross sections, stackups,
connectors).
- Click here for more information on how IC drivers and receivers are modeled.
1. Since you edited the schematic, it can't be simulated in the demo version of LineSim. Instead, on the File
menu, select Open LineSim Schematic. A dialog box opens.
2. Double-click on the file name "Clockfix.tln". The dialog box closes and a schematic identical to the one
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This time, the receiver ICs' waveforms (yellow and purple) look considerably better: almost all of the
overshoot is gone. By increasing the capacitor's value, you could further "tune" the waveform to eliminate all
of the negative overshoot – this is one of LineSim's strengths: how easy it is to perform "what-if" analysis. But
let's look at another circuit, and in the process, find out about an even easier way to determine optimal
termination values.
On this net, an IC – modeled with an IBIS model – drives a transmission line and receiver IC. (Scroll the
schematic to the right to see the receiver, if needed.) The driver is series-terminated with a resistor, whose
value is temporarily 0.0 ohms.
Simulate the net with the 0-ohm resistor; set the IBIS model to Slow-Weak:
The simulator runs, showing what the falling-edge signal on this net would look like: it has very little ringing.
IBIS models can include min/typ/max data; let's change the model to run with best-case-fast/strong
parameters.
Re-simulate with the 0-ohm resistor, but change the IBIS model to run Fast-Strong:
The simulation runs again, plotting over the previous simulation's results. Note how the waveform has
changed: now there is considerable ringing. We need to terminate this net to protect against the faster
versions of our driver IC.
1. On the Wizards menu, click Run Terminator Wizard. A dialog box opens.
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2. In the Select a Device Pin list box, double-click U(A0). The dialog box closes, and the Terminator Wizard
opens and performs its analysis. It is recommending a 28.1-ohm terminating resistor.
3. "Apply" the Wizard's recommendation to the resistor in the schematic by clicking the Apply Values button
(upper right corner).
4. Close the Terminator Wizard by clicking OK.
When you run the Terminator Wizard, LineSim automatically analyzes the selected net, presents a list of trace
statistics, and, at the bottom of the list, makes suggestions for termination values. In this case, the Wizard
correctly determines that the termination type is "series," and makes suggestions for the optimum value of R.
In these calculations, LineSim automatically accounts for such effects as capacitive loading of receiver ICs,
total line length, and driver impedance.
In the schematic editor, notice that, because we clicked the Apply button, the resistor has changed from 0
ohms to the Terminator Wizard's recommended value of 28 ohms. Now let's simulate to see if the terminator
works.
Re-simulate the net; then reset the oscilloscope to 'Typical' IC modeling:
Note how dramatically improved the waveform is. At the receiver (yellow trace), the signal is nearly perfect. By
allowing just a small amount of undershoot at the receiver, the Terminator Wizard has achieved the least
possible delay to the receiver IC, yet ensured that the receiver's low-side clamp diode is not turned on.
The Terminator Wizard is a sophisticated tool. For example, in the analysis you just ran, it automatically
determined the following information (all displayed in the Wizard dialog box):
- switching impedance of the driver IC (average of high-side and low-side values)
- driver slew time (again, average of high and low)
- total net physical length
- nominal characteristic impedance of the net
- adjusted, "effective" impedance of the net, given receiver-IC loading
- what kind of terminator (e.g., series, parallel AC, etc.) you're using
- topology of the net, so that the Wizard knows what termination style to recommend if no terminator is
present
- driver-to-series-resistor stub length, in case the distance is too long
- the optimal termination value to use, given all of the above
Note: If you run an EMC analysis on this schematic, you won't get any radiation because the transmission
line is modeled non-physically as a "simple" line. LineSim's EMC-analysis engine must have physical data
about a transmission line (e.g., where it is in a PCB's stackup) in order to calculate radiation.
About EMC-Analysis Tools: EMC-analysis software is roughly divided into two categories – back-end,
system-level verification tools and front-end, what-if design tools. Verification tools, because they attempt
to perform system-level simulations, are so modeling-intensive and cumbersome that they tend to be
impractical. LineSim is a front-end design tool that's easy to run and attacks EMC problems early in the
design cycle.
1. On the File menu, select Open LineSim Schematic. A dialog box opens.
2. Double-click on the file name "Clock.tln". The dialog box closes and the original version of the clock net –
without a terminator – appears in the editor.
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Then, simulate the net to find its radiation profile, using Simulate > Run Interactive EMC Simulation.
First, set up the EMC-analysis probe, using the Set button:
1. On the Simulate menu, select Run Interactive EMC Simulation. The Spectrum Analyzer dialog box opens;
you can increase its size by dragging its corners with the mouse.
2. In the Probe area, click the Set button. The Set Spectrum Analyzer Probing dialog box opens.
At this point, we have a decision to make. EMC behavior can be investigated by predicting the net's far-field
radiation, or simply by probing its trace current directly and viewing the current in the frequency domain. Use
of a current probe is especially appropriate in LineSim, because radiation prediction requires physical detail
which is sometimes missing in a LineSim schematic: it's not possible to predict radiation from a purely
electrical transmission line, for example (radiation algorithms require detailed stackup knowledge). But
LineSim can always collect trace-current data, no matter how you construct your schematic.
Note: Some EMC experts always prefer dealing just with trace currents, rather than radiation predictions.
HyperLynx's radiation algorithm is powerful, but it is admittedly not able to account for the effects of
attached cables, the product's enclosure, etc. By concentrating on just the frequency content of a net's
currents – which LineSim can predict with high accuracy – you can very effectively manage your EMC
problems.
1. In the Probe Type area, notice that both antenna and current probes are available. Select the Current
radio button. Most controls in the dialog box gray out.
2. In the Pins list box, double-click on pin U(A0). The dialog box closes.
1. In the spectrum analyzer, verify that the Vertical Offset is set to 100 mA.
2. Click the Start Simulation button.
The simulation runs. The spectrum analyzer works first in the time domain, collecting data, then runs an FFT
to transform the current waveform into the frequency domain.
1. On the File menu, select Open LineSim Schematic. A dialog box opens.
2. Double-click on the file name "Clockfix.tln". The dialog box closes and the fixed version of the clock net –
with the terminator added – appears in the editor.
Then, simulate the net to find its EMC profile, using Simulate > Run Interactive EMC Simulation:
1. On the Simulate menu, select Run Interactive EMC Simulation. The Spectrum Analyzer dialog box opens.
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2. In the Probe area, click the Set button. A dialog box opens.
3. In the Probe Type area, verify that the Current radio button is selected.
4. In the Pins list box, double-click on pin U(A0). The dialog box closes.
5. In the spectrum analyzer, set the Vertical Offset to 100 mA.
6. Click the Start Simulation button.
Notice that the clock net's peak current level is now substantially improved: reduced in fact, by approximately
half. (It may look at first glance like less than half, but note that the vertical scale is logarithmic.) This net will
therefore radiate substantially less than the unterminated version. Notice that we've made this improvement
even before PCB layout: a proactive way of treating EMC problems that catches problems early in the design
cycle and significantly reduces the likelihood of certification failure and redesign downstream. Notice also the
connection between good signal-integrity and EMC design: the same termination improved both the signal
quality and EMC behavior.
1. On LineSim's File menu, select Open LineSim Schematic. A dialog box opens.
2. Double-click on the file name "DDR_4DIMM_data_min.ffs". The dialog box closes and a schematic
appears in LineSim's free-form editor.
Note: Running half-screen in the demonstration version, the details of the schematic are difficult to see
(because the schematic automatically fits to the screen width). If you wish, you can use the View > Zoom
Area In menu command to zoom into the schematic and see it in more detail. However, this is not
necessary, and the instructions below are written assuming that you stay at the present zoom level.
Note the difference between this editor and the one you saw in earlier examples. The free-form editor
functions more like a “standard” schematic tool: you choose symbols from a palette, and wire them together.
This technique tends to work better for large or complex designs. But otherwise, there’s not much difference
between the two editors: all of the associated dialog boxes (for modeling transmission line or ICs, for
example) are identical.
The schematic we’ve loaded represents a typical topology for a DDR data path, implemented in LineSim’s
free-form schematic editor. (The schematic was drawn so that the entire design fits on a single page, but it
could just have easily been “stretched” out to fit on multiple screens.) The DDR bus could be run at various
speeds, but we’ll try to make it work at 266 Mbs (133 MHz). The design is based on the minimum interconnect
lengths allowed by the JEDEC spec; trace widths and stackup have been designed to give the desired
impedances.
Looking from left-to-right, the design incorporates these elements:
z A DDR controller, represented by an IBIS model for a Xilinx Virtex-4 SSTL2 driver
z Several transmission lines representing extra package parasitics (recommended by Xilinx in their IBIS
model), breakout routing, and routing to the first DIMM module; plus a series termination resistor just after
the breakout
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1. On the Simulate menu, select Attach Scope Probes. A dialog box opens.
2. In the Pins list, locate pin “controller.dqs”, then double-click on it; a probe is attached. Repeat for pins
“dimm1.front”, “dimm2.front”, “dimm3.front”, and “dimm4.front”. Then click OK to close the probing dialog
box. In the schematic, notice that a colored probe has appeared at each selected pin.
3. On the Simulate menu, select Run Interactive Simulation. The oscilloscope dialog box opens.
4. In the Driver Waveform area, click the Oscillator radio button. In the MHz box, type “133”. In the IC Model
area, verify that the Typical radio button is selected.
5. In the Horizontal Scale area, click the up arrow once to set the scale to 2 ns/div. In the Vertical Scale
area, click the down arrow once to set the scale to 500 mV/div.
6. In the Threshold For combo box, choose pin “dimm1.back”. The receivers’ Vil and Vih threshold values
are plotted in the oscilloscope display, as dashed blue lines.
7. Then click the Start Simulation button to begin simulating.
The resulting waveforms show a problem: at the left-most of the DIMMs (yellow waveform), there is a
noticeable anti-reflection that causes DIMM 1’s received signal to dip back slightly above the high threshold.
This means that there is at least a possibility that DIMM 1 would get double-clocked. Some versions of this
design would fail in the field.
1. Minimize the oscilloscope by clicking its minimize button (in the upper right corner: “–“).
2. In the schematic, point to the pull-up resistor (at the far right edge), and right-click with the mouse. On the
pop-up menu, select Edit Value and Parasitics. The Edit Resistor Values dialog box opens.
3. In the Resistance box, type “22”. Then click OK.
4. Find the minimized oscilloscope, and click on its restore button (“double boxes”); the oscilloscope re-
appears. Click the Erase button to clear the old waveforms.
5. Click Start Simulation to re-simulate. New waveforms appear.
Notice that the rising edge waveform is now OK: the ringback at DIMM 1 (yellow waveform) is well above the
Vih threshold. It is still marginal, though, on the falling edge (versus Vil).
To improve the falling edge, recall that the schematic uses the minimum possible interconnect lengths (per
the JEDEC spec). Sometimes, it actually helps to increase routing length. Let’s see if that’s true in this case.
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Right-click on the three transmission lines that represent the routing between DIMMs 1-2, 2-3, and 3-4;
increase each line’s length to 1.2 inches:
Success! We’ve made the signal quality on all receivers on the DDR data bus “clean” enough to work reliably.
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z accurately predict how much crosstalk will occur when two or more PCB traces are routed near each other
z efficiently specify maximum parallelism, minimum line separation, and other routing constraints
z see the effects on crosstalk waveforms of trace separation; trace width; dielectric thickness; driver-IC edge
rate and impedance; parallel run length; and so forth
z confidently design high-speed buses that meet tight timing and low-crosstalk-noise requirements
z learn the difference between forward and backward crosstalk, and develop an intuitive sense of when
crosstalk occurs and how to minimize it
z implement resistor-termination strategies that can greatly reduce or eliminate end-of-the-line crosstalk
A key technical element of LineSim's ability to analyze coupled transmission lines is its fast, built-in boundary-
element field solver. In one of the examples below, you'll have the opportunity to explore a few of the solver's
features in detail.
z Accurately simulate differential signals, taking full account of the coupling between traces
z Explore termination options for differential signals, and determine when a single line-to-line resistor is
sufficient or when a full "array" termination is required
LineSim also offers features that make it easy to plan for targeted differential impedance. This happens
mostly in the stackup editor; to see an example of differential-Z0 planning, click here.
In the following sections, we'll look at some examples of how LineSim's crosstalk-analysis option can make
preventing crosstalk and designing differential signals easier.
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1. On LineSim's File menu, select Open LineSim Schematic. A dialog box opens.
2. Double-click on the file name "XT_Trace_Separation.ffs". The dialog box closes and a schematic appears
in LineSim's free-form editor.
In the schematic, the three transmission lines represent the side-by-side traces on the bus described above.
The triangular IC-driver symbols at the left end of each line show that all three traces are being driven from
the left side. Each line also has a receiver IC at its right end. The ICs are modeled with a generic 3.3-V fast
CMOS model from the HyperLynx-supplied library “EASY.MOD.”
1. Point to any of the left-end driver-IC symbols in the schematic. Double-click on the symbol; the Assign
Models dialog box opens.
2. In the Pins list, highlight IC pin U1.1 by clicking once on it. Look in the Buffer Settings area to the right and
note that this pin (the driver IC on the uppermost trace) has been set to be an "Output," meaning that it
will switch high/low or low/high when simulation runs.
3. Similarly, in the Pins list box, highlight pin U1.3 (third in the list). It is also set as an "Output."
4. Now highlight pin U1.2. This is the driver on the middle trace. Notice in the Buffer Settings area that it has
been set to "Stuck Low." This means that it will NOT switch when simulation is run.
5. Click OK to close the dialog box. Back in the schematic editor, note that middle-trace driver has a "0" near
its symbol, indicating visually that it is "stuck low."
The reason that the driver ICs are set up this way (middle trace "stuck low" and outer traces switching) is that
we want the middle signal to be the "victim" in our analysis and the outer signals the "aggressors," i.e., we
want to see how much crosstalk develops on the middle trace when its neighboring traces switch. But notice
that we didn't leave the middle trace completely undriven; rather, we applied a driver-IC model, but held it in a
static state. Modeling driver ICs on victim traces is very important, since low-impedance drivers reflect rather
than absorb crosstalk energy.
About "victims" and "aggressors": LineSim will simulate any mixture of "victim" and "aggressor" traces -
in fact, the simulator makes no distinction between the two. Generally, you would refer to traces which are
actively switching as "aggressors" and those on which you're trying to observe the resulting crosstalk as
"victims." In this simulation, we could just as well have made the middle trace also switch, in which case it
would have been both an aggressor to the other traces AND their victim.
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1. Point to any of the transmission lines in the schematic, and right-click with the mouse. A menu appears.
2. Select Edit Type and Values. The Edit Transmission Line dialog box opens.
3. Click on the Edit Coupling Regions tab.
4. Notice how the dialog box allows you to completely define the coupling region's geometry. The Coupling
Regions list box (on the left) shows a "tree list" of the region's stackup layers and transmission lines, and
a graphical view of the current definition. The various edit boxes on the right let you change geometric
parameters for the currently highlighted trace (or in some cases, globally for the entire region). The
Impedance list box (lower right) gives a summary of the resulting electrical characteristics (much more
electrical data is available elsewhere; see below).
Before we actually make any changes to the coupling region, let's run a simulation to see how much crosstalk
occurs with the current arrangement. (Perhaps our design goal of no more than 300 mV of crosstalk voltage is
already satisfied.)
Run a Simulation with Existing Coupling to See How Much Crosstalk Occurs
Simulate the existing schematic and coupling region using Simulate > Run Interactive Simulation; set the
oscilloscope timebase to 2 nsec/div, and simulate once with a falling edge and once with rising:
The green and yellow waveforms show the crosstalk voltages on the middle, "victim" trace, at the receiver and
driver ends, respectively. That the yellow waveform hardly moves is no surprise, since this end of the line is
held low by a low-impedance CMOS driver. But the situation is very different at the green, receiver end: there
is more than 1V of crosstalk when the aggressor signals are driving high. (To see which waveforms
correspond to which driver edge, in the Display area, toggle the Previous Results check box on and off; the
waveform that persists is for the rising-edge simulation.) >1V is well above our design criterion of 300 mV
maximum crosstalk.
When we simulated, LineSim ran its built-in boundary-element field solver to convert all of the geometric data
we entered into electromagnetic coupling parameters. In this example, we won't look specifically at the results
generated by the field solver (though they are always available in the Edit Transmission Line dialog box's
Field Solver tab, by clicking the View button). Later, in a differential-pair example, we'll look at the solver's
output in detail.
Note: It is the backward-crosstalk pulse reflecting off the victim line's driver IC that generates the 1-V
problem. With a little experience using LineSim, you will be able to comfortably distinguish forward
crosstalk from backward. Backward crosstalk persists for twice the delay length of the aggressor net that
creates it (compare the length in time of the pulses in the green waveform to the transmission-line delay
reported in the schematic).
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1. Point to any of the transmission lines in the schematic (you don't need to close the oscilloscope first), and
right-click with the mouse and select Edit Type and Values to re-open the Edit Transmission Line dialog
box.
2. Click on the Edit Coupling Regions tab.
3. In the Coupling Regions list box, highlight the middle trace. There are two ways to do this: either click
once on transmission line "TL2" in the tree list; or carefully point to the middle trace in the graphical
viewer, and click.
4. In the Trace-to-Trace Separation area, in both the Left and Right edit boxes, type "12" to increase the
separation from the aggressor traces. The separations become wider in the graphical viewer.
5. Click OK to close the dialog box, then back in the oscilloscope, click the Start Simulation button.
Notice that the maximum crosstalk (green waveform) has indeed been reduced, but only to about 750 mV, still
well above the acceptable level.
Now the maximum crosstalk at the victim trace's receiver end (green waveform) is sharply reduced, to about
280 mV. This meets our design goal, with a little margin to spare.
In general, crosstalk is a complex effect that is influenced by many different factors: e.g., driver-IC technology,
trace separation, trace width, line length, line-end termination (crosstalk generally requires more-complex
termination than single-line reflections), and PCB stackup (layer ordering and dielectric thickness/material).
LineSim lets you rapidly explore many different options to see which combinations most effectively meet your
requirements.
One of the most powerful uses for LineSim is the development of routing guidelines and constraints. For
example, in this case, we now know that the routing for this bus must be set to a minimum trace separation of
12 mils. We also have a stackup constraint: we know that two of our dielectrics need to be 5 mils thick.
Differential-Trace Example
Differential signaling is a technology that actually takes advantage of the coupling between neighboring
traces. When you design a differential pair, you often deliberately couple the two traces together fairly
strongly, so that any signal induced by external noise on one is also induced on the other – and then rejected
by the differential receiver at the ends of the lines.
However, differential-pair design involves non-trivial issues like determining what geometries to pick to
achieve a specific differential impedance. Terminating differential traces can also sometimes be challenging.
LineSim's crosstalk option is a powerful tool for differential-signal applications, because of the built-in
boundary-element field solver. The field solver automatically calculates differential impedances, determines
coupling parameters, and suggests termination values.
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impedance targets. There are several ways LineSim can help you plan for differential impedances. For
example, when you enter a differential trace pair in LineSim's schematic editor, LineSim immediately makes
the pair's differential impedance available to you. Let's see an example.
1. On LineSim's File menu, select Open LineSim Schematic. A dialog box opens.
2. Double-click on the file name "XT_Coupled_Differential.ffs". The dialog box closes and a schematic
appears in LineSim's editor.
The schematic contains two transmission lines; they are coupled together, as you can see by the dashed rat's
nest line between them. At the left end of the lines is a differential driver IC; here, we're using a high-speed,
low-swing LVDS driver pair (whose total swing voltage is about 400 mV). At the right line ends is a differential
receiver. The line’s receiver ends have been terminated with a 100-ohm differential resistor.
The circuit is set up to run differentially because one of the drivers has its polarity inverted relative to the
other.
Look at how the driver IC is are set up in the Assign Models dialog box; note that pin U1.2 is inverted:
1. Point to the driver-IC symbol in the schematic, and double-click. The Assign Models dialog box opens.
2. In the Pins list, highlight IC pin U1.3 by clicking once on it. Look in the Buffer Settings area to the right and
note that this pin (the lower of the two pins in the schematic) is set to "Output Inverted." This makes it
switch oppositely versus the upper pin.
3. Click OK to close the dialog box.
Suppose our design goal (perhaps specified by the driver-IC manufacturer) is to achieve a 100-ohm
differential impedance with our trace pair. (The differential terminator has already been set to this value.) Let's
see how we can use LineSim to plan for this.
LineSim makes it easy to find the differential impedance of any two-trace coupling region – the value is
calculated automatically. This calculation is performed by LineSim's built-in boundary-element field solver, an
"engine" that can accurately and quickly determine the electromagnetic parameters of any PCB cross section.
Check the differential impedance in the Edit Coupling Regions dialog box, in the Impedance area:
1. Point to either of the transmission lines in the schematic; right-click with the mouse and select Edit Type
and Values.The Edit Transmission Line dialog box opens.
2. Click on the Edit Coupling Regions tab.
3. In the Impedance area (in the lower right corner), look for the entry "(Differential)". This gives the
differential impedance, for the current geometric properties of the coupling-region cross section.
The line-to-line differential impedance is currently 124 ohms, considerably higher than the design goal of 100
ohms.
Note: In the following sections, we'll adjust the differential impedance interactively to achieve our goal of
100 ohms. There's another way to solve for differential impedances, in LineSim's stackup editor. We'll see
details in a later section covering the stackup editor, or click here now.
z In the Trace-to-Trace Separation area, in either the Left or Right box (whichever one is not grayed out),
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type "6" to decrease the separation of the traces; press <Enter> to “accept” the value.
Notice that the differential impedance has dropped to 114, better than before, but still too high.
1. In the Edit Transmission Lines dialog box, click the Edit Stackup button. The stackup editor opens.
2. Verify that the Basic tab is selected.
3. In row 3 of the spreadsheet, click in the Thickness column and type to change the value to "5". Press
<Enter> or click some other cell in the spreadsheet to accept the new value.
4. Verify in the graphical stackup view that the top-most dielectric layer displays as 5 mils thick. Then click
OK to close the editor.
5. Back in the Edit Transmission Lines dialog box, check the new differential-impedance value in the
Impedance area.
The differential impedance is now reduced to 98 ohms. This is very close to our design goal.
1. With the Edit Coupling Regions tab still open and selected, click the Field Solver tab.
2. In the Numerical Results area, click the View button. A report file opens in the HyperLynx File Editor.
z Impedance and Termination Summary - gives a detailed list of possible termination values to use for the
differential pair
z Physical Input Data - records the cross section that was analyzed, for future reference
z Field-Solver Output Data - gives the detailed electrical characteristics of the cross section, including
characteristic-impedance matrix, capacitance matrix, inductance matrix, and propagation speeds
You can also plot the field lines calculated by the field solver (to help give you a feel for how a cross section is
coupled, or just for fun).
Close the File Editor, then set the Propagation mode to Differential and plot the cross section's field lines by
clicking the Start button:
1. Close the File Editor by selecting Exit from its File menu.
2. In the Edit Transmission Line dialog box, in the Field Plotting area, verify that the selection in the
Propagation Mode combo box is Differential.
3. Click the Start button.
The field solver plots the field lines it has calculated. Electric-field lines are shown in blue, and electric
equipotentials are displayed in red. The plot assumes opposed, differential currents in the two traces.
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Waveforms appear, showing the signals in several different ways. (Remember that LVDS drivers have an
approximately 400-mV total swing.) The red, purple, yellow, and blue waveforms are taken with single-ended
oscilloscope probes, at the two driver and two receiver pins. The green and orange waveforms are from
differential probes, one at the driver and one at the receiver. LineSim allows any probe to be single-ended or
differential – your choice.
Click here to continue with the front-to-back HyperLynx demonstration; next, we turn our attention to
advanced features intended specifically for analysis of SERDES and other GHz-level designs.
Click here to return to the main menu.
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Note: HyperLynx's main GHz-level features are lossy transmission-line simulation, advanced via
modeling, eye diagrams, integrated SPICE (HSPICE and Eldo) simulation, and Touchstone (S-
parameter) support. In this demonstration, we've chosen to show lossy simulation, eye diagrams, SPICE
simulations, and Touchstone modeling in this section, running in LineSim; and to show advanced via
modeling in a later section, running in BoardSim. If you want to look immediately at via modeling, click here
to jump to the BoardSim section. Note that all of these features are available in both LineSim and
BoardSim (except via modeling in LineSim, which is coming in a future version), so the division of features
across pre- and post-layout used in this demonstration is only for convenience.
Lossy Simulations
About Loss
As driver-IC switching times grow shorter, the frequency content of the resulting signals increases. Older-style
designs might have a fundamental frequency of, say, 133 MHz, and significant energy content at several
higher harmonics, but little content at or above 1 GHz. Gigabit-per-second designs, though, use very-high-
speed serialized bit streams that demand extremely sharp switching edges; those edges have harmonic
content well above the 1-GHz level.
As a result, physical effects – collectively called "loss" – that play only a minor role in traditional designs
become important in GHz-level designs; and simulators must include those effects in their results. The losses
that occur on PCBs are of two types: one is due to the resistance in the trace metal, and the other is due to
the lossy nature of the surrounding dielectric layers. (The FR-4 material used in typical PCB manufacturing is
particularly prone to loss, compared to other more-expensive types of dielectric.)
Both of these effects – usually known, respectively, as "skin effect" and "dielectric loss" – are complex to
simulate in the time domain because each is frequency dependent, meaning basically that each gets worse
as signal frequency increases. "Skin effect" refers to the fact that the current in a trace tends to crowd more
and more to the edges of the trace cross section as frequency increases; because there is more crowding at
higher frequencies, there is more resistance. Dielectric loss works similarly; the higher the signal frequency,
the higher the loss.
These two factors combine to change the shape of a signal launched at a driver IC as it travels down a trace:
higher-frequency components of a signal are attenuated more severely than lower, which tends to "soften" a
signal's shape and drop its amplitude. Shape changes also result from the fact the different frequencies
propagate at different speeds. The sum total of these lossy effects changes what a signal at the end of a PCB
trace looks like compared to when it was launched by a driver. This in turn means that timing and other critical
signal-quality factors are significantly altered by loss. In SERDES-based systems, it is not uncommon for
signals to be attenuated greatly before arriving at receiver ICs.
Note: To simulate loss, HyperLynx uses the well-known and trusted “W-element” algorithm (although with
some added improvements).
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1. On LineSim's File menu, select Open LineSim Schematic. A dialog box opens.
2. Double-click on the file name "Lossy.ffs". The dialog box closes and a schematic appears in LineSim's
editor.
The schematic is very simple: a driver IC, 20 inches of transmission line buried in FR-4 on a PCB's inner
layer, and a receiver IC. The ICs were modeled for simplicity with the fastest driver in the EASY.MOD library:
a generic 3.3-V CMOS driver with a nominal switching time of 300 ps. (Many SERDES-type drivers have even
faster edges.)
1. On the Simulate menu, select Run Interactive Simulation. The Digital Oscilloscope dialog box opens.
2. On LineSim's main menu bar, select Lossy and verify that Enable Lossy Simulation is not enabled.
3. Back in the oscilloscope, in the IC Modeling area, select the Fast-Strong radio button. (This will give us
the fastest possible edge time for this driver, which should show the most loss.)
4. Click the Start Simulation button.
In the oscilloscope display, note a sharp driver waveform in red, and after a time delay corresponding to the
20 inches of trace length, a similarly sharp receiver waveform in yellow.
1. On LineSim's Lossy menu, select Enable Lossy Simulation. Notice on the toolbar that a button with an
attenuating blue waveform is depressed, indicating that loss is enabled.
2. In the oscilloscope, click the Start Simulation button again.
The new waveform at the receiver (in yellow) – generated with lossy analysis turned on – does indeed look
different than the previous, lossless waveform: it is delayed compared to and has less amplitude than its
predecessor. If the switching edge were even faster, or the trace longer, or the PCB's dielectric material
lossier, the effect would be even stronger.
Look also at the red driver waveform, just past time 7 ns (toward the right side of the display). The disturbance
in the waveform is due to a reflection from the receiver IC's input capacitance. Note how much less severe
(i.e., how attenuated) it is in the lossy simulation versus in the lossless.
Note: Actually, a few conditions must be met for frequency-domain loss information to be available. First,
the transmission line must be modeled with a "style" that's tied to a PCB stackup or cross section (because
prediction of loss is based on knowledge of cross-section geometry and materials). Second, lossy analysis
must be enabled.
Let's view the loss associated with the 20-inch transmission line in the current schematic.
View the transmission line's loss by right-clicking on it and selecting the Loss tab:
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1. Look for the area in the lower right of the loss graph, where the red and green curves intersect.
2. Use the mouse to click and drag a rectangular area around the intersection point.
3. Release the mouse; the graph is zoomed to the area you specified.
Note that the green curve crosses over the red one a little above 700 MHz, meaning that at that frequency,
dielectric loss becomes more important than skin-effect loss.
Actually, there's an even easier way to find out where dielectric loss dominates: note the Dielectric Loss
Dominates At box at the bottom right of the dialog box. It automatically calculates at exactly what frequency
the crossover occurs.
Close the loss-viewer dialog box, and disable loss for later sections of the demonstration:
z "Raw" SPICE has a primitive, unfriendly user interface compared to tools like HyperLynx; much valuable
design time ends up being wasted on set-up
z SPICE interconnect netlists have to be created manually in a text editor; even for simple "what-if"
scenarios, this is time-consuming and error prone, while for post-route scenarios it's essentially impossible
z Field solutions to convert geometric cross sections into electrical parameters have to be generated
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manually; again this is error-prone, and impossible for complex interconnect scenarios which involve many
different cross sections
z Stimulus for an eye diagram has to be manually generated – again, a tedious and error-prone task
A better approach is to integrate the SPICE simulation engine into the robust, friendly HyperLynx
environment, an approach that offers the best of both worlds: you get the extra accuracy of running SPICE IC
models, and all the convenience and productivity of the HyperLynx environment.
In the following example, we'll see how a SPICE simulation is set up and run using HyperLynx.
Note: The dependency of high-speed designers on SPICE simulation may be temporary. In the past, all
digital buffers could be modeled accurately in the non-proprietary IBIS format. Now, some devices have
appeared which their vendors feel are more accurately represented in SPICE. However, very advanced
driver models currently in design reportedly have simplified analog characteristics (to enforce strict
linearity); there are early indications that IBIS modeling may once again suffice to capture the analog
behavior. Also, SERDES-type I/O's have increasingly large amounts of associated digital logic (to generate
pre-emphasized driver signals or implement receiver equalization circuits), which may have to be modeled
in mixed analog/digital languages like VHDL-AMS or Verilog-AMS – SPICE is unable to handle significant
amounts of digital logic.
Whatever the future holds, HyperLynx is committed to providing its customers with all of the analysis
engines required to handle relevant types of models.
1. If the schematic "Lossy.ffs" is already open from the previous section on "loss," go to the next step.
Or
If you jumped to this section from another topic, use File > Open LineSim Schematic; then double-click
"Lossy.ffs".
2. In the schematic, point to the driver-IC symbol (left end of the transmission line) with the mouse, and
double-click. The Assign Models dialog box opens.
3. In the Pins list, double-click on pin U1.1. The Select IC Model dialog box opens.
4. Select the SPICE radio button; the Files list shows only the two SPICE models shipped with the
demonstration software.
5. In the Files list, click once to highlight model Fast_Drv.sp.
6. In the Models list, double-click on model Fast_Drv to select it. The dialog box closes.
Now we're back in the Assign Models dialog box. Note that a small spreadsheet has appeared. The purpose
of the spreadsheet is to help you make connections to all of the "ports" on the SPICE model. (The model's
ports are its external connection points, e.g., for a stimulus waveform, for power supplies, for its output pins,
etc.).
This particular SPICE model has four ports: "Vin" (where the model expects to be stimulated), "Vout" (its
output pin, which should be connected in the schematic), and "Vcc" and "Gnd" (the model's power-supply
pins). Note that LineSim has automatically recognized the names "Vcc" and "Gnd" and guessed that they
should be connected to LineSim's built-in power supplies. (If a SPICE model had more-obscure supply
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1. In the port-mapping spreadsheet, in the Circuit Connection cell for the "Vin" port, click to open the combo-
box list of possible connections. The SPICE model's Vin port expects digital stimulus, so select the
"Stimulus" item in the list.
2. In the Circuit Connection cell for the "Vout" port, click to open the combo box. The Vout port is the pin on
the SPICE model that should be connected in the schematic, so scroll down and choose item "U1.1", the
driver-pin name in the schematic.
The SPICE driver model has now been assigned and completely hooked up. Next, let's assign and connect a
SPICE receiver model.
Note: An important difference between SPICE and IBIS IC models is that SPICE models have "explicit"
ports. This means that with a SPICE model, you're forced to manually connect power supplies, one or
more input stimulus pins, possibly some control pins (there weren't any in this example), and one or more
output pins. Compare this to using IBIS models: the input/stimulus, power-supply, and control pins are
"implicit" and LineSim can connect them automatically for you. This difference results because SPICE
models are inherently "lower level" than IBIS models. Fortunately, through its port-mapping spreadsheet,
LineSim (and BoardSim) makes it fairly easy to make and manage these extra connections.
1. In the Pins list, double-click on pin U2.1. The Select IC Model dialog box opens.
2. Select the SPICE radio button.
3. In the Files list, click once to highlight model Fast_Rcv.sp.
4. In the Models list, double-click on model Fast_Rcv to select it. The dialog box closes.
5. In the spreadsheet, in the Circuit Connection cell for the "Vin" port, click to open the combo box. The Vin
port is the pin on the SPICE model that should be connected in the schematic, so scroll to the bottom of
the list and choose item "U2.1", the receiver-pin name in the schematic.
We're done assigning and hooking up our SPICE models. Now let's look at how you'd run a SPICE simulation.
The message appears because LineSim has noticed that you're running with SPICE models, not IBIS models.
As a result, it wants to switch automatically to a SPICE simulator rather than "native” – HyperLynx simulator,
which is exactly what we want. Notice under the Start Simulation button that we could have changed the
radio-button setting and manually chosen Eldo. If you were an HSPICE rather than Eldo user, a one-time
Preferences change would re-label this radio button to “HSPICE.”
Click OK in the message box to open the Run Eldo Simulation dialog box; click OK to begin running the
SPICE simulator:
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1. Click OK to close the message box. The radio-button setting below the Start Simulation button changes
automatically to Eldo, and the Run Eldo Simulation dialog box opens.
2. The default settings in the dialog box are fine; click OK to run a SPICE simulation.
Again, we're not actually running SPICE in this demonstration. But if we were, the following steps would now
occur:
z LineSim would create a SPICE netlist (targeted to your choice of HSPICE or Eldo) representing the
schematic; the SPICE driver and receiver models would be included with all of the connections you made
in the port-mapping spreadsheet.
z For each transmission line in the schematic, LineSim would invoke the HyperLynx field solver to determine
its electrical characteristics, then write out the electrical data in HSPICE or Eldo matrix format. If lossy
analysis was enabled, the transmission-line data would include skin-effect and dielectric-loss parameters.
z If any Touchstone (S-parameter) models were in the schematic (there were none in this example), they
would be included in the netlist.
z LineSim would invoke HSPICE or Eldo on the netlist.
z Assuming a SPICE license were found, a window would open and HSPICE or Eldo would begin running in
it; all of the SPICE messages would be visible so that you could track its simulation progress in detail.
z If there were an error in one of the SPICE files – for example, a syntax error in one of the models we
assigned – then the SPICE window would automatically jump to the location of the first error message, for
convenience.
Since we're not actually running these steps in the demonstration, a message box opens instead.
Note: If you happen to be running this demonstration with the “real” (not demo) version of HyperLynx and
have Eldo installed, then Eldo will actually begin running on the schematic, and the detailed instructions in
this section won’t be followed. Also, Eldo will report a model error, since the models used in the schematic
are “phony” and don’t actually contain any transistor data.
We didn't run the SPICE simulation here, but the demonstration does include a real SPICE results file. Let's
make LineSim read it in.
In the message box, click OK; the demonstration software looks for a stored SPICE results file, reads it, and
presents the waveforms in the oscilloscope.
Note that the waveform behaves no differently than if it were generated by the native HyperLynx simulator:
you can scale it, scroll around in it, etc.
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Because the models are expressed in the frequency domain, they can’t be directly simulated in the time
domain like, say, an IBIS model. Fortunately, most SPICE simulators (including HSPICE and Eldo) can use
Touchstone models in transient simulation, using one of several possible techniques, the most-common being
“convolution.” A particular strength of the Eldo simulator is its ability to “fit” S-parameter models (using
complex poles), which has various advantages over simple convolution (model compression, speed,
passivation, and causality enforcement).
In the signal-integrity world, S-parameter models are by far the most-common type of Touchstone model in
use. One typical way of creating such models is by measurement, using a vector network analyzer, which
directly outputs S-parameter data. Another possibility is to model the structure using 3-D electromagnetic
software; these tools also typically output S parameters.
So far, we’ve placed an empty symbol on the schematic. It could actually be used to house any passive (non-
driving) SPICE or Touchstone model; in this case we’re going to assign a 4-port S-parameter model to it. The
model we’ll use is “phony”: it contains a valid “introductory” line, but no modeling data. For this demonstration,
though, it doesn’t matter, since we’re only looking at how Touchstone assignments are made.
Double-click on the package/connector symbol, and in the Assign Package / Connector Model dialog box,
choose model “Example.s4p”; move ports 2 and 4 to the right side of the symbol; then close the Assign
Package / Connector Model dialog box and wire the Touchstone symbol to the drivers and receivers:
1. Point with the mouse to the empty package/connector symbol, and double-click. The Assign Package /
Connector Model dialog box opens.
2. In the Model Type combo box, select Touchstone Models. Only one Touchstone file is shipped with the
demo software; verify that Example.s4p is highlighted in both the Libraries and Devices list boxes. Click
the OK button; the Assign Package / Connector Model dialog box closes.
3. In the schematic, the empty symbol has been replaced by one labeled “Example.s4p” and showing 4 ports
on its left side. Let’s assume that this model is arranged with two internal paths, one from port 1 to port 2,
and the other from port 3 and port 4. (Probably, the two interconnects are coupled to each other.)
4. Double-click the Touchstone symbol again. In the Assign Package / Connector Model dialog box, in the
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Side column for both port 2 and 4, click and select “right.” Then click OK.
5. Back in the schematic, note that the Touchstone symbol now has two ports on each side. (If the complete
port names are not displayed, touch each pin name with the mouse; a tool tip displays the full name.)
6. Finally, wire the IC-buffer symbols to the nearest ports. First, connect driver pin U1.1 to Touchstone port 1
by placing the mouse over the “dot” at U1.1 (note that the mouse cursor changes to a “cross”), then
dragging a wire from it to the connector’s port-1 dot, then releasing the mouse. Repeat to connect driver
pin U3.1 to port 3.
7. For variety, connect the remaining two wires in an alternate way: click on receiver symbol U2.1, and with
the mouse button held down, drag U2.1 until its pin dot touches port 2’s dot. Release the mouse button
briefly, then press it down again and drag U2.1 away from the Touchstone symbol; a wire appears
between the two symbols. Repeat to connect U4.1 to port 4.
If you complete all of the steps above correctly, your resulting schematic should look something like this:
At this point, if you were running a “real” copy of HyperLynx and had either the HSPICE or Eldo SPICE
simulators installed, you could immediately open the oscilloscope, and see the effects of driving the sample S-
parameter model. In this demonstration, we can’t actually do it. But the preceding example shows how easily
S-parameter (and other Touchstone) models are included in a LineSim free-form schematic.
Note: Actually, if you happen to be running this demonstration with the “real” (not demo) version of
HyperLynx and Eldo, then Eldo will actually begin running on the schematic, but end up reporting a model
error. The reason is that the model used in this example is “phony” and doesn’t actually contain any matrix
data.
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diagrams and multi-bit driving – are tightly linked, and we'll demonstrate them together in this section.
1. On LineSim’s File menu, select Open LineSim Schematic. A dialog box opens.
2. Double-click on the file name USB_link.ffs. The dialog box closes and a schematic appears in LineSim’s
free-form editor.
3. If the entire schematic doesn’t appear on the screen, then on the View menu, select Fit to Window. The
schematic zoom level automatically adjusts.
The schematic we’ve loaded represents a typical topology for a USB 2.0 implementation, implemented in
LineSim’s free-form schematic editor. Looking from left-to-right, the design incorporates these elements:
z A differential driver pair on a USB 2.0 host controller; the differential buffer is modeled using an IBIS model
from Cypress Semiconductor
z A pair of coupled transmission lines, representing the differential-pair routing from the host controller to a
ribbon cable
z A model of three side-by-side differential pairs in a 28-AWG ribbon cable, constructed by coupling six
transmission lines together in a single LineSim coupling region (for basic information on “coupling regions”
and how LineSim represents and simulates crosstalk, click here)
z Another pair of coupled transmission lines, representing more differential-pair trace routing between the
ribbon cable and a USB cable
z Another pair of coupled transmission lines, representing a 5-meter USB cable
z Another pair of coupled transmission lines, representing the routing in the USB peripheral device
z A differential receiver pair on a USB 2.0 peripheral controller, again modeled using a Cypress
Semiconductor IBIS model
Essentially, the system in this schematic consists of a USB host controller, linked through a ribbon cable (with
a short amount of differential-trace routing on each end) and 5-meter USB cable to a USB peripheral (with
routing and controller input pair). The interconnect lengths are “stressed” to the maximum delay lengths
allowed by the USB 2.0 specification. Will the design actually work? Let’s create an eye diagram, compare it
to the spec’s minimum allowed eye opening, and find out.
1. On the Simulate menu, select Run Interactive Simulation. The Digital Oscilloscope dialog box opens.
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2. In the oscilloscope, in the Operation area, select the Eye Diagram radio button.
3. In the Eye Diagram area, click the Configure button; the Configure Eye Diagram dialog box opens.
With a single radio-button click, we've told the oscilloscope to generate an eye diagram. But before we can
simulate, we have to tell LineSim’s simulator what bit sequence to drive down the differential pair. Fortunately,
this is easy to do in the dialog box that's now open.
The most common type of stimulus used in eye-diagram generation is the "PRBS" or "pseudo-random bit
sequence." However, some technology-specific specifications (like USB 2.0) prescribe their own worst-case
patterns. LineSim allows you to choose between several “built-in” patterns (some configurable, like PRBS
stimulus, for which you can set length, repetition count, starting state, etc.); or your own custom pattern. For
this case, LineSim has the worst-case USB 2.0 pattern built-in.
In the dialog box, choose the USB 2.0 Compliance pattern:
z In the Bit Pattern area, pull down the Sequence combo box, and select USB 2.0 Compliance.
Note that the graphical view updates to show the bit pattern that will be driven during simulation. The
sequence is 330 bits long (per the USB 2.0 specification); you can scroll the sequence viewer, if you want, to
see all of it.
We’re not quite finished specifying the stimulus. We still need to make choices about the length of each bit’s
interval, how many times (if any) to have the pattern repeat, whether to skip any bits at the beginning of the
pattern, and even the number of eyes to show. Also any real driver suffers from a certain amount of inherent
jitter, i.e., a certain amount of random uncertainty in the times at which switching edges are delivered relative
to each other. We can include this effect in our simulations by specifying a jitter percentage.
Set the bit interval to 2.08 ns and the sequence repetitions to 1; select to skip the first 20 bits of output; and
set the jitter to 6% of the bit interval:
1. In the Stimulus area, in the Bit Interval box, type “2.08”. In the Sequence Repetitions box, type (or select)
“1”.
2. In the Display area, in the Skip First box, type “20”. In the Show combo box, select “1”.
3. In the Random Jitter area, in the Amount box, type “6” (and verify that the associated combo box is set to
“% of interval”). Verify that the Distribution combo box is set to “Gaussian”.
With these steps, you’ve completely specified the eye diagram’s stimulus. However, before simulating, there
is another optional step that will make it easier to judge whether the resulting eye diagram is acceptable or
not. Eyes are judged by the extent of their “opening”; each SERDES technology typically specifies a minimum
allowed opening, which can be translated into an “eye mask” that visually defines a “keep-out” region. If a
given eye penetrates this region, then the eye fails to meet the spec’s minimum requirements for signal
quality. Even if the eye is open, the mask gives a quick visual impression of how much margin the eye has.
Similar to eye patterns, LineSim (and BoardSim) includes some built-in masks, and allow you to define your
own. Once again (since USB 2.0 is a common and important signaling technology), the mask we need is built
in to the HyperLynx mask library.
Switch to the Eye Mask tab, and choose the "USB2.0-High_Speed_RX" mask:
Now, the stimulus to create the eye diagram and the mask to judge its success are both ready. Let’s run a
simulation and see whether our USB topology will actually work.
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2. In the oscilloscope, in the Horizontal Scale area, click the down arrow button once to set the horizontal
scale to 500 ps/div.
3. In the Vertical Scale area, click the down arrow button twice to set the vertical scale to 200 mV/div.
4. In the Vertical Position area, in the box, type “-400”.
5. In the Horizontal Delay area, in the box, type “1.4”.
6. In the Show area, click the Eye Mask check box to enable it. A portion of a mask appears in the
oscilloscope’s viewer.
7. At the right edge of the oscilloscope’s viewer, drag the horizontal scroll bar down until a dashed green
ground line appears in the center of the viewer. Positioned symmetrically around the green line, you
should also see a six-sided blue shape that defines the eye mask’s keep-out region.
8. Then click the Attach Probes button. The Attach Oscilloscope Probes dialog box appears.
9. Verify that two differential probes (red and yellow) are set, one for the driver pin pair (Host.D+/-), and one
for the receiver (Device.D+/-).
0. Click OK to close the dialog box and return to the oscilloscope.
1. In the Show area, note that both the red and yellow probes are enabled. Since we’re interested in the eye
diagram only at the receiver IC, click the red probe’s check box to disable it.
2. Finally, before simulating, from LineSim’s main menu, on the Lossy menu, select Enable Lossy
Simulation. (This is essential to producing an accurate eye diagram.)
Now, generate the eye diagram: click the Start Simulation button.
It takes longer to generate an eye diagram than a regular single-edge simulation, since so many switching
edges have to be generated. Still, unless your computer is very slow, this 330-bit diagram builds at a
reasonable speed. Note that unlike SPICE and other analog simulation tools, LineSim does not make you wait
until the simulation is finished to see the results – instead, you actually see the eye diagram being built in real-
time. This is sometimes quite advantageous, because it makes it quick to see whether you’ve made an error
in your set-up; if so, you can stop the simulation immediately and not waste time on a “bad” simulation.
Note that this eye is fairly "open," indicating reasonable signal quality. To see this very clearly, you can center
the eye mask on the eye.
Click the Adjust Mask button, and drag the mask with the mouse until it is centered:
1. Below the oscilloscope display window, click the Adjust Mask button.
2. In the display window, place the mouse near the center of the mask’s keep-out region, then drag the mask
with the mouse button down, until the mask is reasonably centered in the eye.
Now you can see exactly how open your eye is compared to the USB 2.0’s requirements, and judge whether
your margin is sufficient.
Note how easy it was to generate a complex eye diagram: we switched the oscilloscope's mode, selected
some parameters (including a built-in stimulus pattern and eye mask), and clicked Start Simulation. After a
brief delay, we had an eye diagram to look at.
Although in this case we used IBIS models, you can use exactly the same procedures in LineSim or
BoardSim to drive a SPICE simulation. There, the set-up savings are tremendous: defining eye-diagram
stimulus (including jitter and bit-skipping) in a SPICE netlist is tedious and error-prone.
Click here to continue with the front-to-back HyperLynx demonstration; next, we look at how to plan
stackups and trace impedances.
Click here to return to the main menu.
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Note: In this demonstration version of HyperLynx, some of the parameters in the stackup editor cannot be
edited, for example dielectric constants. However, in spite of this limitation, you'll easily see in the following
examples how useful the stackup editor is as a planning tool.
First, note some of the features of the stackup editor. On the left, the data defining the stackup is entered in a
spreadsheet; each row of the spreadsheet represents one layer – metal or dielectric – in the stackup. On the
right is a graphical view, which visually summarizes the key data (like layer names and thicknesses) in the
stackup.
The complete set of data that makes up or affects a stackup is complex. To help you navigate this information
efficiently, the stackup editor uses a series of tabs to sub-divide the data. Let's take a quick look at what each
tab contains:
The Basic tab is the one you're looking at currently. It places the most commonly accessed data defining the
stackup in one convenient location. You can use this tab to set each layer's type (e.g., is it metal or dielectric?;
signal or plane,?; etc.); to change layer thicknesses; to set dielectric constants; and to find out the impedance
of each layer, for any trace width. You can also control the units of the stackup parameters (metric/English;
thickness/weight) from this tab. For basic design work, you may rarely need to access any tabs other than this
one.
Click on the Dielectric tab.
The Dielectric tab contains more-detailed information about the dielectric layers in your stackup. From here,
you can specify whether each dielectric layer is made of "core" or "prepreg" material, whether the dielectric
constant on metal layers should automatically be the same as that on surrounding dielectric layers or be
entered as a "custom" value, and what the loss tangent of each layer's dielectric material is. (Loss tangent
determines how much dielectric loss there is during lossy simulations.)
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1. In row 3 in the spreadsheet (the top-most dielectric layer), click in the Thickness column and type to
change the value to "5". Press <Enter> or click some other cell in the spreadsheet to tell the stackup
editor to accept the new value.
2. Note how the impedance value for signal layer 2 ("TOP") changes instantly from 73.1 ohms to 51.4 ohms.
The response from the field solver is instantaneous. Performing what-if changes like this in an interactive
spreadsheet tied directly to a field solver is much faster and less error-prone than calculating impedances with
approximate equations or reference charts.
Now click on the Z0 Planning tab; verify that the Plan For combo box is set to Single Trace:
This tab gives you an even faster and more powerful way of planning impedances. Note the Target Z0
column; in these cells you can specify a desired impedance for each signal layer. In this example, 75 ohms is
achieved on the bottom layer at about 7.5 mils width, and on the other signal layers at about 3.3 mils. Let's try
changing the target impedance to force a different geometric solution.
Change the target impedance of layer 2 to 50 ohms; note how quickly a new trace width is calculated:
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1. In row 2 of the spreadsheet, click in the Target Z0 column and type to change the value to "50". Press
<Enter> or click some other cell in the spreadsheet to tell the stackup editor to accept the new value.
2. Note how layer 2's value of Width changes instantly to about 8.4 mils, which is the trace width required on
this layer to match the new target Z0.
1. In the Plan For combo box in the stackup editor's bottom left, change the selection to Differential Pair.
Note that the title of the Target Z0 column changes to Diff Z0.
2. Verify that the Strategy combo box is set to Solve for Separation.
With these changes, the stackup editor now interprets the target Z0 values as the differential impedance of a
pair of traces. Setting the Strategy combo box to Solve for Separation means that the editor is solving for the
trace separation (or "gap") that, given the specified trace width, meets the target differential impedance.
For the inner signal layers, the solved-for separation value is about 4.5 mils. But what about for the outer
layers – the gap value reads "error." Is this a problem with the software? No! The stackup editor is telling you
that with the current stackup, differential impedances of 50 and 75 ohms are physically impossible on the
outer layers. If we had more time in this demonstration, we could change the geometry of the stackup to make
75 ohms physically possible (or we might want to target a higher differential impedance, like 100 ohms).
For differential pairs, you can also specify the separation and solve for trace width (the opposite of what we
just did), or most powerfully of all, solve for both separation and width simultaneously. Let's look at an
example of solving for both.
Change the impedance strategy using the Strategy combo box to Solve for Both; click layer 12's (BOTTOM's)
View button to display a curve of width-vs-separation for 75 ohms differential impedance:
1. In the Strategy combo box, change the selection to Solve for Both. The Width and Gap columns gray out
and View buttons appear in the Z0 Curve column for each layer.
2. In row 12 (layer BOTTOM), click the View button in the Curve column. After a few seconds of running the
field solver, a dialog box appears.
The resulting graph shows a curve of constant 75-ohm differential impedance (the target impedance for this
layer), allowing you to choose a range of either trace widths or separations, and read for each value the
corresponding other value. For example, the curve shows that at 5 mils separation, you need a trace about 17
mils wide to achieve 75 ohms differential impedance. You can see now why at our earlier trace width of 8
mils, 75 ohms differential Z0 was physically impossible: the trace separation would have been nearly zero to
achieve the target.
There are still many features in LineSim that we have not explored, but in the interest of time, let's see how
you'd analyze a simple PCB in the HyperLynx's post-layout analysis tool, BoardSim. This part of the
demonstration will show how BoardSim handles both interactive and batch-mode simulation. At the end of the
demo, you are welcome to explore any of the features we have not highlighted here.
Click here to continue with the front-to-back HyperLynx demonstration; next we move to a
demonstration of post-layout signal-integrity, crosstalk, EMC, and GHz-level analysis, using
BoardSim.
Click here to return to the main menu.
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Testing of our prototypes agreed with what we had seen using BoardSim and reaffirmed our
confidence that we had the best possible signal integrity solution. Board Wizard allowed me to
check the entire board in seconds by setting up parameter checks. It would have taken days to
check all the nets manually. The frequency response of components could be displayed allowing
easier selection of items such as ferrite beads. BoardSim provides all the information needed to
ensure a reliable board design and does so in an easy and intuitive manner.
- Hardware Engineer, Leading Avionics Manufacturer
...The risk of transmission line-induced faults on a board of this size easily justifies the purchase
price of this product.
- Engineer, Imaging System Manufacturer
I received my first pass of the routed 16 layer card ... and HyperLynx paid for itself in the first
four hours of use ... I'm very happy with both the product and the support.
- Hardware Engineer, Computer Systems Integrator
Introduction
If you started this demonstration at the beginning, you've already seen how LineSim can help you prevent
signal-integrity, crosstalk, EMC, and GHz-level SERDES problems even before you begin PCB layout. (Click
here if you want to go through the LineSim/pre-layout portion of the demo before reading this section.)
Using the data from your actual routed PCB layout, BoardSim moves HyperLynx's analysis into the post-
layout phase of your design cycle. Typically, BoardSim is used after placement and routing; the analysis is
based on the actual details of your board's routing. But you can also analyze a board as soon as it's placed,
before routing (using Manhattan routes that BoardSim creates); or when your board is placed and only
partially routed.
z Accel EDA
z Cadence Allegro
z Mentor Graphics Board Station
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Note that BoardSim may be able to interface to PCB-layout tools not listed above through the SPECCTRA (or
"CCT") format, since almost all PCB-layout tools can write a SPECCTRA DSN file.
For this portion of the demo, the .HYP file has already been created for you. It's called "Demo.hyp."
LineSim could have prevented many of the problems you're about to see! LineSim is an excellent tool
for solving signal-integrity, crosstalk, and EMC problems early in the design cycle, before you begin PCB
layout. Problems like those you're about to see on the demo PCB – for example, clock nets that are
improperly designed – can also be solved up-front, before time is invested in board layout.
However, other types of problems can only be found after PCB layout. For example, even a properly
designed net can be negatively affected by the layout process, e.g., if the trace's length is not constrained
properly during routing, or if the router can’t meet the constraint that was set, or if a net wanders through
too many vias. Also, it is sometimes difficult to pre-plan nets beyond the truly critical ones on a board.
Addressing these kinds of problems is the purpose of BoardSim.
1. If you previously ran the LineSim portion of the demo, close any open dialog boxes.
2. On the File menu, select Open BoardSim Board. A dialog box opens.
3. Double-click on the file Demo.hyp.
Since the demo board is small, loading takes only a few seconds. When loading is done, you see the board in
BoardSim's viewer.
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next section, the nets being analyzed will be shown in the foreground and other nets will “dim” into the
background.
1. On the Simulate menu, select Run Batch Simulation. The batch-mode “wizard” dialog box opens.
2. Set the check boxes on the wizard's first page as follows: the first six Quick Analysis check boxes
enabled, and the remainder disabled; both Detailed Simulations check boxes (near the top) disabled. This
will include the most-interesting information in the wizard's quick-analysis report, and leave detailed
simulations disabled for now.
3. Click Next twice, so that you move to the Batch-Mode Setup - Default IC Model Settings page.
4. In the Rise/Fall Time box, verify that the default switching time is set to 2 ns.
5. Click Next several more times, until the Batch-Mode – Run Simulation and Show Results page and the
Finish button appear. Click Finish.
Notice that we didn’t bother specifying specific IC models for the nets on the PCB; on the Default IC Model
Settings page, we told the batch engine to assume that any nets not yet populated with models have driver
ICs with approximately 2-ns switching times. (On this board, some nets do have models assigned, but others
don’t.) The ability to assign “default” IC characteristics allows you get results quickly, even before you make
detailed model assignments.
The batch wizard's quick analysis begins running, reporting its percent-done status as it analyzes the nets on
the board. Because the demo board is small, the wizard's analysis – even though it includes every net on the
board – takes only seconds to complete. The HyperLynx File Editor opens on the wizard’s output.
1. In the file viewer, click the yellow "Find Warning" button (yellow with a black checkmark). The viewer
jumps to the first location of the text "warning."
2. Click the Find Warning button several more times. The Viewer jumps to various nets that are likely to have
signal-integrity problems because they are physically long but have no termination, or that have non-
optimal terminating-component values.
You can use the batch wizard to automatically identify "problem" nets, and as a guide to further detailed
analysis and problem fixing.
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For example, look at the wizard's report for the net "datald":
1. In the file viewer, on the Edit menu, select Find. A dialog box opens.
2. In the Find What box, type "datald". Click to enable the Wrap Around Search check box.
3. Click the Find Next button.
The viewer jumps to net "datald's" section. Here the batch engine is reporting that "datald" has no terminator,
but given the default rise/fall time of 2 ns, "datald" is too long to be unterminated. The wizard gives a
suggestion for the maximum length of the net, if it remains unterminated.
Close the file viewer:
Note: For detailed simulation, the Board Wizard is capable of performing not only signal-integrity, but also
crosstalk and EMC analysis. In this example, we'll look at the signal-integrity features, and later in this
demonstration, at crosstalk features.
In general, there are two major reasons that designers run batch-mode signal-integrity simulations. One is to
find out what the min and max delays (or “flight times”) on a collection of nets are. This makes sense: digital
design is heavily centered on timing, and with today’s tighter margins, it’s important to include the effects of
interconnect delays in timing budgets. The second reason is to scan for other (non-timing) kinds of signal-
integrity trouble, for example, overshoot or crosstalk problems. (You can look for both types of issues
simultaneously using BoardSim’s batch feature.)
In the following sections, let’s simulate an example net, first with an eye to calculating accurate timing delays,
and then with a focus on non-timing signal-integrity issues.
Now we'll run the Terminator Wizard to automatically identify and apply optimal termination to improve the
signal integrity on net "datald."
Run the Terminator Wizard on it and apply the series resistor it recommends:
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1. On the Wizards menu, select Run Terminator Wizard. A dialog box opens.
2. Note that the wizard is recommending that a series terminator be added to the net, to improve signal
quality. In cases where a terminator is recommended but isn’t present in the routed design, the Terminator
Wizard can add the terminator "virtually,” with the appropriate component value. (BoardSim calls this a
“Quick Terminator.”) Add the terminator to “datald” by clicking the Apply Values button. Click OK to close
the wizard.
1. On the Simulate menu, select Run Batch Simulation. The batch-wizard dialog box opens.
2. On the first page of the Wizard, disable all of the Quick Analysis features (turn "off" their check boxes);
then in the Detailed Simulations area, enable the Run Signal-Integrity and Crosstalk Simulations check
box. (Leave the Run EMC Simulations check box disabled.) Click Next, so that you move to the Select
Nets and Constraints for Signal-Integrity Simulation page.
3. Click the SI Nets Spreadsheet button (in the upper left). This opens a spreadsheet in which you can select
nets for detailed signal-integrity analysis and set constraints for them. (You can re-size the spreadsheet, if
you wish, to make it bigger.)
4. All of the nets on the PCB are listed, in alphabetic order. Locate net “datald,” near the top of the list.
Enable simulation for this net by clicking once in its SI Enable column. When you make the selection, the
previously grayed-out columns turn white and “activate.”
5. For this net, we’re mostly interested in getting min/max interconnect delays in the batch feature’s output
report. The default rules for overshoot are a little “strict,” so reduce them: in each of the Max Rise (and
Fall) Rail Overshoot and Max Rise (and Fall) SI Overshoot columns (four columns total), type “1000” to
allow 1V of margin. Then click OK to close the spreadsheet.
6. In the wizard, click Next, so that you move to the Set Driver/Receiver Options page. Make/verify the
following settings: Driver Round Robin off (later, we’ll enable it); and Fast-Strong, Typical, and Slow-Weak
IC-model corners all on. (Leave other settings at their defaults.)
7. Click Next to move to the Set Delay and Transmission-Line Options page. Click to enable the Flight-Time
Compensation check box.
8. Click Next four times, making no more changes until you move to the Select Reporting Options page. In
the After the Batch Run Completes area, click to disable the Summary Report File check box, and to
enable the CSV File check box. Leave the “If opening Excel, auto-format” check box disabled.
If you’re not familiar with “flight-time compensation” or “driver time-to-Vmeasure,” see the next paragraph.
About flight-time compensation: The delays reported in signal-integrity simulations (like the one we’re
about to run) are intended to represent the interconnect delays between drivers and receivers on your
routed PCB. You can add these delays to your timing spreadsheet to make your calculations more
accurate.
However, there’s a possible problem: the Tco (clock-to-output) delays for driver ICs in your spreadsheet
already contain built-in delays that represent what happens outside the IC when it drives a load. Worse,
the built-in delay is into some reference load (like a 15-pF capacitor) that doesn’t match the actual
transmission-line load on your board. If you add to Tco in your spreadsheet the delays calculated by
BoardSim, you’ll account for two output loads: you’ll get the effects of both the real transmission-line load
(calculated by BoardSim) plus the reference load (assumed by your IC vendor in the datasheet Tco).
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To eliminate this problem, if you enable the Flight-Time Compensation check box in the wizard, BoardSim’s
batch engine will automatically determine how much reference-load delay is present for each driver’s Tco,
and subtract this value from all reported delays. (The reference-load delay is sometimes called the driver’s
“time-to-Vmeasure” value). With this "compensation” in place, you can add the batch report’s numbers
directly to your timing spreadsheet, and your Tco values will automatically be adjusted to remove the effect
of the extra, incorrect reference load.
This is a valuable “bookkeeping” feature that BoardSim’s batch feature performs automatically for you. (It
knows how to do this, by the way, based on simulating with reference-load information that’s contained in
each driver’s IC model.)
9. Now, click the Next button to move to the Run Simulation and Show Results page. Then click the Finish
button. If queried about whether to overwrite the .RPT we previously generated, click Yes.
After you click Finish, the batch-mode engine begins running, reporting its percent-done status. Because
batch simulation was enabled on only one net, it does not take long to run; however, because we chose to
simulate all three IC corners for the net, there are six simulations to perform (three corners X (rising + falling
edges)).
When the simulations have finished, the batch engine automatically writes out three files:
z a CSV (comma-separated values) file, suitable for loading into a spreadsheet application or parsing with a
custom script
z a text file (“.RPT”) file suitable for viewing in a text editor
z an SDF (“standard delay format”) file suitable for passing to timing-analysis and other tools that read the
format
1. On the Select menu, choose Component Models or Edit Values. The Assign Models dialog box opens.
2. With the IC tab selected, click once to highlight the first pin in the Pins list, then scroll down the list,
watching the Buffer Settings area to the right. Notice that for the previous simulation, the first four pins in
the list all had input-only (receiver) models attached, and pin U3.20 had an I/O pin that was manually set
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to state “output.” For the next simulation, we want to see what happens if all pins are I/Os, so…
3. …with pin U3.20 highlighted, in the Buffer Settings area, click the Input radio button. In the Model to Paste
area, click the Copy button, then click the Paste All button. Now scroll the highlight through the Pins list,
and notice that every pin is assigned an I/O model, and all are currently set to state “input.”
4. Select the Quick Terminator tab. For the next simulation, we’re also interested in seeing how signal-
integrity violations of various types are flagged in the batch-mode results. One easy was to create some
errors is to unterminate the net; so…
5. …highlight pin U3.20 in the Pins list, then in the Terminator Style area, click the None radio button. Click
Close to close the dialog box and click OK. If you get a warning that no pin has a driver, click OK.
Now, consider the current state of the net’s IC models: they’re all I/Os. This is the same situation as on any
real, “multi-drop” net on which multiple I/Os exist, any one of which may turn on and drive at any time. What
should be done in batch simulation for such a net?
For a net populated with multiple bidirectional buffers, it’s important for timing delays to be calculated for each
driver that can turn on. Maybe the maximum delay, for example, will occur when a driver at one end of the bus
is enabled (but which end?); or maybe (because the driver has to drive two traces simultaneously), the longer
delay will come from driving in the middle. You really can’t know for sure without running multiple sets of
simulations, one for each possible driver.
Setting up such simulations manually would be extremely time-consuming. Fortunately, BoardSim’s batch
engine has an option called “driver round robin” which, if enabled, will automatically walk through all possible
driver states, and run simulations for each. Let’s try running with it.
Open the batch wizard; turn off IC corners other than Fast-Strong, and enable round-robin simulation; for
reporting, again choose the CSV file:
1. On the Simulate menu, select Run Batch Simulation. The batch-wizard dialog box opens.
2. Click the Next button twice to move to the Set Driver/Receiver Options page. Click to enable the Driver
Round Robin check box. In the IC-Model Corners area, disable the Typical and Slow-Weak check boxes
(but leave Fast-Strong enabled).
3. Click Next five times to move to the Select Reporting Options page. Verify that the Summary Report File
check box is still disabled and CSV File is enabled.
4. Then click Next, then Finish, to run a new set of simulations. If a message asks whether to overwrite the
earlier report files, click Yes. (Make sure that Excel is not open currently on the old spreadsheet, so that it
can be re-created.)
The batch engine runs, reporting its status. When it completes, (as above) the results open in Excel or
another application mapped to the .CSV file extension. (If no application is mapped, manually open the file
DEMO-SI.CSV in a spreadsheet.)
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Note that some users may wish to parse all of this delay data from the CSV file using a custom program or
script. Since the CSV file is ASCII and simply formatted, this is not difficult to do. HyperLynx is committed to
preserving the format of the CSV file, so any investment in custom scripting that a customer makes will be
preserved in the future.
Close Excel (or whichever spreadsheet application is open on the results.)
Although there are many more advanced features which could be explored in BoardSim’s batch wizard, there
isn’t time in this introductory demonstration to cover them. (You’re welcome to experiment with more of them
or read about them in the Help system later, after completing this demo.)
Click here to continue with the front-to-back HyperLynx demonstration; next, we look at more post-
layout features in BoardSim.
Click here to return to the main menu.
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z quickly predict which nets are likely to suffer the most crosstalk, and have BoardSim determine
automatically which nets are the likely "aggressors"
z use electrical rather than geometric thresholds, for more-accurate and faster simulations (but geometric
thresholds are available, too, in case you prefer them)
z simulate a large number of nets in batch mode, with each net's numerical results (timing, overshoot,
crosstalk) saved into a report file
z simulate interactively to see in oscilloscope waveforms the exact amplitude of crosstalk on a victim net
z see the effects on crosstalk results of changing parameters like stackup layer, dielectric thickness, driver-
IC slew rate, driver impedance, line termination, and so forth
z confidently design high-speed buses and other PCB structures that meet tight timing and low-crosstalk-
noise requirements
z select termination strategies that greatly reduce or eliminate the crosstalk seen at receiver ICs
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z determine the differential impedance of trace pairs on your routed board, and observe the effects of
stackup layer, dielectric thickness, and so forth
z accurately simulate differential signals, taking into account the coupling between traces and the presence
of nearby aggressor and reference (power/ground) traces
z analyze both differential- and common-mode propagation, or any mix of the two
z easily design terminations that work for both the differential- and common-mode components of your
signals
1. On BoardSim's File menu, select Open BoardSim Board. (If any dialog boxes are open from an earlier
portion of this demonstration, close them first.) A dialog box opens. (If you’re prompted to save session
edits, click No.)
2. Double-click on the file name Demo2.hyp. The dialog box closes and a board layout appears in
BoardSim's viewer.
3. Click on the Crosstalk menu, and verify that Enable Crosstalk Simulation is disabled, i.e., not checked.
This board has three clock nets, "clk," "clk2," and "clkin." Let's run an analysis of "clk2."
1. On the Select menu, select Net by Name. A dialog box opens. In the Sort Nets By area, click on the Name
radio button.
2. Double-click on "clk2" to select the net. It appears in the board viewer, with other nets dimmed in the
background.
3. On the Crosstalk menu, select Enable Crosstalk Simulation.
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By default, BoardSim Crosstalk searches for aggressor nets whose individual crosstalk contributions to the
selected victim net exceed or equal 150 mV. Of course, you can adjust this threshold up or down as needed
to meet the requirements of your particular boards and nets.
Notice in the board viewer that only net "clk2" and its associated net "n00077" (they're connected together
through a series resistor) are visible in the foreground. This means that BoardSim predicts that no other nets
will generate 150 mV of crosstalk or more on net "clk2." (This demo board is low-density, for simplicity, so it's
not surprising that it doesn't exhibit a lot of crosstalk.) But now let's adjust the threshold down and see if any
nets exceed the new value.
Drop the crosstalk threshold to 50 mV using Crosstalk/Crosstalk Thresholds:
1. On the Crosstalk menu, select Set Crosstalk Thresholds. A dialog box opens.
2. Verify that the Use Electrical Thresholds radio button is selected. In the Include Nets with Coupled
Voltages Greater Than box, type "50."
3. Click OK.
Notice that more nets have now appeared in the foreground in the board viewer; each one shows with a
dashed line. These are the aggressor nets that could potentially contribute more than 50 mV of crosstalk to
the victim "clk2" net.
Use Reports > Net Statistics to see exactly which nets are aggressors to "clk2":
1. On the Select menu, select Component Models or Edit Values. The Assign Models dialog box opens.
2. In the Pins list, note that some pins have a "coupled" icon just to the left of the reference-designator/pin
label; these are the component pins on the aggressor nets. Pins on the selected, victim net have no icon.
3. The victim net's driver IC is U2.1. Find it in the list, then click once on it to highlight it.
4. With U2.1 highlighted, in the Buffer Settings area, click the Stuck Low radio button.
5. Click on pin U11.6 (at the bottom of the list). It has an I/O model that is currently set to buffer direction
"Input." In the Buffer Settings area, change this by clicking the "Output" radio button.
6. Repeat step 5 for pin U3.20.
7. Click Close.
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In the Coupling Region viewer, you'll see the names of the coupled nets, information about how far apart they
are in the currently displayed region, and a graphical stackup cross-section showing the nets. If you click on
the Impedance button, an impedance and termination summary is added to the window. You can stretch the
entire window vertically to more easily see its contents, or re-size individual panes in the window.
Note that even this simple net requires several different coupling regions to be accurately simulated. On real
nets on a dense board, it is not uncommon to have a hundred or more regions; BoardSim Crosstalk dutifully
and automatically models all of them for you. In the viewer, coupling regions are sorted (as you walk through
them) from strongest coupling to weakest.
1. On the Select menu, select Component Models or Edit Values. The Assign Models dialog box opens.
2. In the Pins list, double-click on pin U3.20. The Select IC Model dialog box opens.
3. In the Device list box, double-click on model CMOS,5V,MEDIUM (it has a slower slew rate than the
previous model).
4. Click OK to close the Select IC Model dialog box.
5. The aggressor net "datald" is no longer visible in the board viewer, since its driver is now not fast enough
to cause crosstalk above our 50-mV threshold.
Note: BoardSim Crosstalk offers geometric thresholds, if that's your preference. (See the Set Crosstalk
Thresholds dialog box.) But electrical thresholds are easier to use and more powerful.
1. On the Simulate menu, select Run Interactive Simulation. The Digital Oscilloscope dialog box opens.
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2. In the oscilloscope, click the Attach Probes button. A dialog box opens.
3. In the Pins list, double-click on each of the following IC pins: U8.9, then U11.6. (U8.9 is the receiver IC on
the victim net).
4. Click OK.
5. In the oscilloscope, click Start Simulation. The crosstalk simulation runs.
6. The red waveform is from the probe at the victim net's receiver IC. Change the vertical scale to 50 mV/div,
so you can clearly see the crosstalk shown by this probe; move the scroll bar at the right side of the
oscilloscope's display down until you see the red waveform again.
Because this simple demonstration board is not densely routed and does not use close trace spacing, it does
not show a great deal of crosstalk. (Also, we significantly slowed one of the aggressor net's driver ICs.)
Nevertheless, you can see that about +/-50 mV of crosstalk does appear at net "clk2's" receiver IC.
Again, it's worth noting that BoardSim will simulate any mixture of victim and aggressor traces; in fact, the
simulator really makes no distinction between the two. Generally, you'd prefer to have the victim nets (nets on
which you want to measure crosstalk) sitting stuck low or stuck high, but in this simulation we could just as
well have made "clk2" also switch, in which case it would have been both an aggressor to the other nets AND
their victim.
1. In the file editor, page through the Crosstalk Report - Quick Analysis section. Note that for each net on the
board with more possible crosstalk than the specified 50-mV threshold, the file editor gives a list of each
net's aggressor nets and an estimate of how much crosstalk each aggressor could generate. The
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contribution of the two strongest aggressors is summed to give a realistic overall crosstalk estimate. Nets
are sorted from most to least crosstalk; this gives you a powerful and simple way to see which nets on
your board are most likely to suffer from crosstalk.
2. On the editor's File menu, select Exit to close the file editor.
Again, it should be emphasized that a Crosstalk Strength Report is a powerful guide to further simulations on
any given board. Since it is electrically based, it is usually considerably more accurate than a simple
geometric “parallelism” report. It can be generated very quickly (even before final IC model assignments are
made), and serves as an excellent guide to which nets on the board need further analysis: interactive, batch-
mode, or a mix of the two.
After a short period of time, depending on the speed of your computer, the batch engine finishes the
requested simulations on net "clk2" and opens its report file.
Use the file editor to look at the data in the batch-mode report:
1. The report contains a detailed table for net "clk2," summarizing its signal-integrity and crosstalk behavior.
Several nets are identified as aggressor nets. After the numerical data, warnings are issued to indicate
these nets have no driver-IC model (this helps you know whether any IC models are missing during
simulations). The numerical data gives the rising- and falling-edge pin-to-pin delays for the driver IC and
each receiver, as well as the maximum overshoot and peak-value crosstalk that occurred. If any
thresholds defined in the Nets Spreadsheet are exceeded, the report flags them as warnings. In this case,
we see that crosstalk on clk2 exceeds our 50 mV threshold on both edges.
2. On the editor's File menu, select Exit to close the report.
Note that in this case, we looked at the batch engine’s human-readable text output (.RPT file). If you ran the
earlier section on BoardSim’s batch-mode features, you saw the alternative .CSV file, which is optimized for
viewing in a spreadsheet application (or parsing by a custom, external script).
BoardSim Crosstalk is useful not only for identifying crosstalk problems, but also fixing them. There are a
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number of ways to reduce crosstalk, including changing driver ICs (slower slew rates are better), altering
board stackup, and adding line termination. We won't explore any of these options in detail now, but, for
example, if you want, try simulating net "clk2" as is; then using the stackup editor (Edit > Stackup) to reduce
the board's dielectric thicknesses to 5 mils; then re-simulating to see how the amount of crosstalk is changed.
Click here to continue with the front-to-back HyperLynx demonstration; next, we turn our attention to
advanced features intended specifically for post-layout analysis of GHz-level, SERDES-based
designs.
Click here to return to the main menu.
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z Eye diagrams
z Multi-bit stimulus
z Lossy transmission-line analysis
z Advanced via modeling
z Integration with SPICE simulation (HSPICE or Eldo)
z Touchstone (S-parameter) modeling
In an earlier section, we showed many of these features (eye diagrams with multi-bit stimulus, lossy-line
analysis, integrated SPICE simulation, and Touchstone modeling) in the context of LineSim. In this section,
we'll look at via modeling. However, eye diagrams, lossy analysis, integrated SPICE simulation, and
Touchstone modeling are available in BoardSim, just as they are in LineSim. Click here if you want to
review these features, by running them in LineSim.
If you want to review any of BoardSim's traditional, non-GHz-specific features, click here.
1. On BoardSim's File menu, select Open BoardSim Board. Another dialog box opens. If prompted to save
session edits, click No.
2. Double-click on the file name Demo.hyp. The dialog box closes and a board layout appears in BoardSim's
viewer.
3. On the Select menu, select Net by Name.
4. Double-click on "clk" to select the net.
Note that this net is poorly routed from a high-speed standpoint: it contains multiple vias.
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1. On the Select menu, choose Component Models or Edit Values; the Assign Models dialog box opens.
2. In the Pins list, double-click on pin U1.13; the Select IC Model dialog box opens.
3. Click the EASY.MOD button.
4. In the Devices list box, double-click on "CMOS,3.3V, ULTRA-FAST" to choose the model; then click Close
to close the Assign Models dialog box.
1. On the Edit menu, select Via Modeling. The Select Method of Simulating Vias dialog box opens.
2. At the top of the dialog box is the Include Via L and C check box, which controls whether any via modeling
is used during simulation. Disable the check box to turn off all via modeling; the options lower in the dialog
box all gray out.
3. Click OK to close the dialog box.
Then open the oscilloscope using Simulate > Run Interactive Simulation; set IC Modeling to Fast-Strong; and
click Start Simulation:
1. On the Simulate menu, select Run Interactive Simulation; the Digital Oscilloscope dialog box opens.
2. In the IC Modeling area, select Fast-Strong, to simulate with the fastest possible driver edge.
3. Click the Start Simulation button; a waveform appears.
1. On the Edit menu, select Via Modeling. The Select Method of Simulating Vias dialog box opens again.
2. Enable the Include Via L and C check box to turn back on via modeling; the options lower in the dialog
box re-enable.
3. Verify that the Auto-Calculate radio button is selected. This tells BoardSim to use its built-in automatic
modeling algorithms for vias.
4. Click OK to close the dialog box.
Now, re-simulate:
Compare the two waveforms; note that there is a clear difference in delay at the receiver ICs (yellow and
purple waveforms). The delays are pushed out when via modeling is added to the simulation. The effect is
reminiscent overall of the increased delay caused by the addition of lossy transmission-line analysis, as we
saw earlier in the LineSim GHz portion of the demonstration, meaning that for accurate delay calculations, it’s
often important to use accurate via modeling. Note that in BoardSim’s batch-mode wizard, you can enable
both lossy transmission-line and via modeling.
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3. Select the User-Supplied Padstack-Specific L and C radio button; a spreadsheet appears and values are
filled in after a short delay.
The radio-button choices in the top half of the dialog box offer three types of via modeling:
z Auto-calculate – the most powerful method, this tells BoardSim to invoke internal algorithms to
automatically model each instance of a via; these algorithms decompose each via into sections and call
fast solvers, section-by-section, accounting for detailed effects such as the frequency-dependent
inductance of a via as it changes its signal's reference planes; includes the effects of different signal entry
and exit layers
z User-supplied global L and C – allows knowledgeable users to supply a single L and C value to be used
for all vias on a board
z User-supplied padstack-specific L and C – a more-advanced type of user-supplied value, managed in a
spreadsheet; the user can mix auto-calculated values for some vias and specify custom values for certain
other padstacks
In the spreadsheet, in the Padstack Name column, the names appear as “AutoPadstk_X.” This is an artifact of
the demonstration PCB; if you were running with one of your own designs, you would see the actual padstack
names that you or your layout designer created in your PCB tool.
Most users will prefer the automated algorithms (because they’re quite accurate and powerful), but
sophisticated users may wish to supply their own L's and C's, based perhaps on the results of external
electromagnetic extractions or lab-measured data.
Look briefly at the contents of the padstack spreadsheet. Until you disable some Auto check boxes, each
padstack shows its auto-calculated value. Note the typical values: hundreds of pH and fF, for L and C
respectively. For padstacks that cause their signals to change reference planes at least once, the L value is
frequency-dependent; BoardSim displays it in the spreadsheet at f=250 MHz, but during simulation uses the
"knee frequency" of each net's driver-IC switching edge as the calculation frequency.
Note that in the board viewer, other nets are dimmed and net DRV1_OUT1+ and its companion net
(DRV1_OUT1-) appear, as a differential pair.
Looking at the routing of this pair, it’s easy to see several possible problems. First, it does not appear
completely symmetric, which could introduce skew between the two halves of the pair (and therefore convert
a pure differential driver signal at least partially into common mode). Second, it includes two via pairs. While
vias are not “forbidden” in differential signaling, their detailed electromagnetic effects need to be watched and
simulated with great care.
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Let’s examine one of the via pairs with the Via Visualizer.
Use View > Zoom Area to zoom into the region around the left-hand of the selected nets’ two via pairs; point
to one of the vias with the mouse, right-click, and select View Via Properties:
1. On the View menu, select Zoom Area. The mouse cursor changes into a magnifying-glass shape.
2. With the left mouse button pressed, drag a box around the area of the left-hand of the selected nets’ two
via pairs, then release the mouse. The viewer zooms in and the vias appear larger.
3. Point to one of the two vias in the pair, until it its round top-layer pad highlights in black. (Be careful not to
highlight one of the connecting trace segments instead.)
4. Then right-click with the mouse. A pop-up menu appears; select View Via Properties. The Via Visualizer
opens. Drag its bottom edge, if necessary, to see the entire graphic in the Visualizer.
The Via Visualizer has opened on the selected via pair. It recognizes (after running a fast geometric/electrical
check) that the via you actually pointed to has a coupled, partner via, and displays both of them. As the dialog
box opens, the Visualizer runs BoardSim’s fast via calculator to determine the via pair’s coupled electrical
characteristics.
In detail, the Via Visualizer is showing the following information:
z the detailed stackup of the PCB; signal layers are shown in solid color and plane layers with “hatched”
colors; all metal is displayed in its layer color
z the exact visual geometry of each via in the differential pair, including connected traces, pads and anti-
pads, and drill hole
z labeling for all geometric dimensions (including pad shapes/diameters, anti-pad diameters, drill-hole
diameter, and separation between the two vias)
z to the side of each via, the via’s electrical model (including the effects of coupling between vias), including
the impedance and delay of the via (drawn as a labeled transmission line), 3-D pad capacitance for entry
and exit layers (drawn as a lumped capacitor)
z the impedances of connecting traces (labeled with “Z0=xxx”)
z a message in red at the bottom of the dialog warning that there seems to be an impedance discontinuity
between the surrounding traces and the via pair (simulation will tell whether the mismatch is serious or not)
Remember that all of this information is automatically calculated and used by BoardSim’s simulator whenever
via modeling is enabled. However, the Via Visualizer makes the modeling information explicit and accessible
to the user (rather than completely hidden, like it is in some other signal-integrity tools).
Note also one other feature: by clicking the Export to SPICE button (at the dialog box’s bottom), you can
easily create a SPICE sub-circuit of the entire via structure.
Click here to continue with the front-to-back HyperLynx demonstration; in this final section we take a
quick look at how BoardSim handles multi-board, system-level simulations.
Click here to return to the main menu.
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Note: The EBD format is a portion of the IBIS specification. IBIS is best-known for modeling IC buffers.
However, its EBD format allows random interconnect to be modeled, and can be used to represent PCBs,
complex IC packages, and so forth.
The main difference between a .HYP file and an EBD model is that the .HYP file is physical: it contains details
about trace routing, stackup, etc. EBD models, on the other hand, are purely electrical: the interconnect is
represented as transmission lines, with already-calculated inductance and capacitance, or impedance and
delay. Thus, a .HYP file can be viewed (there is physical routing to display), while an EBD file can't (there's no
physical information to show). Also, EBD files can't represent coupling. However, either type of file can be
used to include the effects of plug-in modules and boards in a multi-board simulation.
1. If any dialog boxes are open from a previous portion of the demonstration, close them.
2. On the MultiBoard menu, select Open MultiBoard Project. A dialog box opens.
3. Double-click on the file name Demo_MultiBoard.PJH. (A ".PJH" file stores information about a MultiBoard
project; it points to the .HYP files which make up the project.) If prompted to save session edits, click No.
BoardSim loads each of the boards in the project, similar to how you've already seen it load single .HYP files
– except that in this case, there are three boards involved. Notice that in the board viewer, all three boards are
visible at one time.
1. On the MultiBoard menu, select Edit MultiBoard Project. The MultiBoard Project Wizard opens.
The Wizard's first page lists the boards in the project. Adding boards to a project is easy: just click the
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Insert button and choose the board's .HYP file. This example project consists of a main board and two
identical plug-in modules. Note that a comment has been added beside each board's .HYP-file name;
we'll see these labels later in BoardSim's dialog boxes.
The Wizard's second page shows the connections between boards. In the Interconnection List, the main
board's connector J1 is connected to plug-in PCB #1's J1, and main board's J2 is connected to plug-in
#2's J1. For any two connector halves whose pin names match, a single entry is all that's required in the
Interconnection List; BoardSim automatically does the pin-by-pin mating. (If you have connectors whose
pin names don't match, or a connector half that connects to more than one other connector, there's a way
to list explicit pin-by-pin connections.)
The Wizard's third page shows the electrical characteristics of each board-to-board connector. You can
specify a connector's electrical behavior by providing either a capacitance and inductance, or a delay and
impedance. For most connectors, the manufacturer can provide this information.
The yellow and purple oscilloscope waveforms show the signals at the receiver-IC pins, on the plug-in boards.
Note that there is some overshoot at the receivers. The waveforms you would have seen if you had simulated
with just the main board or just one of the plug-in PCBs would be different: only by combining the traces from
both boards in the simulation do you see the actual, system-level waveforms.
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And this power does not come with an ease-of-use penalty: BoardSim is hardly any more difficult to use for
multi-board analysis than for single boards. If your connectors use consistent pin names between the mating
halves, you can usually set up a multi-board project in a matter of just a few minutes.
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