Front-To-Back MMIC

Design Flow with ADS

Speed MMICs to market

Save money and achieve
high yield

Unique Tools for Robust Designs, First Pass, and

High Yield

Yield Sensitivity
Histogram (YSH)
to components

Agilent EEsof MMIC Foundry Partners

All ADS kits are built and certified by foundries
Atmel
austriamicrosystems
Bookham Technology
Cree, Inc.
Filtronic Compound Semiconductors
Global Communication Semiconductors, Inc. (GCS)
IHP Microelectronics
Infineon
IBM Microelectronics
Jazz Semiconductor
Knowledge*on Semiconductor
Maxim Integrated Products
Northrop Grumman Electronic Systems
Northrop Grumman (Velocium)
MagnaChip Semiconductor
Ommic
Peregrine Semiconductor
Raytheon RF Components
Philips Electronics N.V.
Semiconductor Manufacturing International Corporation (SMIC)
STMicroelectronics
Triquint
UMC
UMS
TSMC
WIN
X-FAB

Advanced Tools Seamlessly Integrated in ADS

Convolution

Circuit Envelope
Planar EM
Momentum
Phase Noise at VCOs
Output

Linear Simulator

Phase Noise at
Dividers Output

3D Features includes 3D
JDEC Bond Wire

AM Noise at Dividers Output

Harmonic Balance

FEM 3D EM (EMDS)

True MMIC Verification Prior to Manufacturing

True MMIC Design Verification prior to
Manufacturing is done by Co-simulating
the MMIC inside the package and with
bond wires using EMDS in ADS 2008

EMDS JDEC Bond Wire

PA Verification to Wireless Standards

Realistic Input Signals and test benches for all Wireless
Standards
WIMAX Transmit
Source
PA Verification to
wireless Standards

PA

ADS Complete Front-to-Back MMIC Design Flow

Sc
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Part 1

Agilent EEsof EDA MMIC Foundry Partners

All ADS Kits are built and Certified by Foundries

Knowledge*on

Gaetec
The only complete MMIC PDK offering in the EDA Market, that is fully
supported, maintained, and regularly updated by the foundries.
If we dont have the PDK kit you need, well create it for you!
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Advanced Model Composer (AMC) Technology

AMC brings the accuracy of EM
simulation and the speed of
analytical models into a single,
user-defined, compact model.
Arbitrary user-defined
parameterized shapes
Generates model,
symbol & layout

Example: TriQuint MASC Design Kit

Valid Range of models

EM based Inductor
Models Using AMC
Technology
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Fully Parameterized Lines and Discontinuities

Initial Line

Lines Information
contain Layers and
current density

Modifying the line by inserting an

air-bridge with an offset and angle

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Example: LNA - TriQuint MASC Design Kit

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ADS Complete Front-to-Back MMIC Design Flow

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Demo example Ku-band LNA

Front End Design FET Characterization

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Front End Design

Biasing, Stability, Max Gain, Noise and Gain Circles

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Front End Design

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Impedance Matching

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Front End Design

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Front End Design

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Front End Design

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Front End Initial Design Yield Analysis

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ADS Complete Front-to-Back MMIC Design Flow

DFM

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The Value of ADS DFM Technology

Designing circuits that will work no matter what
First to market

High manufacturing yield

(Lower cost per chip)

Insensitive to changes in
temp and supply voltage

First pass success

ADS
DFM Tools

Tremendous amount of
time and $$ savings

Reliable, high quality designs

The only EDA company with unique DFM design tools that allow
MMIC designers to create and manufacture robust circuits with
first-pass success and high yield
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Real MMIC Designs Fabricated on the Same Wafer

Actual real-world examples

A reticle contains a few

circuits, stepped and repeated
across the whole wafer

Amp1 A
mp2
U/C 1
U/C 2
macro
macro

1) Used a standard
design technique
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2) Used a DFM Based

design technique

All designs went

through the same
Wafer Fab Process

K-Band Up Converter Wafer Probed Results

Mixer 1

Ku-band

U/C 1 Macrocell / Standard Design

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X-band

K-band

Amp2

Ku-band

LO

K-band

Amp1

LO

X-band

Mixer 2

U/C 2 Macrocell / DOE Based Design

Wafer Probed Results

Note: Foundry process shifted to the left during this run. Amp2
shift was less sensitive to this shift
Amp1

Amp2

Standard Design

Amp1
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DFM based Design

Amp2

Understanding the Difference

Amp2

Amp1

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ADS Matching Tool Helps find Robust & High Yield

Networks

19 different networks with

different topologies to
choose from
They all include
DFM analysis!

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Using DFM Techniques On a Demo One-Stage LNA

Yield Sensitivity
Histogram (YSH)
to components

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Using DFM Techniques to Transform One-Stage

LNA into a Robust Design with High Yield

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ADS Complete Front-to-Back MMIC Design Flow

PA Verification

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PA Verification to Wireless Standards

Realistic input signals and test benches for all wireless
standards
WIMAX Transmit
Source
PA Verification
to wireless
Standards
PA

The most accurate and only tool set that provides true circuit verification
to all wireless standards pre- and post-fabrication.
Helps designers not only test and verify their designs, but also get the most
performance out of their circuits.

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An Example WIMAX PA
EVM verification and spectrum

Insert WiMAX PA into the Wireless Test Bench and press simulate

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An Example WIMAX PA
Small signal gain, S11 and Pin/Pout

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Example WiMAX PA EVM Verification

Fas
t

Simulation Time 20 minutes

Fast Cosim (AVM) Not Used

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ver
ific
atio
n!

Simulation Time < 20 seconds

Using Fast Cosim (AVM)

Example WiMAX PA Spectrum

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Swept EVM and Statistical Analysis

Easy Statistical Analysis
on PA Verification
at the System Level
50 Monte Carlo trials
10 minutes 2GB RAM

Sweeping EVM as a
function of Input Power, Pin
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ADS Complete Front-to-Back MMIC Design Flow

Part II

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Advanced Backend Physical Design Capability

Schematic/Layout Synchronization
ADS 2008 Layout
Synchronization
Simulating Layout in
Schematic page
Layout / Schematic Design
Differences
Physical Connectivity
Engine OR Lay-con
DRC
Planar and 3D EM Tools

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Advanced Backend Physical Design Capability

Total flexibility with three synchronization modes
ADS provides three different synchronization modes between
schematic & layout, providing optimum flexibility in the
development of MMICs
Designers are not
constrained by always
having schematic and
layout automatically
synchronized

Ability to switch back and forth between the three different modes
Allows you to efficiently and accurately fit many elements designs into small areas.

The result is a smaller die size and lowered overall cost per chip.
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Advanced Backend Physical Design Capability

Schematic/layout look-alike

Original
Schematic

Layout look alike

Synchronized
Layout for
Momentum
EM Simulation
& Optimization

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Used in the schematic page as:

Full or Sub-network
Graphical Cell Compiler with
parameterized variables
Advanced Model Composer with
parameterized variables

New Transparency to Layer Configuration

Improved layout visibility for multilayer MMIC designs
Easier to see through the multilayer designs such as traces, grounds, and
vias

Before

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After

Advanced Backend Physical Design Capability

Design differences

Identifies

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Components in Layout not in Schematic

Components in Schematic not in Layout
Parameter Differences
Nodal Mismatches

Advanced Backend Physical Design Capability

Check layout vs. schematic and check layout for errors
Custom LVS Utility Program

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Advanced Backend Physical Design Capability

Check physical connectivity (LayCon)
Physical Connectivity
Engine allows you to
check your layout for any
errors.
This capacitor is not shorted.
It is fine.

This capacitor is shorted. It is

shown by the metallization
run.

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Advanced Backend Physical Design Capability

Check physical connectivity (LayCon)

Problem Fixed

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Advanced Backend Physical Design Capability

Building reticles in ADS (TriQuint Foundry)

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Advanced Backend Physical Design Capability

EM simulation with Momentum and EMDS
Spiral inductors are the largest devices on-chip and probably least understood.
Spiral Inductors, Transformers, and Transmission Lines are important to model
accurately in MMIC.
Bond wires and package effects are very important to design to and verify to.
Remember, the MMIC doesnt end at the chip level.
Both Momentum Planar EM simulator and EMDS 3-D
finite-element EM simulator are both seamlessly integrated
in ADS and can insure your design success.

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Momentum EM Simulation
Accuracy and speed pays off
Industries first 64-bit 3D planar EM solver

Improved thick conductor modeling:

Now includes the addition of horizontal
current modeling on the metal
interconnects sidewalls as well as the
vertical currents.
Adding a new Krylov Iterative Solver:
Momentum now hosts three unique
solvers to address the varying degrees
of EM modeling complexity and extend
EM modeling efficiencies across a much
wider application coverage area.

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LNA Layout & Momentum Simulation on the OMN

of our one Stage LNA

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LNA Simulation Results with Momentum

Simulation on the OMN of LNA

No Change in NF
m
Momentu
Cir
c

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uit
m

od
el

Momentum Optimization on LNA OMN

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Momentum Optimization on LNA OMN

Meshing during
Momentum
dimulation and
optimization

Output matching metwork parameterized

layout look-alike component for EM
simulation and optimization

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Momentum Optimized Results

Results achieved by reduction in line
lengths and the series spiral inductor

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EMDS Integration into ADS

3D Features
includes 3D
JDEC Bond Wire

EMDS is now Seamlessly

Integrated in ADS
Follows the Momentum Model

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Advanced 3D EM Simulation with EMDS

Co-simulation of a balanced MMIC Amp inside a 10-pin
package
Efficient approach to package
modeling is to Co-simulate the
MMIC circuit design inside the
package using EMDS in ADS.

EMDS accurately models package

parasitic and its effects on the
MMIC Chip Performance.

Co-Simulation / Optimization
automatically adjusts the designs
parameters and brings back its
performance by counteracting the
effect of the package parasitic

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True MMIC Verification prior to Manufacturing

Our LNA Example
True MMIC design verification prior to
manufacturing is done by co-simulating
the MMIC inside the package and with
bond wires using EMDS in ADS

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3D View

True MMIC Verification Before Manufacturing

You can co-simulate and optimize the

response in the same way as in
Momentum.
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Advanced Backend Physical Design Capability

Design Rule Check (DRC)
Automatically
Finds the Rules
file location
Automatically
Loads the Rules
file
All you have to
do Is to click on
Run

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Advanced Backend Physical Design Capability

Design Rule Check (DRC)
Users now can Load, Run, Compile, and View Results in one mouse click.
Users can sort errors and can choose to view any error first.
DRC provides exact error coordinates and lets you pan and zoom.

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3D Pre-Viewer with Z-scale Expansion

Scale up substrate thicknesses to easily visualize a complex 3D
layout

ADS 3D View

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Up-scaled View

3D Previewer with Cut Plane

Cut through the layout to easily visualize a complex 3D layout
3 cut planes on XY, YZ, and XZ plane
Flip Cut positive or negative cut

No Cut Plane Enabled

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YZ Cut Plane Enabled

New Drag and Drop From Project View Window

Drag and drop existing designs to the current design
Both for Schematic and Layout
Drag and drop designs directly from the Project View window
No need to browse the library browser

Drag and Drop

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Trace With Automatic Via Insertion

Easier to change trace layers with
hot keys, comma(,) and period(.)
Automatically inserts the via when
changing layers.
3D view

2D view

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ADS Data Display is Another Design Tool

Post Processing and Data Display
RF specific functionality and flexibility to post-process and
display data, for better insight to the circuit behavior.

A design tool helps achieve faster design cycles

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