LETTER IEICE Electronics Express, Vol.14, No.

6, 1–8

A 2.4-GHz all-digital phase-

locked loop with a pipeline-
ΔΣ time-to-digital converter
Zixuan Wang1,2a), Shanwen Hu1, Zhikuang Cai1, Bo Zhou1,
Xincun Ji1, Rong Wang2, and Yufeng Guo1
1
College of Electronic Science and Engineering, Nanjing University of Posts and
Telecommunications, Nanjing 210000, China
2
Jiangsu Lixing General Steel Ball Co., Ltd, Nantong 226500, China
a) wangzixuan@njupt.edu.cn

Abstract: A 2.4-GHz all-digital phase-locked loop (ADPLL) for Zigbee

application is presented. The proposed pipeline-ΔΣ TDC is based on
two-stage time quantization with pulse-train time amplifiers. It achieves an
SNDR of 80 dB and a high resolution up to 0.23 ps. A MASH 1-1-1 ΔΣ
modulator based on vernier lines is used to achieve third-order noise shaping.
The proposed ADPLL has been implemented in a 0.13-µm CMOS technol-
ogy. The measurement results show a 12-mW total power consumption.
The in-band and out-band phase noise are −91 dBc/Hz@10 kHz and
−128 dBc/Hz@1 MHz, respectively. The RMS jitter and peak-peak jitter
are 2.9 ps and 21.5 ps, respectively.
Keywords: ΔΣ-TDC, pipeline, noise shaping, ADPLL
Classification: Integrated circuits

References

[1] V. Kratyuk, et al.: “A digital PLL with a stochastic time-to-digital converter,”

IEEE Trans. Circuits Syst. I, Reg. Papers 56 (2009) 1612 (DOI: 10.1109/TCSI.
2008.2010109).
[2] C. M. Hsu, et al.: “A low-noise wide-BW 3.6-GHz digital ΔΣ fractional-N
frequency synthesizer with a noise-shaping time-to-digital converter and
quantization noise cancellation,” IEEE J. Solid-State Circuits 43 (2008) 2776
(DOI: 10.1109/JSSC.2008.2005704).
[3] M. Z. Straayer and M. H. Perrott: “A multi-path gated ring oscillator TDC with
first-order noise shaping,” IEEE J. Solid-State Circuits 44 (2009) 1089 (DOI:
10.1109/JSSC.2009.2014709).
[4] M. Song, et al.: “A 2.4 GHz 0.1-Fref-bandwidth all-digital phase-locked loop
with delay-cell-less TDC,” IEEE Trans. Circuits Syst. I, Reg. Papers 60 (2013)
3145 (DOI: 10.1109/TCSI.2013.2265975).
[5] R. B. Staszewski, et al.: “Spur-free multirate all-digital PLL for mobile phones
in 65 nm CMOS,” IEEE J. Solid-State Circuits 46 (2011) 2904 (DOI: 10.1109/
JSSC.2011.2162769).
[6] Y.-H. Tu, et al.: “A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase
based TDC,” IEICE Electron. Express 13 (2016) 20150950 (DOI: 10.1587/
© IEICE 2017 elex.12.20150950).
DOI: 10.1587/elex.14.20170095
Received February 5, 2017
Accepted February 13, 2017
Publicized February 27, 2017
Copyedited March 25, 2017

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[7] K. Kim, et al.: “A 7 bit, 3.75 ps resolution two-step time-to-digital converter in

65 nm CMOS using pulse-train time amplifier,” IEEE J. Solid-State Circuits 48
(2013) 1009 (DOI: 10.1109/JSSC.2013.2237996).
[8] M. Lee and A. A. Abidi: “A 9 b, 1.25 ps resolution coarse-fine time-to-digital
converter in 90 nm CMOS that amplifies a time residue,” IEEE J. Solid-State
Circuits 43 (2008) 769 (DOI: 10.1109/JSSC.2008.917405).
[9] Y. Cao, et al.: “1-1-1 MASH ΔΣ time-to-digital converters with 6 ps resolution
and third-order noise-shaping,” IEEE J. Solid-State Circuits 47 (2012) 2093
(DOI: 10.1109/JSSC.2012.2199530).
[10] Y. C. Huang, et al.: “A 2.4 GHz ADPLL with digital-regulated supply-noise-
insensitive and temperature-self-compensated ring DCO,” IEEE ISSCC. Dig.
Tech. Papers (2014) 270 (DOI: 10.1109/ISSCC.2014.6757430).

1 Introduction
As the key components of transceivers, phase-locked loops (PLLs) provide pure
local oscillation signals for mixers. All digital PLLs (ADPLLs) have better noise
immunity, greater scalability and better adaptability to deep-submicron process,
comparing to the analog implementations [1]. As important modules of ADPLLs,
time-to-digital converters (TDCs) largely affect loop performance. Higher resolu-
tion of a TDC gives the benefits to decreased quantization errors and in-band noise
[2, 3]. Unfortunately, it is difficult to achieve a high-performance TDC because the
input time is a special signal that is hard to store and process.
As a special type of analog-to-digital converters, the state-of-art TDCs are as
follows. A flash structure [4, 5] is simplest and fastest, but its resolution is limit to
gate class. A pipeline TDC [6, 7, 8] has higher resolution, but the limited resolution
still causes the quantization noise and brings the noise in band. An attractive
structure with oscillators [2, 9, 10] can solve this problem. It uses difference
operations on quantization errors and achieves noise shaping, which resembles to
the principle of a  ADC. However, the resolution of this structure is largely
limited by the oscillator frequency. Furthermore, the gated ring oscillators are
hardly enabled when the input time intervals are small.
Here we present a 2.4 GHz integer-N ADPLL with a pipeline- TDC, as
shown in Fig. 1. On power up, only the auto frequency calibration (AFC), DCO
and 1/8 divider are active. AFC counts the number of cycle of FDCO=8 in one Fref
cycle, compares it with jNdiv=8 j and changes FTW accordingly. Once AFC finishes
detection, it freezes FTW and activates frozen module by setting En low-voltage.
The TDC output is processed by DLF and  modulator, and controls DCO core.
The proposed TDC is composed of a pipeline TDC and a  TDC. The  part
uses charge pumps and capacitors to accumulate the small output of the pipeline
TDC in the form of voltage, and achieves noise shaping. Therefore, the proposed
structure simultaneously has advantages of high resolution and noise-shaping effect
thanks to the pipeline structure and the  modulator respectively.

© IEICE 2017
DOI: 10.1587/elex.14.20170095
Received February 5, 2017
Accepted February 13, 2017
Publicized February 27, 2017
Copyedited March 25, 2017

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 IEICE Electronics Express, Vol.14, No.6, 1–8

Fig. 1. Block diagram of the proposed ADPLL

2 Proposed pipeline- TDC

The proposed pipeline- TDC is composed of a pipeline TDC and a  TDC, as
shown in Fig. 2. The pipeline TDC is based on two-stage time quantization. The
first stage has 64 delay units, with a coarse resolution of 25 ps. So the measure
range is up to 1.6 ns to accommodate the probable phase jumps duo to 
modulator in DCO (the cycle of DCO output signal TDCO is about 0.4 ns in this
work). The second stage has a similar structure with the first stage, the only
difference is the second stage has a shorter delay line that comprises only 16 delay
units. The gain of the pulse-train time amplifier (TA) [7] is 16. Therefore, the
pipeline TDC can achieve a resolution of 1.6 ps.

Fig. 2. Structure of the proposed pipeline- TDC

The  TDC is composed of a MASH 1-1-1 modulator and an error neutralizer,

as shown in Fig. 3a. In the first stage modulator, the pipeline TDC output Derror0
controls the charge pump (CP) to charge the capacitor. The amplified time residue is
thereby converted to a corresponding voltage and is periodically accumulated on
the capacitor. The discharger uses the same delay units with that of pipeline TDC to
generate a reference voltage Vref that corresponds to an amplified time resolution.
When the integral voltage on capacitor Vc1 is beyond Vref, the comparator outputs
one and activates the buffer to discharge the capacitor, otherwise, it outputs zero
© IEICE 2017
and locks the buffer. Therefore, Vc1 will be decreased by a voltage of Vref after one
DOI: 10.1587/elex.14.20170095
Received February 5, 2017
discharge, as shown in Fig. 3b. In this design, all the CPs have a same current of
Accepted February 13, 2017
Publicized February 27, 2017
800 µA and the capacitance is up to 0.8 pF to reduce the influence of parasitics.
Copyedited March 25, 2017

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© IEICE 2017
DOI: 10.1587/elex.14.20170095
Received February 5, 2017
Accepted February 13, 2017
Publicized February 27, 2017
Copyedited March 25, 2017
IEICE Electronics Express, Vol.14, No.6, 1–8
A MASH 1-1-1  TDC is formed by cascading two same  modulators,
which can achieve higher order noise shaping. Unit-gain buffers are used to isolate
capacitors in different stages. Switch capacitor integrators are used to accumulate
quantization errors that are generated in the previous stage. The dischargers are
same in each stage. An error neutralizer in digital circuit follows the three 
modulators to neutralize the quantization errors in the first and the second stages.
Therefore, the output only contains the high-pass filtered quantization error
generated in the third stage modulator.
(a)
(b)
Fig. 3. (a) Structure of the proposed MASH 1-1-1  TDC, (b)
Waveform of the  modulator.
3 The all-digital PLL
As shown in Fig. 4, the LC-based DCO consists of three tuning stages: a 5-bit
binary-coded coarse array tuned by the AFC, a 6-bit binary-coded medium array
tuned by the DLF and a 7-bit thermometer-coded fine array tuned by the 
modulator in DCO. The DCO achieves a tuning range of 2.39–2.52 GHz, meeting
the required frequency range (2.4–2.485 GHz) of Zigbee applications. A MOS
capacitor, comprising two PMOS pairs that are inversely connected in parallel, is
used as the unit of the medium and fine array to achieve a tiny capacitance up to
0.1 fF, corresponding a high resolution up to 200 kHz/LSB. In order to eliminate
a possible gap between adjacent frequency bands due to PVT variations, the unit
capacitance of the medium array is slightly smaller than that of the fine array.
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In the arbiter circuit, the two pMOS transistors have insufficient time to charge
their drain terminals prior to the next detection when the phase difference between
start and stop approximates ³, as shown in Fig. 2. This probably results in
abnormal situations of TDC operation. A divider with zero-phase error starting
can solve this problem. Ndiv is the dividing ratio. 10-stage D flip-flops form a 10-bit
down counter. When the count value is down to zero, jNdiv =2j and Ndiv -jNdiv =2j are
alternately selected to be the load value of D flip-flops. Once AFC finishes
frequency locking, the signal En triggered by the falling edge of Fref becomes
low-voltage. Then the divider starts to work and the first rising edge of Fdiv will
align with that of Fref when the divider finishes the first down-counting, as shown
in Fig. 5. The zero-phase error starting is achieved and the locking time is largely
reduced, although there is still a tiny phase difference that is much less than ³.

Fig. 4. Structure of the proposed DCO

© IEICE 2017
DOI: 10.1587/elex.14.20170095 Fig. 5. Structure of the divider with zero-phase error starting
Received February 5, 2017
Accepted February 13, 2017
Publicized February 27, 2017
Copyedited March 25, 2017

5

© IEICE 2017
DOI: 10.1587/elex.14.20170095
Received February 5, 2017
Accepted February 13, 2017
Publicized February 27, 2017
Copyedited March 25, 2017
IEICE Electronics Express, Vol.14, No.6, 1–8
4 Experimental results
The proposed ADPLL has been fabricated with a 0.13-µm CMOS technology. The
chip occupies 0.49 mm2, as shown in Fig. 6. A 10 kHz −3 dBFs PWM signal is
applied to the  TDC. The bandwidth is about 100 kHz and the sample frequency
is 20 MHz (Fref ), denoting an OSR of about 100. The measured spectrum agrees
well with third-order noise shaping, as shown in Fig. 7. It shows an SNDR of
24.8 dB and an ENOB of 3 bits. Combining the 10-bits 1.6-ps-resolution pipeline
TDC, the whole pipeline- TDC can achieve an SNDR of about 80 dB and an
effective resolution of 0.23 ps.
Fig. 6. Chip micrograph
Fig. 7. Measured output spectrum
The measured results of ADPLL output noise with and without  TDC are
shown in Fig. 8a and Fig. 8b, respectively. When the whole pipeline- TDC is
used, the in-band and out-band phase noise are about −91 dBc/Hz @10 kHz offset
and −128 dBc/Hz @1 MHz offset, respectively. The in-band noise performance is
better than that of ADPLL without  TDC by 17.29 dBc/Hz.
The TDC quantization effect mainly affects the in-band phase noise of ADPLL.
As analyzed in [5], the phase noise spectrum at the ADPLL output due to the TDC
quantization effect can be determined by
ð2TLSB Þ2 Ndiv FDCO
L¼ ð1Þ
12
where TLSB is the TDC resolution, Ndiv is the dividing ration of the divider, and
FDCO means the output frequency of DCO. In this work, the reference clock is
20 MHz. Substituting FDCO ¼ 2:4 GHz and TLSBðpipelineÞ ¼ 1:6 ps, the phase noise
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(a)

(b)

Fig. 8. ADPLL output phase noise: (a) with  TDC, (b) without 
TDC

without  TDC is about −116 dBc/Hz. Substituting TLSB ¼ 0:23 ps again, L ¼

133 dBc/Hz. An in-band noise performance improvement of 17 dBc/Hz is
achieved, which coincides well with the measurement results.

© IEICE 2017
DOI: 10.1587/elex.14.20170095
Received February 5, 2017
Accepted February 13, 2017
Fig. 9. ADPLL jitter performance
Publicized February 27, 2017
Copyedited March 25, 2017

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Table I. Performance comparison with prior works

[2] JSSC [4] CAS1 [6] ELEX [10] ISSCC This work
TDC Resolution (ps) 6 4 15.6 N/A 0.23
Frequency (Hz) 3.67 G 2.4 G 1.6 G 2.4 G 2.4 G
In-band Phase noise −102 @ −75 @ −90 @ −91 @
N/A
(dBc/Hz) 12 kHz 10 kHz 10 kHz 10 kHz
Out-band Phase noise −131.5 @ −104.6 @ −109 @ −128 @
N/A
(dBc/Hz) 3 MHz 10 MHz 10 MHz 1 MHz
RMS Jitter (ps) 0.2 4 3.9 3.29 2.9
Power (mW) 46.7 14.4 9.1* 6.4 12
Technology (nm) 130 130 90 40 130

under a 0.6-V supply

The jitter performance at 2.4 GHz is shown in Fig. 9, the RMS jitter is 2.9 ps
and the peak-peak jitter is 21.5 ps. Table I summarized the performance comparison
with prior works.

5 Conclusion
A 2.4 GHz ADPLL for Zigbee application is presented. The TDC that based on
pipeline and  structure achieves a high resolution up to 0.23 ps and third-order
noise shaping simultaneously. The chip was fabricated in a 0.13-µm CMOS
technology and occupies 0.49 mm2, including a bandgap reference circuit. The
measured results showed that the ADPLL featured a −91 dBc/Hz in-band phase
noise and a 2.9 ps RMS jitter. The total power consumption is 12 mW under a 1.2-V
supply.

Acknowledgments
This work was financially supported by the Natural Science Foundation of Jiangsu
(BK20130880 & BK20150848), Nanjing University of Posts and Telecommuni-
cations Foundation NUPTSF (Grant No. NY214156), and the National Natural
Science Foundation of China (No. 61504061 & 61501261 & 61504065 &
61601239).

© IEICE 2017
DOI: 10.1587/elex.14.20170095
Received February 5, 2017
Accepted February 13, 2017
Publicized February 27, 2017
Copyedited March 25, 2017