A 12 mW All-Digital PLL Based on Class-F DCO for 4G Phones in 28 nm CMOS

Feng-Wei Kuo1 , Ron Chen1 , Kyle Yen1 , Hsien-Yuan Liao1 , Chewn-Pu Jou1 , Fu-Lung Hsueh1 ,
Masoud Babaie2 , Robert Bogdan Staszewski2
1 TSMC, Hsinchu, Taiwan. 2 Delft University of Technology, Delft, The Netherlands. email: fwkuo@tsmc.com

0.9
Abstract

Coupling Factor
Transformer s
We propose a new architecture of an all-digital PLL (AD- 0.8 (w/i fill)
PLL) for advanced cellular radios that is optimized for 28 nm (w/o fill)
0.7
CMOS. It is based on a wide tuning range, fine-resolution
class-F DCO with only switchable metal capacitors and a 0 5 10 15 20 25 30

phase-predictive TDC. The 8 mW DCO emits -157 dBc/Hz at 20

Qs (w/o fill)

Transformer s Q-factor
Transformer s windings
20 MHz offset at ∼2 GHz, while fully satisfying metal density 2.5
15
Qs (w/i fill)

inductance (nH)
2 Ls (w/i fill) Qp (w/o fill)
rules. The 0.4 mW TDC clocked at 40 MHz achieves PVT- Ls (w/o fill)
1.5 10
stabilized 6 ps resolution for -108 dBc/Hz in-band phase noise.
1 Qp (w/i fill)
FREF spur is ultra-low at <-94 dBc. The ADPLL supports a Lp (w/o fill) Lp (w/i fill) 5
0.5
2-point modulation and consumes 12 mW while occupying
0 0
0.22 mm2 , thus demonstrating both 72% power and 38% area 0 5 10 15 20
Freq (GHz)
25 30 0 5 10 15 20 25
Freq (GHz)
30

reductions over prior records.

Fig. 1. Effects of dummy metal fills on the 28 nm CMOS class-F transformer.
Introduction PVT LSBs 3

Voltage waveforms
Tracking bank
(C1)
While mobile phones enjoy the largest production vol- 2
ume ever of any consumer electronics product, the demands Cf3 Bf3 Cf3
1
they place on frequency synthesizers are particularly tough, Cf0 Bf0 Cf0 VD1 VD2
0
especially on integration with digital processors, low area,
VD1 Lp VDD Lp VD2 VG2 VG1
low-power consumption, low phase noise and virtually no -1

spurs, while being robust against PVT variations. In this Km 0 (b) 2π

M1 M2
difficult design environment, the all-digital PLLs (ADPLLs) Ls

VG2
VG1

VB Ls
1
Traditional Oscillator
have shown to outperform analog PLLs in terms of area and ID1

ISF function
CC0 BC0 CC0 ID2 0.5
power dissipation while having best-in-class RF performance Proposed Class-F
[1]. These advantages are expected to continue improving with CC3 BC3 CC3 0

CMOS scaling, although each process node presents a unique -0.5

3
set of challenges. In this paper, we propose and demonstrate PVT MSBs M3 CT
Switched -1
a new ADPLL architecture optimized to the most advanced (C2)
Resistors
0 (c) 2π

production low-leakage CMOS technology (i.e., 28 nm). The (a)

digitally controlled oscillator (DCO) addresses the new strict
metal density rules and exploits better gm/C of switches
to improve tuning range and resolution. The time-to-digital
converter (TDC) uses phase prediction to improve resolution
and lower the required linear range, thus saving power.
Class-F Digitally Controlled Oscillator (DCO)
The 28 nm CMOS technology has strict requirements on
design for manufacturing (DFM), especially the 25–50%
minimum metal density rule, which is much stricter than in
the previous 40 nm node. Hence, inductors and transformers
must include a lot of dummy metal pieces on all metal layers.
EM simulations of a transformer used in this design are
shown in Fig. 1. Metal fills show negligible effect on the
windings self-inductance and coupling factor km . However,
Eddy currents in the dummy fills increase the resistive loss
and thus transformer’s Q-factor is degraded by 10–20%.
Dummy fills also increase the capacitance, thus degrading
the self-resonant frequency. Furthermore, the excess noise of
transistor, γ, is also increased. Consequently, both phenomena
hurt the operation of an RF oscillator.
Recently introduced class-F oscillator [2], as shown in
Fig. 2, addresses the above issues by: (1) enforcing a pseudo-
square voltage across the tank, thus reducing the impulse
sensitivity function (ISF), and (2) exploiting the transformer’s
voltage gain, G0 . The phase noise is less sensitive to the loss
of the tank due to its lower ISF, while the effective noise
factor of the gm-devices is reduced by G0 . Consequently, the
Fig. 2. Schematic of the class-F DCO with voltage waveforms and ISF.
new structure offers ∼4 dB improvement over the traditional
oscillator at the same VDD and tank’s Q-factor. The pseudo-
square waveform is realized by increasing the 3rd harmonic
of the fundamental oscillation voltage through an additional
impedance peak and strong 3rd harmonic of the drain cur-
rent. The transformer along with tuning switched capacitors
realizes a 4th-order tank with two resonant frequencies, in
which the first one determines the oscillation frequency, ω0 ,
and second one should be adjusted around 3ω0 to enforce
the pseudo-square voltage waveform. The ratio of resonant
frequencies should be 3 with 10% accuracy and controlled
by C2 /C1 for a given transformer with a km < 0.8. On/off
ratio of the tuning capacitors is 8:1. Gm-devices are thick-
oxide transistors to withstand large gate swings. The positive
feedback is realized by a 1:2 step-up transformer with pri-
mary and secondary inductors Lp and Ls , respectively. The
aluminum capping layer is strapped to the top copper layer to
form the windings and improve the transformer’s primary and
secondary Q-factors. PVT banks are divided equally between
Lp and Ls to guarantee the class-F operation over tuning
range, while the tracking bank is located at Lp .
The switched poly resistors, which are digitally friendly and
substantially free of 1/f noise, define the tail current. However,
a small tail resistor could load the LC tank and lower the Q
when the oscillation forces M1 or M2 into the triode region.
Fortunately, tank ISF is negligible during this time span and

978-1-4799-3328-0/14/$31.00 ©2014 IEEE 2014 Symposium on VLSI Circuits Digest of Technical Papers
 Sample

CORDIC
SPI

SRAM
rate Data FCW
conv.
(SRC)

CKS m DCO
CKV/8 gain
FREF normalization
SRC Class-F
LF DCO
Channel RR[k] E[k] tune CKV0-7


FCW 2 8
ZOH

÷4
+ D
- RF
out -94dBc
0
CKS CKV/4 CKV
RV[k]+[k] frac 2 4
m CKV/8 FREF
FREF Slicer
in Variable
FREF CKV0-7 (1.25—2.05 GHz) 40MHz
phase,
TL 1/8 TDC
Slope

Fig. 3. Block diagram of the proposed ADPLL with class-F DCO, phase- (a)
predictive 1/8-length PVT-stabilized TDC, and 2-point frequency modulation.
This CICC'12 JSSC'11 JSSC'12 Units
work [3] [1] [4]
CMOS node 28nm 65nm 65nm 55nm
Supply 1.05 1.2 1.2 1.2 V
Output frequency 1475-2125 1600-2100 1600-2000 1800 MHz
Tuning range 36 27 22 33 %
PLL FOM 187 182.7 184.4 182.9 dB
-108dBc/Hz
PLL FOMT 198 191.3 191.2 193.3 dB
Settling time 2 60 20 79 us
Normal
BW
(AD)PLL current 11 35.5 38 34.6 mA Narrow loop BW
DCO current 7 30 18 27.1 mA Wide BW
PLL w/FM area 0.22 1.3 0.35 0.7 mm2
FOM = |PN| + 20log 10 (f 0 / D f) - 10log 10 (P DC /1mW)
FOMT = |PN| + 20log10((f 0 / D f)(TR/10%)) - 10log10(PDC/1mW)

Fig. 4. Performance comparison with published ADPLLs for cellular phones. fcarrier = 2.0913 GHz
(b)
extensive noise of loaded-Q will not convert to phase noise. Fig. 5. Measured ADPLL spectrum with wide loop bandwidth of 1.8 MHz
The measured FOM of this class-F oscillator is 189 dB. (a); and phase noise (b). The inset in (a) shows the ADPLL die micrograph
It is among best-in-class despite being 3 dB lower than the and the zoomed-in transformer revealing lots of dummy metal fills.
original design in 65 nm [2], where it can support larger VDD
and does not suffer from the lack of thick Cu metal layer requirements of 4G cellular phones. Fig. 5(a) shows the chip
and restrictive metal density rules. It should be noted that a micrograph. Fig. 4 summarizes the ADPLL and compares it
traditional oscillator was also fabricated on the same wafer to state-of-the-art in cellular radios. While keeping the best-
and shows a 3–4 dB lower FOM. in-class RF performance, the area (0.22 mm2 ) and power
consumption (12 mW) are much better (72% and 38%, re-
ADPLL Architecture spectively) than the prior records. The FOM that captures the
Fig. 3 shows a block diagram of the proposed ADPLL, PN normalized to the power consumption of DCO and PLL
which supports a 2-point frequency modulation (FM). The (our DCO and PLL FOMs are 10 log10 (7mA/11mA)=2 dB
∼2 GHz ÷4 divider output of 8 phases, CKV0−7 , oversamples from each other) is much better than prior art, despite the lack
the external frequency reference (FREF) generating CKR0−7 of thick metal and strict density rules. The ADPLL locking
vector clock to sample the variable DCO phase Rv[k]. The range is 36% and its settling time is only 2 us.
CKV0−7 phase closest to the FREF edge is predicted based Fig. 5 shows a representative spectrum and phase noise
on ΣFCW and fed to the TDC covering the range of 1/8 DCO (PN). An ultra-low FREF spur of -94 dBc is measured with no
period. The reduced required range allows to significantly other significant spurs observed. PN at 20 MHz offset from the
improve the TDC resolution and linearity while reducing its ∼2 GHz carrier is -157 dBc/Hz and can be further improved
current consumption. Each TDC delay unit (i.e., inverter) is with higher current. PN was measured for three different
loaded by a digitally controlled capacitor to normalize the ADPLL loop bandwidths: narrow (80 kHz), normal (250 kHz)
delay, and thus to stabilize the resolution at 6 ps. and wide (2.5 MHz). The in-band PN of -108 dBc/Hz in wide
The normalized TDC output, [k], is combined with RV [k] bandwidth corresponds exactly (according to Eq. 2 in [1])
before being subtracted from the reference phase RR [k] = to the TDC quantization noise at 6 ps resolution at 40 MHz
ΣF CW to calculate the phase error, φE [k]. To avoid metasta- FREF, while showing no other noise sources. The measured
bility in FREF retiming, FREF is simultaneously oversampled integrated jitter of 253 fs corresponds to the total integrated
by different phases of CKV and an edge selection signal PN of 0.18o . The in-band PN varies only 0.5 dB over the full
chooses the path farther away from metastability. The PHE frequency range and gets worse by 1 dB when the temperature
is fed to the type-II loop filter (LF) with 4th order IIR. The increases from -40o C to 120o C.
LF is dynamically switched during frequency acquisition to
minimize the settling time (measured: 2 us). The FREF slicer R EFERENCES
[1] R. B. Staszewski, et al., “Spur-free multirate all-digital PLL for mobile
contains a 3-bit slope control to reduce the FREF spurs. phones in 65nm CMOS,” IEEE JSSC, vol. 46, no. 12, pp. 2904–2919,
Built-in DCO gain, KDCO , and TDC gain, KT DC , LMS- Dec. 2011.
type calibrations are autonomously performed to ensure the [2] M. Babaie and R. B. Staszewski, “A class-F CMOS oscillator,” IEEE
JSSC, vol. 48, no. 12, pp. 3120–3133, Dec. 2013.
wideband FM response and suppression of fractional spurs. [3] K. Ueda, et al., “A digital PLL with two-step closed- locking for multi-
Measurement Results and Conclusion mode/multi-band SAW-less transmitter,” IEEE CICC Conf., pp. 1–4,
Sept. 2012.
The proposed ADPLL is implemented in 28 nm digital [4] L. Vercesi, et al., “A dither-Less all digital PLL for cellular transmitters,”
CMOS and meets the tough phase noise (PN) and spurious IEEE JSSC, vol. 47, no. 8, pp. 1908–1920, Aug. 2012.

2014 Symposium on VLSI Circuits Digest of Technical Papers