IRAware STAAnalysis

IR Drop Aware STA Analysis
Product Version - Voltus 15.2, Tempus 15.2

February 15, 2016
Copyright Statement
© 2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are
registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective
holders.
Learn more at Cadence Online Support - http://support.cadence.com

© 2016 Cadence Design Systems, Inc. All rights reserved worldwide. Page 2
Contents
Purpose ....................................................................................................................... 4
Audience ...................................................................................................................... 4
Overview ...................................................................................................................... 4
The Basic VOLTUS/TEMPUS Flow ............................................................................. 5
IR Drop effect on delays .............................................................................................. 6
VOLTUS setup for power and IR Drop ........................................................................ 7
Library Setup ............................................................................................................. 12
Skew Analysis ........................................................................................................... 14
Jitter Analysis ............................................................................................................ 19
IR Drop aware critical path analysis using Spice ....................................................... 21
Summary ................................................................................................................... 26
Support ...................................................................................................................... 26
Feedback ................................................................................................................... 26

Purpose
The purpose of this document is to educate designers about what is IR Drop Aware
STA Analysis, how it is implemented, and when to utilize it.
Audience
The audience for this IR-Aware STA document are design teams wanting to determine
the estimated timing for IR drop violators. IR Drop Aware STA Analysis does not
physically fix any IR drop violations in your design. It is not intended to be used for
massive IR Drop violations (greater than 20% of supply voltage). It is intended to show
the STA Analysis for non-ideal voltage.
Overview
Designing a robust power grid has become a major challenge with shrinking technology
allocating more performance in a smaller area.
The power distribution on a semiconductor has to ensure circuit robustness for the
power/current requirements, as well as timing and reliability of the design. IR Drop on
power rails can significantly affect standard cell and net delays. The drop in voltage of
the power grid degrades transitions dynamically in the design. The variation can span
from within a clock cycle or clock cycle to clock cycle as you can see in Figure 1.
Figure 1. IR Drop within a Timing Window.
The delay variations due to IR Drop impacts both cell and net delays in clock and data
paths as can be seen in Figure 2. Typically, the drop in voltage leads to a slower
transition through the standard cell or IP.
Figure 2. Delay Variability.

The Basic VOLTUS/TEMPUS Flow
VOLTUS
IR Drop Analysis
Delay comparison
TEMPUS between Spice vs.
TEMPUS delay calculation
Spectre
Figure 3. Basic VOLTUS/TEMPUS Flow.
The delay variance in data path and clock paths adversely impacts the setup and hold
timing checks. TEMPUS supports skew analysis to check the effect of IR Drop on the
clock arrival times at different register pins. It also supports jitter analysis to check late
and early arrival times at a particular register. Figure 3 shows the flowchart for using
VOLTUS and TEMPUS in running IR Drop Aware STA. Detailed discussion on skew
and jitter analysis is covered in the later sections of this document.
VOLTUS can perform the min and max IR Drop analysis based on the low and high
switching activities and derives the effective min/max operating voltages for every
instance in the design. The VOLTUS-related scripts are on the pages 8-10 of this
document. These specific instance effective operating voltages will be written into the
files which will be referred to as low activity or high activity IR Drop files in this
document. The low_activity/high_activity IR Drop files can be read in TEMPUS using
the read_instance_voltage command. These instance-based min and max voltages will
be used during delay computation for respective corners, and perform various checks
using these delays.
TEMPUS can also run spice simulations for the given timing path and compare delays
against the delays computed using the cell level delay models. TEMPUS creates a
constant voltage source for each instance with voltage specified in the IR Drop files. On
the other hand, VOLTUS can generate detailed power and ground voltage waveforms
for each instance, which can be inputted into TEMPUS. TEMPUS will use these
waveforms to create a piece-wise linear voltage waveform for each instance.

IR Drop effect on delays
Figure 4. IR Drop effect on delays.
IR Drop can affect both net and cell delays. Because the peak voltage is reduced, IR
Drop voltage swing range will be smaller than nominal voltage, and hence will affect the
net delay and input slew at the receiver. As you can see in Figure 4, when the voltage is
ideal, your slew is different than when the effective voltage is lowered because of IR
Drop.
As shown in figure 4, assume that the driver is operating at nominal voltage, Vdd, and
receiver is operating at the VirDrop voltage. Also, assume the following trip points set in
timing library: Lower slew threshold = 20%, Upper slew threshold = 80%, Input
threshold = 50% and output threshold = 50%. The net delay with nominal voltage swing
is smaller than the delay computed with IR Drop voltage because the signal waveform
propagates across the net. This example also shows the variance in input slew at the
receiver. Because the cell delay is a function of input slew and output load, the cell
delay will also be affected. Apart from input slew, the cell delays derived from the
library, which is characterized for nominal voltage, will be degraded because of IR Drop
voltages. For accurate delay modeling, Cadence recommends the use of multiple
libraries characterized with different operating voltages. These libraries are referred to
as TriLibs in this document.
Important Note: irDrop files created in VOLTUS include irDrop voltages for all the
instances in design, <block.iv>. However, it is important to specify nominal voltage for the
design using the create_op_cond and set_op_cond commands. Otherwise, IO ports are
assumed to be at the same voltage as the first cell in their fan-out cone. This will cause
inconsistency with spice netlist created in TEMPUS.
In using the tri-lib flow, make sure you are using libs from the same process corner with
different voltages, for example: slow_1.0V_125C.lib, slow_0.9V_105C.lib,
slow_0.8V_25C.lib.

VOLTUS setup for power and IR Drop

Clock jitter analysis requires minimum and maximum voltage for each instance in the
design. To achieve this, IR Drop analysis is run with minimum and maximum activity,
which translates to min and max power for the design. This power is fed to IR Drop
analysis to generate min and max voltage for each instance in the design as shown in
Figure 5.
Figure 5. Min and Max activity flow in VOLTUS.
The min activity during power analysis is defined by turning off the activity of
combinational logic and toggling only the clock network. This is achieved by setting
negligible activity (1%) on the primary inputs and the output of the sequential logic. If the
design has gated clock, it should be enabled. Review the set_default_switching_activity
command in the following example script.
Note: Specifying 0% activity does not currently work, because power analysis will
revert to the default activity of 20% in this case.

The max activity during power analysis is defined as the expected average activity on
the primary inputs and the output of sequential logic. In addition, gated clocks are
disabled.
Alternately, if VCD is available with low and high activity cycles, it can be specified in
VOLTUS using the “read_activity_file” command with start and stop times. Optionally,
you can find high or low activity cycles by profiling the VCD file using the
“report_vcd_profile” command.
Example VOLTUS script for the flow is shown here. It is a vectorless VOLTUS script:
#######################################################
# VOLTUS Script
# Purpose: Dynamic analysis at min and max activity
# Run, >Voltus -init script.tcl
#######################################################
# Import design
read_lib –lef <lef files>
read_lib –min <min libraries>
read_lib –max <max libraries>
read_verilog <logical netlist>
set_top_module <top cell>
read_sdc <timing constraints>
read_def <physical netlist>
read_spef <signal parasitics>
#The set_dc_sources commands AREN’T REQUIRED if all of the libs you read in are at the same voltage
set_dc_sources VDD -power -voltage 1.0
set_dc_sources VSS -ground
# Power analysis
set_power_analysis_mode \
-method dynamic_vectorless \
-corner min \
-create_binary_db true \
-write_static_currents true
# dynamic power @low activity

set_default_switching_activity -input_activity 0.01 -seq_activity 0.01 \
-clock_gates 1.0 -period 4.0
set_power_output_dir ./dynamic_power_low_activity
report_power
# dynamic power @high activity

# Power analysis
set_power_analysis_mode -reset

set_power_analysis_mode \
-method dynamic_vectorless -create_binary_db true \
-corner max -write_static_currents true
set_default_switching_activity -input_activity 0.25 -seq_activity 0.25 -clock_gates 0.0 -period 4.0

set_power_output_dir ./dynamic_power_high_activity
report_power
# IR Drop analysis
set_rail_analysis_mode \
-method dynamic \
-accuracy hd \
-extraction_tech_file qrcTechFile \
-temperature 25 \
-enable_rlrp_analysis true \
-generate_movies true \
-save_voltage_waveforms true \
-power_grid_library {../data/pgv_dir/tech_pgv/techonly.cl \
../data/pgv_dir/stdcell_pgv/stdcells.cl ../data/pgv_dir/macro_pgv/macros_pll.cl}
# Power nets, domain and IR Drop threshold

set_pg_nets \
-net VSS \
-voltage 0.0 \
-threshold 0.05 \
-tolerance 0.3
set_pg_nets \
-net VDD \
-voltage 1.0 \
-threshold 0.95 \
-tolerance 0.3
set_rail_analysis_domain \
-name core \
-pwrnets VDD \
-gndnets VSS
# Power pad location

set_power_pads \
-net VDD \
-format xy \
-file ../DATA/powerpads/VDD.pp
set_power_pads \
-net VSS \
-format xy \
-file ../DATA/powerpads/VSS.pp

# IR Drop anlaysis @low_activity power

set_power_data \
-format current \
-scale 1 \
{ dynamic_power_low_activity/dynamic_VDD.ptiavg \
dynamic_power_low_activity/dynamic_VSS.ptiavg }
analyze_rail -type domain -results_directory ./dynamic_rail_low_activity core
# IR Drop analysis @high_activity power

set_power_data -reset
set_power_data -format current -scale 1 \

{ dynamic_power_high_activity/dynamic_VDD.ptiavg \
dynamic_power_high_activity/dynamic_VSS.ptiavg }
analyze_rail -type domain -results_directory ./dynamic_rail_high_activity core

##################### END #######################################
The instance voltage file, which has the effective voltage AFTER IR Drop, will be
outputted and has a .iv extension. It is saved under IR Drop results directory, for
example, “core_25C_dynamic_1/core.iv”. The instance voltage is determined using
power and ground IR Drop waveforms inside the switching window of the instance as
shown in Figure 6. It is also referred to as effective instance voltage.
Figure 6. Minimum Operating Voltage.

This file can be read in TEMPUS/VOLTUS using the “read_instance_voltage” command

as discussed in the subsequent sections of clock jitter and skew analysis. The instance
voltage can be displayed in the context of the layout using the “view_analysis_results”
command as well. For example:
view_analysis_results -state_directory core_25C_dynamic_1/VDD

view_analysis_results -effective_iv_file core_25C_dynamic_1/core.iv
view_analysis_results -plot eiv
Figure 7. Example IR Drop picture showing highest IR drop across the power grid in RED.
In addition to instance voltage, IR Drop waveforms are also stored inside IR Drop
results directory, for example, “core_25C_dynamic_1/VDD/VDD.ptiavg and
VSS/VSS.ptiavg”. These voltage waveforms can be used for critical path analysis using
SPICE in TEMPUS as described in the subsequent sections.
If dynamic power and IR Drop analysis are done using vector-based method, you might
be required to shift these waveforms during critical path analysis using the
“create_spice_deck” command. This will be required to align IR Drop waveform with the
clock edges of SDC. The IR Drop waveform for instance can be viewed using the TCL
command in VOLTUS, for example, “view_dynamic_waveform”.
view_dynamic_waveform \
-type voltage \
-waveform_files \
{core_25C_dynamic_1/VDD/VDD.ptiavg core_25C_dynamic_1/VSS/VSS.ptiavg} \
-effective_voltage_waveform \
-instance_name inst1
Figure 8. Instance Voltage waveforms.
Library Setup
Multiple libraries characterized with different operating voltages (triLibs) can be read into
TEMPUS. Delay calculator computes an instance delay by interpolating delays between
two libraries that are close to IR Drop voltage of that particular instance. For example, if
user loaded libraries characterized for 1.0volts, 0.9volts and 0.8volts, Delay calculator
uses 1.0v and 0.9v libraries for all instances with IR Drop < 1.0v and > 0.9v.
The triLibs s can be loaded into TEMPUS in following three ways:
1. Reading libraries using read_lib commands
read_lib [list [list ../data/libs/slow.lib_0.9V_ecsm\

../data/libs/slow.lib_0.8V_ecsm\
../data/libs/slow.lib_1.0V_ecsm] \
../data/libs/pll.lib\
../data/libs/bufao.lib\
../data/libs/pso_header.lib\
../data/libs/pso_ring.lib]
Libraries with same cells characterized for different voltages should be grouped into a
separate list. From example 1, libraries scmetro_cmos10lp_hvt_ss_*,
scmetro_cmos10lp_lvt_ss_* and scmetro_cmos10lp_rvt_ss_*, which have three
libraries characterized for 1.0v, 0.9v and 0.8v are grouped into a list. The list can be
mixed with other libraries like pllclk_slow.lib, which is not characterized with multiple
operating voltages.
2. MMMC setup
triLibs can be specified while creating TEMPUS libraries for particular corner.
create_library_set –name max_corner \

[list [list ../data/libs/slow.lib_0.9V_ecsm\
3. read_design: configuration file
Libraries can be loaded into TEMPUS via the configuration file which exists in the
save database. Following syntax should be used in the configuration file to load
triLibs via read_design:
set rda_Input (ui_timelib) [list [list ../data/libs/slow.lib_0.9V_ecsm\

Important Note: For better accuracy, it is recommended that the difference

between the two adjacent libraries should not be more than 20%. Also, better
delay accuracy be achieved by reducing this difference at lower operating
voltages.
Important Note: The voltage range of characterized libraries should cover min
and max irDrop voltages. If irDrop voltages of an instance falls outside this range,
extrapolation is not supported. Instead, TEMPUS adjusts the voltage to the
closest value. For example, you read libraries characterized for 0.8, 0.9 and 1.0
and a particular instance IrDrop voltage is 1.1 volt. TEMPUS computes the delays
for this instance based on 1.0 volt.

Skew Analysis
Figure 9. Skew Analysis and IR Drop impact on SKEW.
Skew is the difference in arrival times of the clock at the launch and capture registers. In
the on-chip variation mode, the launch flop uses late paths and capture flop uses early
paths. Late path delays are computed based on IR Drop observed during high switching
activity, and Early path delays are computed based on IR Drop observed during low
switching activity as can be seen in Figure 9. High switching activity resulting into a
higher voltage drop means lower operating voltages. Lower operating voltages result in
larger net/cell delays. Low switching activity resulting into lower voltage drop means
higher operating voltages (but less than the nominal voltage). Higher operating voltages
result in smaller net/cell delays.

Clock skew analysis can be performed in TEMPUS using the report_clock_timing –type
skew command.
Example TEMPUS script for the flow is shown here:
#######################################################
# TEMPUS SCRIPT FOR IR-AWARE-STA
# BASIC SCRIPT TO RUN STA
#######################################################
#READ IN THE DESIGN

read_design -physical_data ../design/postRouteOpt.enc.dat/ super_filter
#setting the value for the dc sources

set_dc_sources VDD -power -voltage 1.0
set_dc_sources VSS -ground -voltage 0.0
#######################
# IDEAL VOLTAGE TIMING ANALYSIS
#######################
#setting the Analysis View to be analyzed

set_analysis_view -setup [list single_lib_wc] -hold [list single_lib_wc]
set_delay_cal_mode -siAware false
report_timing -path_type full_clock -format "instance arc cell voltage delay slew" >
NOIR.worst.tim.rpt
report_analysis_summary > Ideal.summary.rpt
report_clock_timing -type skew > Ideal_skew.rpt
report_clock_timing -type jitter > Ideal.jitter.rpt
########################
# IR AWARE TIMING ANALYSIS
########################
set_analysis_view -setup [list TRILIB_wc] -hold [list TRILIB_wc]
report_timing -path_type full_clock -format "instance arc cell voltage delay slew" >
IR.worst.tim.rpt
report_analysis_summary > IR.summary.rpt
report_clock_timing -type skew > IR_skew.rpt
report_clock_timing -type jitter > IR_jitter.rpt

To set the TRILIB_wc view, there needs to be three different libs at three different
voltages. You can see the following had to be created in viewDefinitions.tcl:
1) create_library_set -name TRILIB_wc\

-timing\
[list [list ../data/libs/slow.lib_0.9V_ecsm\
../data/libs/slow.lib_1.0V_ecsm] ../data/libs/pll.lib\
2) create_rc_corner -name RC_wc_125\

-cap_table ../gpdk090.lef.extended.CapTbl\
-T 125\
-qx_tech_file ../data/qrc/gpdk090_9l.tch
3) create_delay_corner -name TriLib_wc\

-rc_corner RC_wc_125\
-library_set TRILIB_wc\
-opcond_library slow\
-late_irdrop_file HIGH_ACTIVITY_125C_dynamic/VDD_VSS.iv \
-early_irdrop_file LO_ACTIVITY_125C_dynamic/VDD_VSS.iv
The difference between viewDefinitions with single libs and viewDefinitions with
TRI_libs is given in the following example:
Figure 10. Difference of viewDefinition.tcl files for single libs and Tri-libs.
As you can see in Figure 10, the library set for the single library was Single_wc. The
library set for the tri-lib library was TRILIB_wc. You can see the difference in the number
of libs being used in the tri-lib flow. Voltages for the libs are 1.0V, 0.9V, and 0.8V.
The following report shows the clock skew for a register pair. The report shows the
skew and latency values are less without the impact of IR Drop once IR Drop is factored
in the delays are larger.

The datapath delays are slower once IR drop is utilized as can be seen in the following
paths:
Delay reported for instance DTMF_INST/RESULTS_CONV_INST/g6001 without

IRDrop is 0.277 ns for both late and early paths. When the min/max IR Drop files are
provided, IR drop caused the instance DTMF_INST/RESULTS_CONV_INST/g6001
delay to increase from 0.277 ns to 0.298 ns for late path (using max delays) and 0.284
ns for early path (using min delays).
Overall there is a 22 ps timing increase due to IR Drop.

Jitter Analysis
Figure 11. Jitter Analysis view.
Jitter is the difference in late and early arrival times of clock phase at a register clock
pin.
In the on-chip variation mode, the launch flop uses late paths and capture flop uses
early paths. Late path delays are computed based on IR Drop observed during high
switching activity, and Early path delays are computed based on IR Drop observed
during low switching activity. High switching activity resulting into higher voltage drop
means lower operating voltages. Lower operating voltages result in larger net/cell
delays. Low switching activity resulting into lower voltage drop means higher operating
voltages (but less than the nominal voltage). Higher operating voltages result in smaller
net/cell delays. Clock jitter analysis can be performed in TEMPUS using the
report_clock_timing –type jitter command.

Clock Jitter reports without IR Drop files

As can be seen in the following clock jitter reports, IR Drop impacts the amount of jitter
and latency. In the reports, the variability min/max delays due to IR Drop increases the
amount of jitter but decreases the amount of latencies on the clocks.

IR Drop aware critical path analysis using Spice

TEMPUS supports IR Drop aware spice analysis of timing paths. TEMPUS writes out
sensitized spice Netlist for a given timing path and invokes Spectre simulator to do
spice simulations. Upon completion of spice simulations, TEMPUS reads back the spice
report and generates a delay comparison table between spice delays and TEMPUS
internal delay calculator.
When IR Drop files are read into TEMPUS, it automatically creates a constant voltage
source for each instance in spice Netlist with voltage specified in the IR Drop file for that
particular instance. Alternately, you can input dynamic voltage waveforms of power and
ground nets to TEMPUS path simulator for TEMPUS to create a piece-wise linear
waveform form for power and ground nets.
Running spice simulations with constant IR Drop voltage per instance

Spice deck created using the create_spice_deck command after reading IR Drop files
automatically creates constant voltage source for each instance. Here is the syntax of
create_spice_deck command:
create_spice_deck [-report_timing {report_timing_options} \

-power {power nets} -ground {ground nets} \
-model_file <spice model files> \
-subckt_file <spice sub circuit file> \
-outdir <output directory for spice run>\
-run_path_simulation
Example:
create_spice_deck [-report_timing {-from i_5/CK –path_type full_clock}\

-power {VDD VNW} -ground {VSS VPW} \
-model_file "spmodels.sp" \
-subckt_file "cmos10lphvt_m.cdl" \
-outdir path_spice_deck_max \
Note: To be able to run Spectre simulator, it should be in your search path, or you can
use the –spectre option to specify full path to Spectre.

Running spice simulations with dynamic IR Drop voltage

waveforms per instance
VOLTUS writes out dynamic voltage waveforms for each instance in a file. The
create_spice_deck command can parse these files and write these as piece-wise linear
waveform in spice deck.
Here is the option for inputting IR Drop waveform files to the create_spice_deck
command
-irdrop_waveforms <list of IR Drop waveform files>:
- irdrop_waveforms {$rootDir/irDrop/VDD/VDD.ptiavg $rootDir/irDrop/VSS/VSS.ptiavg}
While performing critical path analysis with dynamic IR Drop waveforms, you have to
align the IR Drop waveform with launching clock edge. User can use the –offset option
to specify the offset of IR Drop waveform from/to the launch clock edge. This option has
to be used along with the –irdrop_waveforms option.
If the duration of IR Drop waveforms derived from VOLTUS is smaller than the required
spice simulations time, create_spice_deck concatenates the waveform consecutively.
The number of repetitions can be chosen by specifying a number to the –repeat option.
This option has to be used along with the –irDrop_waveforms option.

Example Flow Script for non-MMMC Mode:
#Load the design

read_design simple.conf
#Set analysis mode to on chip variations

set_analysis_mode –analysisType onChipVariation
# Read parasitics information

read_spef simple.spef
#Set nominal voltage.

# if required, user can create operation condition with required PVT values
# create_op_cond –name triLib_nominal –library_file dtmf_hvt_10v.lib –P 1 –V 1.0 –T 125
set_op_cond typical –library elc_10v
#input max and min irDrop files

read_instance_voltate –max –infile simple_max.iv
read_instance_voltate –min –infile simple_min.iv
#Analyze setup and hold timing of critical paths

report_timing –late –path_type full_clock
report_timing –early –path_type full_clock
#Analyze clock skew

report_clock_timing –type skew –nworst 10 –verbose
#Analyze clock jitter

report_clock_timing –type jitter –nworst 10
#check data path delays from spice with original STA report
create_spice_deck –report _timing {-from i_5/CK –late –path_type full_clock} \
-outdir path_spice_deck_max –power {VDD VNW} –ground {VSS VPW} \
-model_file “spmodels.sp” -subckt_file cmos10lphvt_m.cdl \
#check clock path delays from spice with original STA report
create_spice_deck –report _timing {-from i_5/CK –early –path_type full_clock} \
-outdir path_spice_deck_max –power {VDD VNW} –ground {VSS VPW} \
-model_file “spmodels.sp” -subckt_file cmos10lphvt_m.cdl \

Spice Comparison Reports

The previous scripts create spice decks and reported timing through specific paths. The
format of those paths can be seen in the following reports. These spice-created timing
reports give detailed information through the specific paths.


Summary
IR Drop adversely affects STA. The reason for utilizing IR-Drop Aware STA is to provide
the users with timing reports based on IR-Drop. IR-Drop Aware STA is executed at non-
ideal voltage whereas normal STA is based on ideal voltage. IR-Drop Aware STA is
more accurate version of STA because the voltage is not ideal.
Support
Cadence Online Support provides access to support resources, including an extensive
knowledge base, access to software updates for Cadence products, and the ability to
interact with Cadence Customer Support. Visit http://support.cadence.com.
Feedback
Email comments, questions, and suggestions to content_feedback@cadence.com.


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IR Drop Aware STA Analysis

Product Version - Voltus 15.2, Tempus 15.2

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Figure 1. IR Drop within a Timing Window.

Figure 2. Delay Variability.

The Basic VOLTUS/TEMPUS Flow

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IR Drop effect on delays

Figure 4. IR Drop effect on delays.

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VOLTUS setup for power and IR Drop

Figure 5. Min and Max activity flow in VOLTUS.

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# dynamic power @low activity

# dynamic power @high activity

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set_default_switching_activity -input_activity 0.25 -seq_activity 0.25 -clock_gates 0.0 -period 4.0

# Power nets, domain and IR Drop threshold

# Power pad location

Learn more at Cadence Online Support - http://support.cadence.com

# IR Drop anlaysis @low_activity power

analyze_rail -type domain -results_directory ./dynamic_rail_low_activity core

# IR Drop analysis @high_activity power

set_power_data -format current -scale 1 \

analyze_rail -type domain -results_directory ./dynamic_rail_high_activity core

Figure 6. Minimum Operating Voltage.

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This file can be read in TEMPUS/VOLTUS using the “read_instance_voltage” command

view_analysis_results -state_directory core_25C_dynamic_1/VDD

Figure 8. Instance Voltage waveforms.

1. Reading libraries using read_lib commands

read_lib [list [list ../data/libs/slow.lib_0.9V_ecsm\

create_library_set –name max_corner \

3. read_design: configuration file

set rda_Input (ui_timelib) [list [list ../data/libs/slow.lib_0.9V_ecsm\

Important Note: For better accuracy, it is recommended that the difference

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Figure 9. Skew Analysis and IR Drop impact on SKEW.

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Example TEMPUS script for the flow is shown here:

#READ IN THE DESIGN

#setting the value for the dc sources

#setting the Analysis View to be analyzed

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1) create_library_set -name TRILIB_wc\

2) create_rc_corner -name RC_wc_125\

3) create_delay_corner -name TriLib_wc\

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Delay reported for instance DTMF_INST/RESULTS_CONV_INST/g6001 without

Overall there is a 22 ps timing increase due to IR Drop.

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Figure 11. Jitter Analysis view.

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Clock Jitter reports without IR Drop files

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IR Drop aware critical path analysis using Spice

Running spice simulations with constant IR Drop voltage per instance

create_spice_deck [-report_timing {report_timing_options} \

create_spice_deck [-report_timing {-from i_5/CK –path_type full_clock}\

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Running spice simulations with dynamic IR Drop voltage

- irdrop_waveforms {$rootDir/irDrop/VDD/VDD.ptiavg $rootDir/irDrop/VSS/VSS.ptiavg}