VLSI Crash Course Synthesis - 2019

NTU GIEE EECS
VLSI Crash Course

Synthesis
Li-Yang Huang
Jul. 18, 2019
NTU GIEE EECS
Reference
 VLSI Crash Course Synthesis 2018 Yi-Long
Liou
2
NTU GIEE EECS
Outline
 Introduction
 Synopsys Graphical Environment
 DC-TCL: Introduction
 Setting Design Environment
 Setting Design Constraints
 Synthesis Report and Analysis
 Gate-Level Simulation
3
NTU GIEE EECS
Outline
 Introduction
4
NTU GIEE EECS
Cell-Based Design Flow

Implenentation Verification
RTL code
always @ (posedge clk) RTL Simulation
if (in1==1) Lint check
a=c+d code coverage
else analysis
a=c-d
Logic synthesis Formal
Gate-Level netlist
Gate level Simulation
Static Timing Analysis
Power Analysis
Formal
Post layout Gate level Simulation
Place&Route
Gate-Level netlist Static Timing Analysis
Power Analysis
transistor netlist
LVS
GDS layout
Extraction
DRC Transistor-level Simulation

Transistor-level STA
Tape out
Power Analysis
5
NTU GIEE EECS
Synthesis Design Flow

 Develop the HDL design description
and simulate the design description
Specification
to verify that it is correct
 Set up the .synopsys_dc.setup file. RTL Coding Prepare
 Set the appropriate technology,
synthetic, and symbol libraries, target
libraries, and link libraries.
Setting Design Environment
 Set the necessary compilation
options, including options to read in
the input files and specify the output
formats. Setting Design Constraint
 Read the HDL design description
Cell
 Define the design. Library Compile Design
 Set design attributes
 Define environmental conditions
 Set design rules Analysis
 Set realistic constraints
(timing and area goals)
 Determine a compile methodology Gate-level Cell-based Netlist
6
NTU GIEE EECS
What is Synthesis
 source /usr/cad/synopsys/CIC/synthesis.cshrc
7
NTU GIEE EECS
What is Synthesis
 Synthesis = translation + optimization + mapping
8
NTU GIEE EECS
Logic Synthesis Overview

c=a+b
+ - x / cos sin
9
NTU GIEE EECS
HDL Compiler
 In schematic view, we can see the Verilog file is translated
into Design Compiler as Synopsys design block with a
GTECH library (the Synopsys default)
always @(reset or set) begin

HDL
if (reset) Comipler
y=1'b0;
else if (set)
y=1'b1;
end
always @(gate or reset)
begin
if (reset)
t=1'b0;
else if (gate)
t=d;
end
10
NTU GIEE EECS
Design Compiler
 Design Compiler maps Synopsys design block to gate level
design with a user specified library
Technolog
y
Library
11
NTU GIEE EECS
Design Compiler Interaction

 Three ways to interface
Design Vision
(GUI)
dc_shell
(Legacy Interface)
GUI
Design
Compiler
(DC)
dc_shell –t
(TCL Interface)
Command line
12
NTU GIEE EECS
RTL Coding Related to Synthesis

 Syntax
 Each-variable is assigned in the same always block
 Delay is for simulation, not for synthesis
 Memory case: #1 in nonblocking block v.s +notimingcheck
 Synopsys full_case / parallel_case
 Partition for synthesis
 Separate combinational and sequential part
 Separate control and VLSI-design strategy
 Register at input/output
 Special-case needs constraint setting
 Clock gating
 Multi-cycle
 False path
 Asynchronous logic
13
NTU GIEE EECS
STA (Static Timing Analysis)

 Sequential circuits are usually constrained by clock specify
 Clock cycle >= DFFclk-Qdelay + combinational delay + DFFsetup
 DFFclk-Qdelay + combinational delay >= DFFhold
1.CLK pin of Flop1 to D pin of Flop2

2.Input port to a D pin of Flop.
3.Q pin of flop to an output port
4.Input to output port through purely combinational logic
14
NTU GIEE EECS
Trade-off between Speed and Area

 Synthesis is Constraint Driven
 Technology Independent
15
NTU GIEE EECS
What .synopsys_dc.setup Defined

 search_path: the path to search for unsolved reference library or
design
 target_library: the ASIC technology that the design is mapped to
 link_library: the library used for interpreting input description
 Any cells instantiated in your HDL code
 Wire Load or Operating Condition models used during synthesis
 symbol_library: used during schematic generation
 synthetic_library: designware library to be used
 Other variables
16
NTU GIEE EECS
Synopsys Related Files

 Set your .synopsys_dc.setup
set company "EECS“
set designer "Student“
set search_path “ . $Your_path/CBDK_TSMC018/SynopsysDC/db/ \

./Memory/ $search_path“
set target_library “ slow.db fast.db tpz973gvwc.db tpz973gvbc.db \
SRAM2048x20_slow_syn.db SRAM2048x20_fast_syn.db “
set link_library “ * $target_library dw_foundation.sldb “
set symbol_library “ tsmc18.sdb generic.sdb “
set synthetic_library “ dw_foundation.sldb “
set verilogout_no_tri true

set hdlin_enable_presto_for_vhdl "TRUE“
set sh_enable_line_editing true
keep 100
alias h history
17
NTU GIEE EECS
Outline
 Introduction
 DC-TCL:Introduction
18
NTU GIEE EECS
Invoke Design Vision

 Linux%> dv &
19
NTU GIEE EECS
Optimization Using the Design Vision

 File/Read or File/Analyze & File/Elaborate
 Attributes – set up Design Environment & Goals
(record in script sdc files)
 Analysis/Report - check if set up is OK
 Analysis/Check Design
 Tools/Design Optimization
 Analysis/Report
 File/Save
20
NTU GIEE EECS
Read File
 Read netlists or other design
descriptions into Design Compiler
 File/Read
 Support many different formats:
 Verilog: .v
 VHDL: .vhd
 System Verilog: .sv
 EDIF
 PLA(Berkeley Espresso): .pla
 Synopsys internal formats
 DB(binary): .db
 equation: .eqn
 state table: .st
Equivalent dc_shell command :

dc_shell> read_file –format verilog lab1.v
21
NTU GIEE EECS
Analyze & Elaborate

 Use analyze and elaborate to bring Verilog or VHDL
files into design compiler memory
 Analyze does syntax checking and produces an
intermediate .syn .mr .pvl files to be stored in a
design library
 Elaborate looks in the design library for the
intermediate file and builds the design up into
design compiler memory (as design block)
22
NTU GIEE EECS
Analyze
File/Analyze
 Check VHDL & Verilog for syntax
and synthesizability
 Create intermediate .syn .mr .pvl
files and places them in library
specified – design library

dc_shell> analyze -format verilog –library WORK counter.v
23
NTU GIEE EECS
Elaborate
 Elaborate after analyze to File/Elaborate

bring design into Design
Compiler memory using
generic components
(GTECH)
 Look in the design library for
intermediate file for design
specified

dc_shell> elaborate counter -architecture verilog -library WORK
24
NTU GIEE EECS
Describe the Design Environment

 You can use Design Vision to constrain your design
25
NTU GIEE EECS
Link Design
 Analysis/Link Design
 Execute link -all before you optimize your design
 To ensure all sub-elements of your hierarchical
design are available
26
NTU GIEE EECS
Check Design
 Execute check_design before you optimize your design
 Two types of messages are issued
 Error
 Error: In design ‘bcd7segs’, cell ‘decoder’ has more
pins than it’s reference ‘d1’ has ports
 Warnings
 Warning: In design ‘converter’, port ‘A’ is not
connected to any nets
27
NTU GIEE EECS
Compile the Design

 The compile command optimizes and maps the current_design
28
NTU GIEE EECS
Report the Design

 From Design report and Timing analysis, you can find the set
attributes and the results after optimization
29
NTU GIEE EECS
Outline
 Introduction
30
NTU GIEE EECS
DC-TCL(Tool Command Language)

 TCL script = sequence of commands
 .synopsys_setup / my_script.tcl / DUT_syn.sdc
 Separate line ; Comments #
 GUI interface v.s. DC-TCL command

 dv –f script.tcl
 TCL Basics dc_shell>help get_*

 Function arguments
 Return string result

 Variable Substitution
 Syntax: $varName (set a b v.s set a $b)
 Nested Commands
 Syntax: [commands..] (set a “b-3 is [expr $b-3]”)
 get_, all_ command syntax
 Search the current design for names of the given object types
 Syntax: [get_type [-hierarchy] [name_list]] (set_dont_touch [get_cells * -hier])

 [all_inputs]…
31
NTU GIEE EECS
Design Objects
 Design: A circuit that performs one or more logical
functions
 Cell: An instance of a design or library primitive within
A design
 Reference: The name of the original design that a cell
instance “points to”
 Port: The input or output of a cell
 Pin: input or output of a design
 Net: The wire that connects ports to pins and/or pins
to each other
 Clock: Waveform applied to a port or pin identified as a clock
source
32
NTU GIEE EECS
Design Objects
Module TOP(A, B, C, D, CLK, OUT1);
input A, B,C, D, CLK; clock
output [1:0] OUT1; port
wire
wire INV0, INV1, BUS0, BUS1;
ENCODER U1 (.AIN(A), .BIN(B), .CIN(C), .DIN(D), .Q0(BUS0), .Q1(BUS1));
INV U2 (.A(BUS0, .Z(INV0))),
U3 (.A(BUS1, .Z(INV1))); pin
REGFILE U4(.D0(INV0), .D1(INV1), .CLK(CLK), .Q[0](OUT[0]), .Q[1](OUT[1]));
endmodule cell
reference and design
pin cannot
appear by itself,
must accompany
with cell
33
NTU GIEE EECS
Design Objects Exercise
pin cannot appear by

itself, must accompany
with cell
 Make a list of all the ports in the design?{ get_ports A,B,CLK,SUM }
 Make a list of all the cells that have the letter “U” in their name?
 { get_cells *U* ADDER/U1, DFF/U2 }
 Make a list of all the nets ending with “CLK”? { get_nets *CLK CLK }
 Make a list of all the “Q” pins in the design? { get_pins */Q U2/Q }
 Make a list of all the references? { ADDER,DFF }
34
NTU GIEE EECS
Outline
 Introduction
35
NTU GIEE EECS
Why Describes
the Real World Environment
 Beware that the defaults are not realistic conditions
 Input drive is not infinite
 Capacitive loading is usually not zero
 Consider process, temperature, and voltage (PVT) variation
 The operating environment affects the components
selected from target library and timing through your
design.
 The real world environment you define describes the
conditions that the circuit will operate within.
36
NTU GIEE EECS
Describing Design Environment (1/2)
1 set_operating_conditions
4 set_load
3 set_driving_cell
5 set_input_delay
set_wire_load_model 6 set_output_delay
create_clock
2
37
NTU GIEE EECS
Describing Design Environment (2/2)

For STA, every node should be known:
• RC value
• Inside DUT: Tech lib
1. standard cell/external-IP
2. wire load model
• Outside DUT:
• set_drive / set_driving_cell
• set_load
• I/O delay
• set_input_delay
• set_output_delay
38
NTU GIEE EECS
1. Setting Operating Condition

 Attributes/Operating Environment/Operating Condition
Step 1
Step 2
Name Process Temp Volt

Slow 1 125 1.62
Typical 1 25 1.8
Fast 1 -40
1.98
dc_shell> set_operating_conditions -max_library slow -max slow
-min_library fast -min fast
39
NTU GIEE EECS
2. Setting Wire Load Model

 Wire load model estimates wire capacitance based on chip
area & cell fanout
 Attributes/Operating Environment/Wire Load
Step 1
Step 2

dc_shell> set_wire_load_model –name tsmc18_w10 –library slow
40
NTU GIEE EECS
Drive Strength & Load for Pads

 Input Drive Strength for Pads  Output Load for Pads
41
NTU GIEE EECS
3. & 4. Input Drive Strength & Output Loading
TSMC18: PDIDGZ
 Consider for IO Pads (Synthesis w IO) R
 Setting Input Drive Strength c

pad
dc_shell command :
dc_shell> set_driving_cell –library tpz973gvwc –lib_cell PDIDGZ –pin {C} [all_inputs]
 Setting Output Loading
dc_shell command :
dc_shell> set_load [load_of “tpz973gvwc/PDT16DGZ/I” ] [all_outputs]
 Remember to add IO.db

into target_library in .synopsys_setup
42
NTU GIEE EECS
Port Report
 Design/Report ports Step 1 Step 2
dc_shell command :
dc_shell> report_port -verbose {port_list }
43
NTU GIEE EECS


44
NTU GIEE EECS
Input/Output Delay
 Clock cycle >= DFFclk-Qdelay + c + DFFsetup
 Clock cycle >= DFFclk-Qdelay + a + b + DFFsetup

 Input delay = DFFclk-Qdelay + a
 Clock cycle >= DFFclk-Qdelay + d + e + DFFsetup

 Output delay = e + DFFsetup
45
NTU GIEE EECS
Attention!
The step should execute
5. Setting Input Delay after clock specify
 Select input ports

 Attributes/Operating Environment/Input Delay
 Relative to clock trigger time
Step 3
Step 1 Step 2

dc_shell> set_input_delay –clock clk –max 6.4 [get_ports in1]
dc_shell> set_input_delay –clock clk –min 4.4 [get_ports in1]
46
NTU GIEE EECS
Attention!
The step should execute
6. Setting Output Delay after clock specify
 Select output ports

 Attributes/Operating Environment/Output Delay
 Relative to clock trigger time
Step 3
Step 2
Step 1

dc_shell> set_output_delay –clock clk –max 5.3 [get_ports out1]
dc_shell> set_output_delay –clock clk –min 4.4 [get_ports out1]
47
NTU GIEE EECS
SDC about
Setting Design Environment
set cycle 20
set t_in [expr $cycle/2]
set t_out 0.5
# Constraint setting
# Clock
constraints
set_fix_hold
create_clock -name [get_clocks clk]
set_dont_touch_network
clk -period $cycle [get_clocks
set_ideal_network
[get_ports clk] clk] [get_ports
set_clock_uncertainty clk]
set_clock_latency 0.1 [get_clocks clk]
0.5 [get_clocks clk]
# Other constraints
set_max_fanout 6 [all_inputs]
# Environment setting
1 set_operating_conditions -min_library fast -min fast -max_library slow -max slow
2 set_wire_load_model -name tsmc13_wl10 -library slow
3 set_drive 1 [all_inputs]
4 set_load 1 [all_outputs]
5 set_input_delay $t_in -clock clk [remove_from_collection [all_inputs] [get_ports clk]]
6 set_output_delay $t_out -clock clk [all_outputs]
48
NTU GIEE EECS
Outline
 Introduction
 Optimization Constraints
 Basic clock constraints concept
 Constraints & STA for Special Circuits
 Constraint for Power & Area
 Design Rule Constraint
49
NTU GIEE EECS
Basic Clock Constraints

 Clock 七大法則 :
 Period & Waveform
 Fix timing issue:
 Fix hold
 Issue handled in P&R CTS Stage
 Don’t touch
 Set ideal network ( 告知 DC 無 skew 問題 , 之後利用 uncertainty 悲觀模擬解決 )
 Uncertainty
 Skew
 Latency
 Source latency (option)
 Network latency
 Transition
 Input transition
 測試機台環境→適用 whole system 情況 DUT is submodule: set driving
strength
 Clock transition
 In P&R, 限制其後接的 FF 數
50
NTU GIEE EECS
Specify Clock Constrains

 Select clock port  create_clock : define clock’s waveform
 Attributes/Specify Clock dc_shell> create_clock -name clk
-period 10 -waveform {0 5} { clk }
//2nd clk: ports name
 set_fix_hold : respect the hold time
Step 1 requirement of all clocked flip-flops
dc_shell> set_fix_hold [ get_clocks clk]
 set_dont_touch_network : do
Step 2 not re-buffer the clock network
dc_shell> set_dont_touch_network [ get_clocks clk ]
 set_ideal_network
dc_shell> set_ideal_network [ get_ports clk ]
51
NTU GIEE EECS


52
NTU GIEE EECS
Clock Skew Issue
Arrival(FF1) = 0.5ns
53
NTU GIEE EECS
Setting Clock Uncertainty

 Different clock arrival time
 Models clock skew effects on the clock
 After CTS in P&R
real propagated skew is considered!
 Experie
 Small circuits: 0.1ns
 Large circuits: 0.3ns

dc_shell> set_clock_uncertainty 0.1 [get_clocks clk]
Timing report
54
NTU GIEE EECS
Setting Clock Latency
 Source latency
 Network latency

dc_shell> set_clock_latency –source 3 [get_clocks clk]
dc_shell> set_clock_latency 1 [get_clocks clk]
55
Combinational Circuit – NTU GIEE EECS
Max Delay Constraints
 For combinational circuits only
 Select the start & end points of the timing path
 Attributes/Optimization Constraints/Timing Constraints
dc_shell> set_max_delay 1 from
[all_inputs] –to [all_outputs]
56
NTU GIEE EECS
Setting Area & Power Constraint

 Attributes/Optimization Constraints/Design Constraints
Area unit(follow unit defined in

library):
1. Equivalent gate counts
 Gate counts
= Chip Report Area / NAND2 Area
2. um x um
3. Transistors
dc_shell> set_max_area 0
57
NTU GIEE EECS
Design Rule Constraints

 Design rules constraints can’t be violated at any cost, even if it
will violate the timing and area goal
 Design rules constraints restrict how many cells are connected
to one another based on capacitance, transition and fanout
 You may apply more conservative design rules to:
 Anticipate the interface environment your block will see
 Prevent the design from operating cell close to their limits, where
performance degrades rapidly
 Three kinds of design rule constraint are set:
 set_max_transition
 set_max_fanout
 set_max_capacitance
set_max_transition 0.2 [get_ports IN1]

set_max_fanout 6 [get_ports IN1]
set_max_capacitance 2 [get_ports IN1]
58
NTU GIEE EECS
Constraints Priority
 During the optimization, there exists a constraint priority
relationship.
 Design Rule Constraint
(max_transition, max_fanout, max_capacitance)
 Timing constraint (max_delay, min_delay)
 Power constraint
 Area constraint
 Use set_cost_priority command to modify the order

dc_shell> set_cost_priority [ -default] [-delay] [cost_list]
EX : set_cost_priority {max_fanout max_capacitance max_delay}
59
NTU GIEE EECS
SDC about Setting Design Constraint

set cycle 20
set t_in [expr $cycle/2]
set t_out 0.5
# Constraint setting
# Clock
constraints
set_fix_hold
create_clock -name [get_clocks clk]
set_dont_touch_network
clk -period $cycle [get_clocks
set_ideal_network
[get_ports clk] clk] [get_ports
set_clock_uncertainty clk]
set_clock_latency 0.1 [get_clocks clk]
0.5 [get_clocks clk]
# Other constraints
set_max_fanout 6 [all_inputs]
# Environment setting
set_operating_conditions -min_library fast -min fast -max_library slow -max slow
set_wire_load_model -name tsmc13_wl10 -library slow
set_drive 1 [all_inputs]
set_load 1 [all_outputs]
set_input_delay $t_in -clock clk [remove_from_collection [all_inputs] [get_ports clk]]
set_output_delay $t_out -clock clk [all_outputs] 60
NTU GIEE EECS
Check Design
 After you set up the deign attributes & design
constraints, we recommend the next step is to
check design
 Example: multiple instance
 How to handle ?
 uniquify
61
NTU GIEE EECS
Uniquify
 Create a unique design file for each instance
 May select one cell or entire design hierarchy to be uniquify
 Allow design to be customized to its interface
Step 2
 Select the most top design of

the hierarchy Step 1
 Hierarchy/Uniquify/Hierarchy

dc_shell> uniquify
62
NTU GIEE EECS
Check Constraints & Attributes

 Use the following reports to check constraints & attributes
before compiling
 Deign/Report Constrants
Step 2
Step 1
63
NTU GIEE EECS
Save Constraints & Attributes

 Save attributes & constraints setting as the design setup
file in TCL command format
 File/Save Info/Design Setup
64
NTU GIEE EECS
Execute Script File

 Execute TCL command script file, use
 File/Execute Script
Step 2
Step 1
Another method
65
NTU GIEE EECS
Compile
Step 2
Step 1

dc_shell> compile –exact_map –map_effort high –bounaray_optimization
66
NTU GIEE EECS
Assign Problem
 The syntax of “assign” may cause problems in the LVS

dc_shell> set_fix_multiple_port_nets -all -buffer_constants
67
NTU GIEE EECS
Floating Port Removing

 Due to some ports in the standard cells are
not used in your design
dc_shell> remove_unconnected_ports -blast_buses [get_cells -hierarchical *]
68
NTU GIEE EECS
Change Naming Rule

 Purpose: Let the naming-rule definitions in the gate-level
netlist are the same as in the timing file (e.g. *.sdf file)
 Also, the wrong naming rules may cause problems in the LVS
Bus[5] → Bus_5_
69
NTU GIEE EECS
Problem: High Fan-out Net

 Report Timing Path
 clock or reset has big delay
1. set hign_fanout_net_threshold 0
2. Find high fanout net

 report_net_fanout –high_fanout
 set_dont_touch_network
set_ideal_network
 report_net_fanout –high_fanout
 compile –inc –map_effort high
P 70
NTU GIEE EECS
Outline
 Introduction
71
NTU GIEE EECS
Timing Report
 Timing/Report Timing Path Step 2
Step 1
72
NTU GIEE EECS
Timing Report (from STA)
Start
End
73
NTU GIEE EECS
Area Report
External IP
Don’t care net area!
74
NTU GIEE EECS
Outline
 Introduction
75
NTU GIEE EECS
Gate-Level Simulation (Verilog)

 Write out gate-level netlist
1. File/Save As  Verilog
2. > write -format verilog -hierarchy -output chip_syn.v
 Get SDF(Standard Delay Format)

> write_sdf –version 2.1 chip_syn.sdf
 Modify your testbench file to include timing delay(Back annotate)

$sdf_annotate (“the_SDF_FILE_NAME”, top_module_instance_name);
 Gate level simulation with timing information:

>> ncverilog testbench.v chip_syn.v –v tsmc18.v +access+r
76
NTU GIEE EECS
Thanks for Listening

VLSI Crash Course Synthesis - 2019

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

VLSI Crash Course Synthesis - 2019

Uploaded by

Copyright:

Available Formats

NTU GIEE EECS

VLSI Crash Course

Cell-Based Design Flow

DRC Transistor-level Simulation

Synthesis Design Flow

Logic Synthesis Overview

always @(reset or set) begin

Design Compiler Interaction

RTL Coding Related to Synthesis

STA (Static Timing Analysis)

1.CLK pin of Flop1 to D pin of Flop2

Trade-off between Speed and Area

What .synopsys_dc.setup Defined

Synopsys Related Files

set search_path “ . $Your_path/CBDK_TSMC018/SynopsysDC/db/ \

set verilogout_no_tri true

Invoke Design Vision

Optimization Using the Design Vision

Equivalent dc_shell command :

Analyze & Elaborate

Equivalent dc_shell command :

 Elaborate after analyze to File/Elaborate

Equivalent dc_shell command :

Describe the Design Environment

Compile the Design

Report the Design

DC-TCL(Tool Command Language)

 Separate line ; Comments #

 GUI interface v.s. DC-TCL command

 TCL Basics dc_shell>help get_*

 Return string result

 Syntax: [get_type [-hierarchy] [name_list]] (set_dont_touch [get_cells * -hier])

Design Objects Exercise

pin cannot appear by

Describing Design Environment (1/2)

Describing Design Environment (2/2)

1. Setting Operating Condition

Name Process Temp Volt

2. Setting Wire Load Model

Equivalent dc_shell command :

Drive Strength & Load for Pads

3. & 4. Input Drive Strength & Output Loading

 Setting Input Drive Strength c

 Setting Output Loading

 Remember to add IO.db

STA (Static Timing Analysis)

1.CLK pin of Flop1 to D pin of Flop2

 Clock cycle >= DFFclk-Qdelay + a + b + DFFsetup

 Clock cycle >= DFFclk-Qdelay + d + e + DFFsetup

 Select input ports

Equivalent dc_shell command :

 Select output ports

Equivalent dc_shell command :

Basic Clock Constraints

Specify Clock Constrains

STA (Static Timing Analysis)

1.CLK pin of Flop1 to D pin of Flop2

Clock Skew Issue

Setting Clock Uncertainty

Equivalent dc_shell command :

Setting Clock Latency

Equivalent dc_shell command :

Setting Area & Power Constraint