The SoC Design Process

ECE 2140
Alex K. Jones
Spring 2011

SoC Design Overview

!  Overview and definitions
!  Design process
!  System domain
!  Structural domain
!  Physical domain
!  SoC specifics
!  Reuse, IP’s (macros), integration

1
 SoC Features
!  Canonical definition
!  100,000+ gates?
!  Programmable core?
!  Memory?
!  Plenty of virtual components?
!  Moderate volume product?
!  Short time-to-market?
!  Consumer electronics product?

SoC Features (cont’d)

!  Different design process?
!  Different CAD tools?
!  Different use?
!  Different design culture?
!  Etc.

2
 Canonical SoC

Peripherals Software

Memory
Processor Memory
Controller

I/O Data I/O

Interface Transformation Interface

Virtual Components (VC)

!  Reuse of intellectual property (IP)
!  In-house or externally acquired

!  Examples
!  Microprocessor core
!  A/D converter
!  Digital filter
!  Audio compression algorithm

3
 “Obtain” vs. “Create”
!  The SoC paradigm

!  Quickly assemble complex systems from

simpler, pre-characterized blocks

(some glue logic is inevitable)

4
 Building Block Components
(roughly equivalent terms)
!  Macros

!  Cores

!  IP (Intellectual Property)

!  Virtual Components (VC’s)

Intellectual Property (IP)

!  Three types of IP blocks

!  Hard (least flexible)

!  Firm

!  Soft (most flexible)

5
 Hard IP
!  Delivered in physical form
(e.g., GDSII file)

!  Fully
!  Designed
!  Placed and routed
!  Characterized for timing, power, etc.

Hard IP
!  Tied to a manufacturing process
!  Actual physical layout
!  Fixed Shape

!  Complete characterization
!  Guaranteed performance
!  Known area, power, speed, etc.

!  No flexibility

6
 Power
Hard
Macro
A-Input
Data Out
B-Input

Ground

Fixed Schematics and Layout

7
 Examples of Hard IP Blocks
!  A microprocessor core

!  A phase-locked loop (PLL)

!  Deeply process dependent

!  Stricter performance requirements

Soft IP
!  Delivered as synthesizable RTL
HDL code (e.g., VHDL or
Verilog)

!  Performance is synthesis and

process dependent

8
 Soft IP Blocks
!  Synthesizable Verilog/VHDL

!  Synthesis scripts, timing constraints

!  Scripts for testing issues

!  Scan insertion, ATPG, etc.

ENTITY example IS
PORT(clock, a, b, sel:IN BIT; d:OUT BIT);
END example;

ARCHITECTURE behavior OF example IS

BEGIN
PROCESS (clock)
IF (clock’EVENT AND clock=‘1’) THEN
IF (sel=‘1’) THEN d<=a OR b;
ELSE d<=a AND b;
END IF;
END IF;
END PROCESS;
END behavior;

9
 Examples of Soft IP
!  Counter, Comparator, Arithmetic/Logic Unit
!  Register File (Memory)
!  PCI bridge
!  Microprocessor core possible (not typical)
!  Representation form less process dependent
!  Final performance is still process and
synthesis dependent

Firm IP Blocks
!  Intermediate form between hard and soft IP

!  Some physical design info to supplement RTL

!  RTL or netlist or mixture of both

!  More (or less) detailed placement

!  Limited use beyond specified foundry

10
 Design Domains and Levels of
Abstraction

Design Domains
!  Represent different aspects
of a system
System
!  System or behavioral domain Behavior
Data Flow
!  Structural or RTL domain RTL
Physical Design

!  Physical domain

11
 Levels of Abstraction
!  Architectural
!  Algorithmic
!  Module (functional block)
!  Logical
!  Switch
!  Circuit (transistor)
!  Materials (device)

Behavioral (System) Structural (RTL)

Domain Domain
Operating Systems Computer
Applications
Microprocessor
User Programs
Adders, gates, flip-flops
Subroutines

Instructions Transistors

Circuit Abstraction Level

Transistors

Logic Abstraction Level

The Y
Cells

Architectural Abstraction Level

Chart Modules

Chips, Boards, Boxes

Physical Domain

12
 System Domain

• What a particular system does

" Functionality
" User interface
" Applications
" Operating system
" Subroutines, etc…

Structural Domain

• How entities are interconnected to

implement prescribed behavior
" Logic gates
" Registers
" RISC processor, etc…

13
 Physical Domain

• Physical structures to implement behavior

" Devices (transistors)
" Interconnections (wires)
" Physical qualities: conductivity,
capacitance, etc.

Physical Domain
!  Build the physical structures
to implement behavior

!  Devices (transistors)
!  Interconnections (wires)
!  Physical qualities: dielectrics,
conductors, etc.

14
 Example
!  An n-bit adder

!  Adds two n-bit numbers A and B to produce

a result C

Behavioral Representation
!  How a design responds to a set
of inputs?

!  Specification of behavior
!  Boolean equations
!  HDL, e.g., Verilog or VHDL

15
 Example Adder
!  Boolean equations

Sum = A.B’.C’ + A’.B’.C + A’.B.C’ + A.B.C

Carry = A.B + A.C + B.C

!  Verilog HDL
module carry (co, a, b, c);
output co;
input a, b, c;
assign
co = (a&b) | (b&c) | (a&c);
endmodule

Structural Representation
!  How components are
interconnected to perform the
required function

!  Specification
!  Typically a list of modules and
their interconnections

16
 Example Adder
!  Verilog HDL 1-bit component

module add (co, s, a, b, c);

input a, b, c;
output s, co;
// describe 1-bit adder
enddmodule

17
module Add4 (S, c4, ci, a, b);
input [3:0] a, b;
input ci;
output [3:0] s;
output c4;
wire [2:0] co;
add a0(co[0],s[0],a[0],b[0],ci );
add a1(co[1],s[1],a[1],b[1],co[0]);
add a2(co[2],s[2],a[2],b[2],co[1]);
add a3(c4, s[3],a[3],b[3],co[2]);
endmodule

modules interconnections

Physical Representation
!  How to build a part to guarantee
specific structure/behavior

!  Physical specifications
!  Materials qualities
!  Resistance, capacitance, etc.
!  Photo-masks required by various
fabrication steps

18
 Design Methodology
!  Also called Design Flow

!  The progressive transition from

design idea to real product

19
 Top-Down Design
!  Progressively descend into
lower abstraction levels

(recall adder example)

Top-Down Design

!  System specification
!  Refine architecture,algorithms
!  Decompose into blocks
!  Design or select macros
!  Integrate macros
!  Deliver to next level integration
!  Verify

20
 System Design Flow
!  SoC challenges force chip
designers to alter design flow

!  Waterfall model to spiral model

!  Top-down methodology to
Top-down/Bottom-up combination

Waterfall Model
!  Step-to-step handoff

!  Fewer feedback paths in the flow

!  Possibilities for re-iteration exist

21
 Waterfall Methodology
Specification RTL Code Functional
Development Development Verification

Timing Place and

Synthesis
Verification Route

Prototype Deliver to System

Build and Test Integration and SW Test

ASIC Specification
!  Typical design style for ASIC’s
(Application-Specific IC)

!  ASIC’s with high algorithmic

content developed by an expert

!  Algorithm handed to a design team to

develop RTL model for the ASIC

22
 Waterfall Flow Limitations
!  Handoff between teams rarely clean
!  May have to tell the system designers
algorithm will not work

!  Doesn’t work for large, deep

submicrometer designs
!  Software and hardware must be developed
concurrently
!  Physical design issues must be considered early to
meet performance goals

Spiral Development Model

!  Response to increased complexity and
shorter time-to-market pressure

!  Multiple aspects of design are worked

on simultaneously

!  Each area is incrementally improved

together as the entire project is
completed

23
 Spiral Methodology
System Design and Verification
PHYSICAL TIMING HW SW

Physical Timing HW Specs SW Specs

Specs Specs

Preliminary Block Timing Block Test App.

T
Floorplan Specs Selection/Design prototype
I
Updated Block Block Application
M
Floorplan Synthesis Verification development
E
Updated Top-level Application
Floorplan HDL testing

Trial Top-level Top-level Application

Placement Synthesis Verification testing

Final Place and Route/ Tapeout

Software:
Hardware:
• Platform
• Architecture
• Language
• Sub-system
• Application
• RTL
Others…
• Testing
• Verification
• Etc.
Physical:
• Technology Timing:
• Floorplan • System I/O
• Placement • Sub-system
• Clocking

24
 Spiral Design Characteristics
!  Concurrent HW & SW development
!  Parallel verification and synthesis
!  Floorplanning and place-and-route included in the
synthesis process
!  Modules developed only if a predesigned hard or
soft macro is not available
!  Planned iteration throughout

Simultaneous Development
!  For aggressive projects,
simultaneous development of
!  Top-level system specifications
!  Algorithms for critical sub-blocks
!  System-level verification suites
!  Timing budget for final chip
integrations
!  All aspects of hardware and
software designed concurrently

25
 System Level Design
!  What a particular system does?

!  Functionality
!  User interface
!  Applications
!  Operating system
!  Subroutines

System Level Overview

!  Requirements and specifications
!  Algorithmic modeling
!  IP (macro) acquisition
!  Embedded software codesign
!  Hardware co-design/co-verification
!  Testing issues

26
 The Design Process

WRITE DEVELOP
IDENTIFY
preliminary REFINE
requirements
specs Algorithms

WRITE and DETERMINE

DEVELOP
DEVELOP HW/SW
software
SW prototype partition

CO- VERIFY/TEST Library

SIMULATION HW models

The Design Process

WRITE DEVELOP
IDENTIFY
preliminary REFINE
requirements
specs Algorithms

WRITE and DETERMINE

DEVELOP
DEVELOP HW/SW
software
SW prototype partition

CO- VERIFY/TEST Library

SIMULATION HW models

27
 IDENTIFY
Requirements requirements

!  System requirements identified

!  Required functionality
!  Required performance
!  Cost & development time

!  Preliminary specifications
!  Joint venture: engineering
and marketing
!  Based on systems
requirements

IDENTIFY
Top-Down Perspective requirements

Product
Product Product requirements
Description Requirements from marketing

System
System Block Block specification to
Specification Requirements Specification meet product
requirements

28
 IDENTIFY
Components of a Price requirements

List price
Average
Discount

Average selling price

Gross Gross
Margin Margin

Direct costs Direct costs Direct costs

Component Component Component Component

Costs Costs Costs Costs

33% for direct costs 33% for gross margin 50% for average discount

The Design Process

WRITE DEVELOP
IDENTIFY
preliminary REFINE
requirements
specs Algorithms

WRITE and DETERMINE

DEVELOP
DEVELOP HW/SW
software
SW prototype partition

CO- VERIFY/TEST Library

SIMULATION HW models

29
 WRITE
IDENTIFY
Specifications preliminary
requirements
specs

!  Recursively develops, verify and

refine specifications to enable
modeling

!  Completeness and consistency

!  Know exactly what is to be built

and identify errors early

WRITE
IDENTIFY
Formal Specification preliminary
requirements
specs

!  Required features of design are

implementation-independent

!  Promising in the long term

!  Permit using formal methods for

verification
e.g., property checking

30
 WRITE
Executable Specs preliminary
specs

!  More useful than for functional

behavior

!  Abstract model of hardware and

software specified

!  Describes critical physical

specifications

WRITE
preliminary
Executable Specs specs

!  High level specifications

!  C, C++, SystemC, UML

!  Lower level specifications

!  Verilog, VHDL

!  Permit functionality
verification before
start of design

31
Specification WRITE
preliminary
Requirements specs
!  HW & SW equally
important

!  Must be
specified

!  Describe behavior
and interface
to world

Software Specification WRITE

preliminary
Requirements specs

!  Functionality
!  Timing
!  Performance
!  Interface to HW
!  SW structure,
kernel

32
Hardware Specification WRITE
preliminary
Requirements specs

!  Functionality
!  Timing
!  Performance
!  External interfaces
to other hardware
!  Interface to SW
!  Area, power

The Design Process

WRITE DEVELOP
IDENTIFY
preliminary REFINE
requirements
specs Algorithms

WRITE and DETERMINE

DEVELOP
DEVELOP HW/SW
software
SW prototype partition

CO- VERIFY/TEST Library

SIMULATION HW models

33
 DEVELOP
High-level Model REFINE
Algorithms

High-level algorithmic model !  Use for future

developed for overall system designs

!  C and C++
behavioral model

!  Check RTL with

software model

Model Refinement DEVELOP

REFINE
and Test Algorithms

!  High-level model
!  Refine and test high-level model
!  Verify performance of algorithm
!  Used later to verify models for
hardware/software

!  Systems with high algorithmic

content need considerable
testing

34
 DEVELOP
Performance Analysis REFINE
Algorithms

!  Throughput: total amount of

work done in a given amount
of time

!  Latency: total amount of time to

complete a task

DEVELOP
Throughput REFINE
Algorithms

92.2 Kbps 128 Kbps 112 Kbps

End-to-end throughput: 92.2 Kbps or 72% of fastest transformation

!  Bottleneck limits end-to-end

throughput
(slowest transformation)

35
 DEVELOP
Latency REFINE
Algorithms
!  Latency: Same as response time
!  How long it takes a transformation (or system) to
produce an answer
!  Users care about response time!

10 ns 8 ns 12 ns
From time request received to time an answer is produced is sum of
the latency of the blocks (10 ns + 8 ns + 12 ns = 30 ns)

DEVELOP
Software vs. Hardware REFINE
Algorithms

!  Software
!  Flexible – field changes!
!  Increased performance needed
SW is abstraction (adds overhead)
!  Efficient use of HW (processor)
!  Hardware
!  Less flexible
!  Achieve best power/performance
tradeoff

36
 The Design Process

WRITE DEVELOP
IDENTIFY
preliminary REFINE
requirements
specs Algorithms

WRITE and DETERMINE

DEVELOP
DEVELOP HW/SW
software
SW prototype partition

CO- VERIFY/TEST Library

SIMULATION HW models

DETERMINE
HW/SW Partitioning HW/SW
partition

!  Divide system functionality

between hardware and
software

!  Largely manual process requiring

extensive human experience

37
 DETERMINE
HW/SW
Define Interface partition

!  Final step in hardware/software

partitioning

!  Define interfaces between

hardware and software

!  Specify communication protocols

(hw to hw, hw to sw, sw to sw)

DETERMINE
HW/SW
Block Specification partition

!  Software specification

!  Hardware specification
!  Functions
!  Timing
!  Area
!  Power requirements
!  Physical interfaces

38
 DETERMINE
IP Selection HW/SW
partition

!  Select IP’s for transformations

from initial architecture

(1)  For a given block, what IP is

available
(2) Evaluate available IP
(3) Select IP that best matches
design
(4) Design refinement required?

DETERMINE
IP Sources HW/SW
partition

Internal External
IP IP

Software Developed
Libraries IP

39
 DETERMINE
Selecting IP HW/SW
partition
!  Identify potential IP’s in design,
type, and where to get it
!  Evaluate potential macros
!  Documentation, cost, licensing, etc.
!  Functionality (meet specs?)
!  Effort to integrate?
TSMC Free Library Products
Process CL025 CL018 CL015 CL013
(Click on product below to view datasheet ) G E G LV LP G LV G LV LV-LK LV-LK-OD
SAGE Standard Cell Library X X X
SAGE-X Standard Cell Library X X X X X X X X
SAGE-HS Standard Cell Library Eval
Kit
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High-Speed/Density Single-Port Register File Generator X X X X
High-Speed/Density Two-Port Register File Generator X X X X X X X
High-Density Single Port Memory Generator X
High Density Dual Port Memory Generator X
I/O Cell Library X X X X X

DETERMINE
IP Selection Check List HW/SW
partition

Functionality A useful check list may

Type (1) Rate blocks in each
category
Cost (2) Given written advantage
and disadvantages of the
Performance block
Documentation (3) Document vendor
willingness to help and
Design flow provide information (as a
Licensing sign of things to come)

Vendor support

40
 DETERMINE
Verification of IP’s HW/SW
partition

!  Is block fully verified?

!  Desirable to have process
documented: including testbench
and test vectors

!  Good verification documentation

includes
!  Environment used to verify blocks
!  Actual test vectors and test bench

DETERMINE
IP Licensing Model HW/SW
partition

!  Pay once: one time payment, use

block as much as needed
!  Pay per use: fixed payment, use
block in each design
!  Pay per unit: payments tied to
volume of product sold

!  Reality: A combination of above!

41
 DETERMINE
Sources of Internal IP HW/SW
partition

Organizational IP

Department IP

Group
IP

Ease of Amount of
getting it IP

DETERMINE
External IP’s HW/SW
partition

!  Major problem: Identify IP

vendors which offer desired
macro(s)

!  Solutions:
!  Web searches (www.google.com)
!  IP repositories, such as Design and
Reuse B2B web-site
http://www.us.design-reuse.com

42
 DETERMINE
Integrating Blocks HW/SW
partition

Preparation Placement Loop

Design Planning, Iterate placement,
Block Synthesis, Analyze timing results,
Detailed Floorplanning, Refine placement until
Initial Placement timing constraints met

Physical Verification
Timing Closure
Final checks before layout
Adding clocks and detailed
Check power distribution,
routing, fix remaining
Design rule checking,
timing problems
Layout vs. scheme

The Design Process

WRITE DEVELOP
IDENTIFY
preliminary REFINE
requirements
specs Algorithms

WRITE and DETERMINE

DEVELOP
DEVELOP HW/SW
software
SW prototype partition

CO- VERIFY/TEST Library

SIMULATION HW models

43
 DEVELOP
Software IP for SoC’s software

!  Similar problems with HW IP

!  Product complexity
!  Sophisticated applications
!  Multi-domain applications
!  Time-to-market issues

!  Most software IP, like hardware

IP is developed internally

DEVELOP
Unique Challenges software

!  Proliferation of processor cores

!  Few players dominate market

44
 DEVELOP
Writing SoC Software software

!  Traditionally done in assembly

!  Modern approach: move to high

level languages (HLL)

!  Advantages: time-to-market, reuse,

readable, maintainable
!  Disadvantages: performance
penalty (memory and cycles)

DEVELOP
Structuring SoC Software software

!  Create software architectures

similar to hardware
architectures
!  Layer software for increasing
abstraction and portability
!  Less efficient than “custom design”
but quicker time-to-market and
more reliable

45
 DEVELOP
Software Development software

!  Phases similar to hardware

Instruction-level Development (Timing estimates)

Software Functionality Development

Architecture Faithful Development

Complete Design Integration with other actual IP

DEVELOP
Phase 1 software

!  Develop software on host

workstation
!  Start before target processor selected
!  Implement modules with desired
functionality interfaces
!  Test software design
!  Very fast testing (at host processor
speed)
!  Tools: compiler, debugger, OS, are
available (experience exists)

46
 DEVELOP
Phase 2 software

!  Move software to target processor

family ISA simulator
!  Get early estimate of instruction
count
!  Measure of performance:
!  Time = IC * Cycle rate
!  Assembly code for performance
critical code

DEVELOP
Phase 3 software

!  Timing accurate simulation of

selected processor (specific
architecture)
!  Only after processor selection
!  Improves timing estimates
!  Generally faithful model of processor hardware
!  Simulation times grow by 100-1000X

47
 DEVELOP
Phase 4 software

!  Integrate software into complete

design as other modules (incl.
IP’s) are identified

!  Begin with algorithmic model

!  Move to full codesign environment
!  Most accurate timing estimates
!  Interaction with hardware verified

DEVELOP
Getting SoC Software software

!  Processor vendor
!  A few selections:
!  Mentor: www.mentor.com
!  QNX: www.qnx.com
!  WindRiver: www.windriver.com
!  MontaVista: www.mvista.com
!  GNU and Redhat: www.redhat.com
!  Metrowerks: www.metrowerks.com

48
 DEVELOP
Software Architecture software

Error Memory
GUI Diagnostics,
Host Handler Allocation
Debug,
Applications State
Messaging Scheduler Test
Machine
Application Program Interface
Display Timer/Alarm Event
Services Services Manager
Protocol Kernel
File Library Data
Stack Manager Routines I/O Services

Device Drivers
Hardware

The Design Process

WRITE DEVELOP
IDENTIFY
preliminary REFINE
requirements
specs Algorithms

WRITE and DETERMINE

DEVELOP
DEVELOP HW/SW
software
SW prototype partition

CO- VERIFY/TEST Library

SIMULATION HW models

49
 VERIFY/TEST
Behavioral Model HW models

!  Behavioral model developed in

parallel with software

!  Consider behavioral models of

hardware in macro library

!  Continue throughout design

process

VERIFY/TEST
Codesign/Coverification HW models

!  Integrating all blocks into a

complete design
!  Software models substituted as
hardware blocks become
available
!  Objective: verify complete
system in hardware

50
 Structural Design Domain
!  Data handed off from System
domain

!  Executable specifications exist

!  Further refinement of architecture

!  Final choice of macros

Structural Milestones
!  Detailed top-level architecture

!  Final partitioning decomposition

!  Blocks and sub-blocks design

!  Testing/verification
!  Functionality
!  Performance

51
 Architecture Partitioning
!  Recall system level partitioning
!  More refined and detailed specs

!  Still mostly manual process

!  Engineering ingenuity, experience

!  More details (vs. system domain)

!  Power budget
!  Interface constraints
!  Performance goals

Unique Features for SoC

!  Virtual components

!  IP Creation: design for re-use

conventions, standards, safe
practices

52
 IP Design Methodology
!  Specification: Functional
Modeling and Partitioning
!  Sub-Component Specs and Design
!  Testbench Design
!  Speed, power, and area
considerations
!  Integration and productization:
documentation of functionality,
testing/synthesis environment

53
 Specifications for IP Design and
Reuse
!  Define IP specificationss
!  Process-Flow Graphs
!  Block Diagrams
!  Finite State Machine Descriptions
!  Choice of test methodology
!  Prepare software models
requirements for embedding
!  Set of deliverables
!  Verification Plan

Top Level Design

!  Implementation guidelines for portability and
extensibility
!  Design using standard libraries
!  Behavioral design and simulation
!  Move from executable specifications to
executable RTL
!  Testbench creation
Fault coverage models

54
 High Level Synthesis
!  Synthesis issues: coding for synthesis

!  Behavioral Synthesis Process

!  Scheduling operations
!  Resources allocation and binding

!  Supported Data-Types

!  Coding styles for FSM controllers, I/O,

timing, ports, clocks, resets

!  Scheduling control and pipelining

Partition & Decompose

!  Writing specifications for sub-blocks:
speed/power/area requirements
!  Representation, precision and accuracy issues
!  Generic datapath and controller model
!  Datapath design
!  Finite State Machine controllers:
!  Styles
!  Clocking
!  Reset

55
 Sub-Component Design
!  Write RTL vs. high level synthesis

!  RTL coding styles

!  Sub-Component Interfacing

!  Timing: Registers, Clocking, Resets, etc.

!  I/O ports: specifications, standards, busses,

handshaking, etc.

Integration and Test

!  Sub-block integration and testing:
Integrating the synthesized designs

!  Support portable testability:

!  Testbenches
!  Code coverage
!  Scripts
!  Timing specifications

!  Verification Issues:
Top-Level VHDL behavioral model vs.
Synthesized Design(s)

56
 Hardware Wrappers
!  Interfaces consistency to ensure
inter-block communication
!  Between interfaces (to a bus, block)
!  Between different protocols
!  Between different data rates
!  Between exception models

!  Mostly an issue for re-used IP

rather than newly developed IP

Wrappers
!  Need to judge likely wrapper complexity
when selecting a piece of IP
!  Don’t under-estimate importance, difficulty,
and time of developing a wrapper
!  Include development time estimate and
chip cost of wrappers
!  Wrappers must be tested and verified too!

57
58
Example Wrapper Between Blocks

Block with Block with

unidirectional bidirectional
data input and data input and
output output

Wrapper may map a block with a simple handshake

protocol, separate address and data, and unidirectional
data lines to another block that has a more complex
handshake with bidirectional data lines and address/data
multiplexing

Example Wrapper to a Bus

Block with
narrow data
interface

Wrapper maps a narrow 8-bit interface to an industry

standard bus (e.g., ARM’s AHB) with a 32-bit data width and
multiplexed address/data

59
 Physical Design Domain
!  Final chip integration

!  Various verifications
!  Example 1: Power and clock verification
delivered everywhere?
!  Example 2: Interconnections correspond
exactly to transistor-level schematic?

Physical Design Domain (cont’d)

!  Translate higher level description into
final physical layout

!  Finalize physical design of soft IP blocks

!  Constraints are met?

!  Verify timing and power constraints

60
 Example Verification: Chip
Power
!  Ensure good power distribution
!  Voltage (IR) drop
!  Ground bounce
!  Electro-Magnetic (EM) problems
!  Routing
!  Power pins

Example Integration Problem

!  Thermally hot IP blocks cause a power

supply drop (insufficient power)
!  Potential solutions:
! More bond wires?
! Sufficient number of power pins on
package?

61
 Key Points
!  Waterfall to spiral design methodology

!  System/structural/physical design domains

!  Hardware/Software interaction
!  Common architectural platform

!  Importance of correct
integration of IP blocks

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