Review of VLSI

Dr. SC Bose
scbose@iitj.ac.in

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Human Brain has 1011 neurons, each with ~103
synapses switching ~103 times per second.

Total operations: ~1017 operations/sec.

•Lap-Top has 108 transistors, each switching ~109

times per second.

•Total operations: ~1017 operations/sec.

Why can a human think while a lap-top cannot ?

New Architectures
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 Aspects of Hardware Description

Behavioural (Functionality and Speed)

Structural (Parts and their Interconnection, netlist)

Physical (Means to realise on semiconductor — Silicon

The information on each of these aspects is itself

represented at different levels of details—using different
abstraction levels. Each abstraction level is used to
represent information on an aspect of the design at a
certain convenient level of detail.— Gajski’s Y-Chart.

A complete system of maintaining , providing and exchanging

information on a VLSI design must address all the three domains
individually or in combination. 3
Structural Domain Y Chart Behavioural Domain
System System Synthesis System
Structure behaviour
Register Transfer Synthesis
Processors, Buses Flow Charts, Algo
Registers, ALUs Logic Synthesis Register Transfer

VHDL or Gates, FFs Circuit Synthesis Boolean Expression

Verilog or
SystemC Transistors Transistor Functions
Three levels of
abstraction/domain of Transistor layout
Chip/IC Design: (i)
Behavioural, (ii) Structural Cell layout
and (iii) Physical. Along GDSII or CIF
each axis there are different Block Layouts
levels of domain
Chips, Floor Plans
description.

Many feed backs involved, Boards, MCM, System Partitions

not shown. Physical Domain 4
 Desired Behaviour
Top Down Approach
Desired complex behaviour of a hardware
is achieved by partitioning it (recursively)
into interconnection of simpler (known)
behaviour.
Partitioned Sub-Behaviours
The designer controls the partitioning and
specifies the sub-behaviour of each Desired Behaviour
partition. There are no a priori given parts
or components. Design Hierarchy

Bottom-up Approach
Desired complex behaviour of a hardware
(of reasonable complexity) is achieved by Given Parts/components
suitable selection and interconnection of
parts/components with known behaviours
available in standard cell library of TTL
gates.

Mixed Top-Down and Bottom-up

Design 5
 Hierarchical decomposition,
Sum = a b c + a b c + a b c + a b c = a + b + c Divide and conquer

Carry = a b + b c + c a = b (c + a) + a b

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 VLSI design involves translating the
given specification into geometrical
patterns that are used for fabricating
chips.

It is accomplished through a
succession of translation steps of
manageable complexity.
One to many mapping.

Each translation step translates a

more abstract(less detailed) design
representation into less abstract (more
detailed) design representation.

Managing increasing complexity and making optimal

choice, under given constraints, as one goes through
successive translation steps is the central issue. 7
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 Mixed Mode
Structural Domain Behavioural Domain
System System
Structure behaviour
Processors, Buses Flow Charts, Algo
Registers, ALUs
Register Transfer
Gates, FFs Boolean Expression
Transistors Transistor Functions

Transistor layout

Cell layout

Block Layouts

Chips, Floor Plans

Boards, MCM, System Partitions

Physical Domain 9
 DE/DS Behavioural Level DV Simulation
DE—Design Entry
No DS—Design Synthesis
OK ?
Design output
DV—Design Verification
yes
DE/DS RT Level DV Simulation

OK ?
No
yes Design output
Synthesis is defined as
DE/DS Logic/Gate Level DV Simulation
translation from behavioural
description to structural
No
description. Also known as
OK ?
yes
Design output Design Refinement.
DE/DS Tran/Circuit Level DV Simulation

No Verification
OK ? Bugs or Mistakes are
Design output
yes preferred to be found at the
DE/DS Layout/Physical Level DV Simulation early stages, otherwise cost
No and time to market will
increase.
ok
yes Design output
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 The majority of design cycle time is devoted for achieving desired level
of performance (speed, power consumption, precision etc) at an
acceptable cost(economical cost, design time and verification time,
capturing the market window etc).

The choice of design style depends upon performance requirement,

technology being used, expected lifetime of the product and the cost of
the project/implementation.

Every two years, the technology node changes. The application(s) should
garner the maximum benefit (RoI—Return on Investment).

The design cycle time of next generation overlaps with the production time of
current technology.

Shorter Design Time—Demand/Evolution and extensive of EDA tools

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Regularity: The hierarchical decomposition of a large
system should result in not only simple but also similar
blocks as much as possible

It reduces the number of different modules that need

to be designed and verified at all levels of abstraction.

Modularity: Various functional blocks must have well

defined functions and interfaces. Independent design
of blocks. Enables parallelization of design effort.

Locality: Internal details remain local and is

unimportant to external module. Connections are
mostly between neighbouring modules avoiding long
distance connection

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 Boolean Algebra led to the concept of digital logic.
There are eight major families of logic :

Register-Transistor Logic (RTL), Diode-transistor logic (DTL), Transistor-

transistor logic (TTL), Complementary transistor logic (CTL), Emitter-coupled
logic (ECL), Metal Oxide Semiconductor (MOS) logic, Complementary Metal-
Oxide Semiconductor (CMOS) and Integrated Injection Logic (IIL)

MOS or planar technology became commercially viable and CMOS is most

popularly used from low power point of view.

Feature Size : 6 µm to 0.065 µm, 0.022µm

Wafer Size : 2 inch to 12 inch

Chip Size 2 by 2 mm to 2 by 2 cm
Few Hundred transistors to
Thousand million of transistors
per chip.

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How is VLSI ? Specification

The technology that enabled this exponential growth Block level

is a combination of advances in process technology,
Bheaviour
architecture and design and development tools.
Sub blocks
Better understanding of device structure, RTL

governing physics, their electrical behaviour Gates/FU

Synthesis
and of the interaction between the devices led
to a lot of research on software resulting in Gate Arrays / Standard Cell Transistors
many useful EDA tools. Uses of these tools FPGAs

reduced the design time and cost. Mask

Simulation tools are available for different levels

The lower the level of simulation,
of abstraction of the circuit like behavioural,
more accurate are the simulation
architectural, functional, gate, switch, circuit,
results, also more is the simulation
device, and silicon levels.
time, costlier is correction (if any).
Front-End & Back –End
Design Inter-disciplinary, Multi Disciplinary
Functional verification, detection of spikes (at transistor level) are the essential
part of simulation. 16
Packaging
Packaging issue should be considered right at the beginning.

Number of ground plane, power plane, bonding pads and the distance
between the pads affect the behaviour of the chip
The distance (wire length) between the pad and the package pin determines
the inductive voltage drop.

Thermal aspect

Hermetic seals to prevent moisture, Thermal conductivity, Thermal expansion

coefficient, Pin density, Parasitic inductance and capacitance and radiation
protection

PTH (Pin Through Holes), SMT (Surface Mounted Technology)

Plastic and Ceramic (Power dissipation, performance and environmental

requirement)
DIP, PGA, CCP, QFP, MCM
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Types of Packages

Dual In-Line Package (DIP): PTH type, Low cost,

Dimensions are large, High interconnect inductances,
Maximum pin count is 64

Pin Grid Array (PGA): PTH type, Higher pin count

(several Hundred), High thermal conductivity, requires
large PCB area, cost is higher.

Chip carrier Packages (CCP): SMT type, (leadless and leaded

chip carrier), very high pin count for leadless but thermal mismatch
between carrier and PCB leads to mechanical stress

Quad Flat Packs (QFP): SMT type, Pin count is very high (around
512)

Multi Chip Module (MCM) : Multiple chips within one package,

reduced lead counts, faster operation, reduced size. 19
System on Chip (SOC) designs involve the use of hardware-software co-design,
leveraging different programmable architectures including RISC, CISC, VLIW,
DSP, ASIP, re-configurable architectures, Mixed-signal design, RF design and
integration of Sensors( MEMS/NEMS ,MOEMS, Biological, Chemical)

This poses the highest degree of inter-disciplinary design challenge.

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• Increasingly, the most interesting work is being
done at the interfaces between chemistry,
biology, physics, engineering, geology, and other
disciplines. That has the effect of blurring the
boundaries between traditional disciplines.

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