Design Compiler Introduction: Yi Zhang Jan 30, 2015

Design Compiler Introduction
Yi Zhang
Jan 30th, 2015
© 2015 Synopsys, Inc. All rights reserved. 1

Contents:
• DC in ASIC Design Flow

• DC Family
• DC Synthesis Flow
• DC Optimization Fundamentals

Preface
• Synthesis: 综合
• Implementation: Implements target design specification using netlist with best QoR, through performing synthesis.
• HDL source code: Describe design using Hardware Description Language, Verilog HDL or VHDL.
• RTL: register transfer level description of a target design;
– Behavior Level
– Register Transfer Level
– Gate Level
– Transistor Level
• GTECH library (gtech.db): generic technology-independent library cells, no physical info.

• SEQGEN: generic technology-independent sequential logic cell (**SEQGEN**), no physical info.
• Design Ware: Components to implement various basic logic operation, for Ex., +,-,*,/,>,<,>=,<=,!=,<<,>>, …
• Synthetic Operator: Operators in arithmetic will firstly be mapped to synthetic operators.
• Synthetic Library: Design Ware module library
– DesignWare standard (standard.sldb): basic implementations, built-in DC, no need to specify.
– DesignWare foundation (dw_foundation.sldb): high performance implementations with advanced architecture.
Needs Design Ware foundation license.
– report_synlib will see the detailed component list.
• Symbol library (generic.sdb): For schematic generation. You’d see following info when “View Schematic”:
– Loading db file '/u/re/spf_j2014.09_sp/image_NIGHTLY/latest/libraries/syn/generic.sdb'

DC in ASIC Design Flow
FLOW TASK TOOL
Design Specification
Describe Design in Text Editor;

HDL Coding
Register Transition Level Using HDL Language.
Check for Functional

RTL Simulation VCS
Correctness
• Logic Optimization
• Netlist Generation
Analog Circuit Logic Synthesis DC, RC (Cadence)
• Netlist Optimization for
Area, Timing, and Power
• Insert Scan Logic to Netlist

Test Synthesis DFTC, DFT Adviser (Mentor)
• DFT DRC Check and Fix
• Floorplan;
• Power Planning;
Auto-Place&Route • Placement, CTS, Routing; ICC/ICC2, EDI (Cadence)
…… • DRC Fixing, Timing
closure, Area, and Power
Digital Circuit optimization.

Launching DC
Design Compiler Graphical
DC Ultra (TM)
DFTMAX (TM)
Power Compiler (TM)
DesignWare (R)
DC Expert (TM)
Design Vision (TM)
HDL Compiler (TM)
VHDL Compiler (TM)
DFT Compiler
Library Compiler (TM)
Design Compiler(R)
Version J-2014.09-SP2 for RHEL64 -- Nov 25, 2014

Copyright (c) 1988-2014 Synopsys, Inc.
This software and the associated documentation are confidential and

proprietary to Synopsys, Inc. Your use or disclosure of this software
is subject to the terms and conditions of a written license agreement
between you, or your company, and Synopsys, Inc.
Initializing...
dc_shell>

DC Family
Design Compiler Graphical Role of Members
DC Ultra (TM)
DFTMAX (TM) Design Compiler for Logic Synthesis
Power Compiler (TM)
Scan Logic insertion and scan compression
DesignWare (R)
DC Expert (TM)
Power Analysis and Low Power Implementation
Design Vision (TM)
HDL Compiler (TM)
Read in HDL Source Code
VHDL Compiler (TM)
DFT Compiler
GUI for Schematic and Design Implementation
Design Compiler(R)
Library Conversion from .lib to .db

Library for Frequently Used Operators

Initializing...
dc_shell>

DC Family
DC Ultra (TM)
Power Compiler (TM)
DesignWare (R)
DC Expert (TM)
Design Vision (TM)
HDL Compiler (TM)
VHDL Compiler (TM)
DFT Compiler
Design Compiler(R)


Initializing...
dc_shell>

DC Family
DC Ultra (TM)
Power Compiler (TM)
DesignWare (R)
DC Expert (TM)
Design Vision (TM)
HDL Compiler (TM)
VHDL Compiler (TM)
DFT Compiler
Design Compiler(R)


Initializing...
dc_shell>

DC Family
DC Ultra (TM)
Power Compiler (TM)
DesignWare (R)
DC Expert (TM)
Design Vision (TM)
HDL Compiler (TM)
VHDL Compiler (TM)
DFT Compiler
Design Compiler(R)


Initializing...
dc_shell>

DC Family
DC Ultra (TM)
Power Compiler (TM)
DesignWare (R)
DC Expert (TM)
Design Vision (TM)
HDL Compiler (TM)
Read and Translate HDL Source Code
VHDL Compiler (TM)
DFT Compiler
Design Compiler(R)


Initializing...
dc_shell>

DC Family
DC Ultra (TM)
Power Compiler (TM)
DesignWare (R)
DC Expert (TM)
Design Vision (TM)
HDL Compiler (TM)
VHDL Compiler (TM)
DFT Compiler
Design Compiler(R)


Initializing...
dc_shell>

DC Family
DC Ultra (TM)
Power Compiler (TM)
DesignWare (R)
DC Expert (TM)
Design Vision (TM)
HDL Compiler (TM)
VHDL Compiler (TM)
DFT Compiler
Design Compiler(R)


Initializing...
dc_shell>

DC Family
DC Ultra (TM)
Power Compiler (TM)
DesignWare (R)
DC Expert (TM)
Design Vision (TM)
HDL Compiler (TM)
VHDL Compiler (TM)
DFT Compiler
Design Compiler(R)


Initializing...
dc_shell>

DC Family
DC Ultra (TM)
Power Compiler (TM)
DesignWare (R)
DC Expert (TM)
Design Vision (TM)
HDL Compiler (TM)
VHDL Compiler (TM)
DFT Compiler
Design Compiler(R)


Initializing...
dc_shell>
DC Explorer

Light-Weight Logic Synthesis for What-If Analysis.
Initializing...
de_shell>

DC Family
DC Ultra (TM)
Power Compiler (TM)
DesignWare (R)
DC Expert (TM)
Design Vision (TM)
HDL Compiler (TM)
VHDL Compiler (TM)
DFT Compiler
Design Compiler(R)


Initializing...
dc_shell>
DC Explorer

Light-Weight Logic Synthesis for What-If Analysis.
Initializing...
de_shell>

DC Family – Logic Synthesis
DC Expert (DCE) DC Ultra (DCU) DC Graphical (DCG)
DCE DCU DCG

Shell dc_shell> dc_shell> or dc_shell-topo> dc_shell-topo>
License DC Expert License DC Ultra + DesignWare Foundation DC Graphical
Command dc_shell> compile dc_shell> compile_ultra dc_shell-topo> compile_ultra
Techniques Optimize design for area, timing, and All DCE features, plus following ： All DCU features, plus following:
power using WLM estimation. Provide • Multi-core • Reduce routing congestion during
following features: • Arithmetic optimization synthesis by using z-route based
• Hierarchical compile (Top down or • Register retiming congestion driven placement
bottom up) • Physical constraints are supported • Improved area and timing
• Full and incremental compile if topographical mode is used correlation with ICC
• Combinational and sequential (DCT). • Improved runtime and routability in
mapping When use “dc_shell –topographical” to ICC by using Synopsys Physical
• Timing borrow for latch based launch DC in DCT mode (shell prompt Guidance (SPG) technology, which
design timing optimization will be dc_shell-topo>), with additional pass seed placement to ICC
• Timing analysis license, following additional features
• Command-line interface and GUI are enable:
• MV
• MCMM
• Placement and optimization
technology that shared with ICC

DC Synthesis Flow
Synthesis = Translate + Optimize + Map
residue = 16’h0000;
if (high_bits == 2’b10)
residue = state_table[index];
Translate : dc_shell> read_file
else
state_table[index] = 16’h0000;
HDL Source
Optimize + Map :
dc_shell> compile(_ultra)
Generic Boolean
(GTECH)
Target Technology
DC Synthesis Flow - Steps to Perform Synthesis
Generate HDL
Source Code
Library Setup
HDL in
Constraining
Synthesis
Compile

Generate HDL
Source Code
Library Setup
HDL in
Constraining
Synthesis
Compile

Generate HDL
Source Code
• $link_library : {* mem.db $synthetic_library}

• $target_library: {sc.db}
Library Setup • $symbol_library: {generic.sdb}
• $synthetic_library: {dw_foundation.sldb}
• standard.sldb don’t have to be in $synthetic_library, it is built-in DC
HDL in
Constraining
Synthesis
Compile

Generate HDL
Source Code
Library Setup
• dc_shell> analyze ; elaborate

• dc_shell> read_file –format verilog | vhdl | db | ddc
HDL in • Presto reader on/off effect elaborate result
• set hdlin_* variables to control HDL in process
Constraining
Synthesis
Compile

• HDL-in Methods: analyze+elaborate VS. read_file

– Analyze:
– Reads HDL (only VHDL or Verilog) source file and performs syntax checking and Synopsys rule checking
– Checks errors without creating generic logic for the design
– Creates intermediate format for HDL code
– Stores intermediate files in location defined by define_design_lib command
– Example: dc_shell> define_design_lib work –path WORK
dc_shell> analyze -library work -format verilog my_design.v
dc_shell> ls WORK
. .. DFF.mr dff-verilog.pvl dff-verilog.syn
– Elaborate:
– Reads the intermediate files and translate the design into its GTECH representation
– Allow changing of parameter values defined in the source code
– Performs link automatically

• HDL-in Methods: analyze+elaborate VS. read_file

– read_file:
– Performs the same operations as analyze and elaborate in one step
– Does not create any intermediate files for Verilog
– Unable to specify parameter values in command-line
– Does not execute link automatically
– Reads several more formats, for example, db, lsi, mif, …
• Presto:
– Is enhanced HDL reader
– Increased elaboration speed
– Increased capacity in supporting additional language construct
– Variable hdlin_enable_presto set to false to turn off Presto (default true).

Generate HDL
Source Code
Library Setup
Design:
• dc_shell> analyze ; elaborate • GTECH
• dc_shell> read_file –format verilog|VHDL
HDL in representation
• Presto reader on/off effects elaborate result • With DW
• set hdlin_* variables to control HDL in process components
Constraining
Synthesis
Compile

Generate HDL
Source Code
Library Setup
HDL in
• Design environment:
• Operating condition
• Wire Load Model (WLM)
Constraining
Synthesis • System interface
• SDC
• Area
• Design Rule
Compile

• Operating condition:
• Select min/max operating condition from db
Generate HDL • At lease max condition needed
Source Code • Wire Load Model (WLM)
• Select one wire load model from db
1 Wire Loading Model:

Library Setup 2
3 Name : TSMC18_Conservative
4 Location : slow
5 Resistance : 0
6 Capacitance : 1
HDL in 7 Area : 1
8 Slope : 0.005702
9 Fanout Length Points Average Cap Std Deviation
10
---------------------------------------------------
Constraining 11 1 0.00
Synthesis 12 2 0.01
13 3 0.01
14 4 0.01
15 5 0.02
Compile 16 6 0.02
17 7 0.03
18 8 0.04
19 9 0.05
20 10 0.06
• set_wire_load_model -library slow -name TSMC18_Conservative

• set_wire_load_mode top | enclosed | segmented
• SDC
• Area: set_max_area 0 Versus set_max_area 90%_of_target
• Design Rule

Automatic Area Ungrouping
Generate HDL
Source Code High-Level Optimization
Datapath Optimization
Multiplexer Optimization and Mapping

Library Setup
Sequential Mapping
HDL in Boolean Optimization and Mapping
Auto-Uniquification
Constraining
Synthesis
Implement Synthetic Parts
Timing-Driven and Power-Driven Combinational

Compile Optimization
Delay and Leakage Optimization
Design Rule Fixing
Area Recovery

DC Optimization Fundamentals
- High Level Optimization (HLO) and Datapath Optimization
 During HLO, DC performs arithmetic simplification and resource sharing.

a b a b c d
 Arithmetic Simplification: 0 0 0 0 0 0
 a+b+c+d (a+b)+(c+d) +1 0 c
+1 1 +
 a+b-a b +2 0 d +
 a*2*3 a*6
+ 2
3
 Resource: A resource is an arithmetic or comparison operator read in as part of an HDL design.

 Resource Sharing: Reduce the hardware needed to implement operators such as adder (+). Without
this feature, each operator + builds an adder, these repetition of hardware increases the area of design.
 Common sub-expressions identification: X=A>B; Y=A>B&&C; TEMP=A>B;X=TEMP;Y=TEMP&&C;
 X=C+B+A; Y=A+D+B; TEMP=A+B;X=TEMP+C;Y=TEMP+D;
C B D B A B
+ A + A C + D
+ + + +
X Y X Y
 B (1) < C (2) < D (3) < A (4)

DC Optimization Fundamentals
- High Level Optimization (HLO) and Datapath Optimization
 Datapath Optimization performs datapath extraction and datapath implementation.

 Datapath: + - +
 It refers to the structure formed by connected synthetic operators in the gtech design that manipulates data.
 Datapath extractor transforms arithmetic operators into datapath blocks. It includes as much directly connected
synthetic operator as possible into datapath block. The purpose is to build large carry-save tree, to utilize carry-save
arithmetic technique for better timing and area QoR.
 Carry-save arithmetic technique: A high performance data arithmetic technique, lead to better timing
and area QoR. Use adder (+) as an example:
1 0 111 0 1 0 1 0 1 0 11 0 1 1 0 111 0 1 0 1 0 1 0 11 0 1
+ 100 0101011101001 + 1 0 0 0 1 0 1 0 111 0 1 0 0 1
1 0 1 0 0 0 1 0 11 0 0 1 0 11 0 2011202021202102
10000101100010001001100010010010
 CPA: carry-propagate adder: propagate carry to the left bit, and delay is proportion to n (bit num of data).
 CSA: carry-save adder: does not propagate carry, delay is independent to n. It performs addition for each bit
simultaneously, and produce an intermediate result for each bit. The intermediate result can be used to :
A. interpret final result through several-steps manipulation, including conditional assign and shift
B. pass to next stage CSA adder.
 In order to pass the intermediate result to next stage adder, the connection to the 2nd adder should be transformed,
such as adding more redundant bits.
 The last adder should be a CPA adder, to interpret the final result. E.g.: A (CSA) B (CSA) C (CPA) D
 So it is best to include as much connected arithmetic operators as possible to be transformed to a datapath block, to
achieve best QoR
 Datapath Implementation: Extracted datapath blocks are implemented by Design Ware datapath
generator.

Thank You

Design Compiler Introduction: Yi Zhang Jan 30, 2015

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Design Compiler Introduction

© 2015 Synopsys, Inc. All rights reserved. 1

• DC in ASIC Design Flow

© 2015 Synopsys, Inc. All rights reserved. 2

• GTECH library (gtech.db): generic technology-independent library cells, no physical info.

© 2015 Synopsys, Inc. All rights reserved. 3

Describe Design in Text Editor;

Check for Functional

• Insert Scan Logic to Netlist

© 2015 Synopsys, Inc. All rights reserved. 4

Version J-2014.09-SP2 for RHEL64 -- Nov 25, 2014

This software and the associated documentation are confidential and

© 2015 Synopsys, Inc. All rights reserved. 5

Version J-2014.09-SP2 for RHEL64 -- Nov 25, 2014

This software and the associated documentation are confidential and

© 2015 Synopsys, Inc. All rights reserved. 6

Version J-2014.09-SP2 for RHEL64 -- Nov 25, 2014

This software and the associated documentation are confidential and

© 2015 Synopsys, Inc. All rights reserved. 7

Version J-2014.09-SP2 for RHEL64 -- Nov 25, 2014

This software and the associated documentation are confidential and

© 2015 Synopsys, Inc. All rights reserved. 8

Version J-2014.09-SP2 for RHEL64 -- Nov 25, 2014

This software and the associated documentation are confidential and

© 2015 Synopsys, Inc. All rights reserved. 9

Version J-2014.09-SP2 for RHEL64 -- Nov 25, 2014

This software and the associated documentation are confidential and

© 2015 Synopsys, Inc. All rights reserved. 10

Version J-2014.09-SP2 for RHEL64 -- Nov 25, 2014

This software and the associated documentation are confidential and

© 2015 Synopsys, Inc. All rights reserved. 11

Version J-2014.09-SP2 for RHEL64 -- Nov 25, 2014

This software and the associated documentation are confidential and

© 2015 Synopsys, Inc. All rights reserved. 12

Version J-2014.09-SP2 for RHEL64 -- Nov 25, 2014

This software and the associated documentation are confidential and

© 2015 Synopsys, Inc. All rights reserved. 13

Version J-2014.09-SP2 for RHEL64 -- Nov 25, 2014

This software and the associated documentation are confidential and

Version J-2014.09-SP2 for RHEL64 -- Nov 25, 2014

© 2015 Synopsys, Inc. All rights reserved. 14

Version J-2014.09-SP2 for RHEL64 -- Nov 25, 2014

This software and the associated documentation are confidential and

Version J-2014.09-SP2 for RHEL64 -- Nov 25, 2014

© 2015 Synopsys, Inc. All rights reserved. 15

DCE DCU DCG

© 2015 Synopsys, Inc. All rights reserved. 16

© 2015 Synopsys, Inc. All rights reserved. 18

© 2015 Synopsys, Inc. All rights reserved. 19

• $link_library : {* mem.db $synthetic_library}

© 2015 Synopsys, Inc. All rights reserved. 20

• dc_shell> analyze ; elaborate

© 2015 Synopsys, Inc. All rights reserved. 21

• HDL-in Methods: analyze+elaborate VS. read_file

© 2015 Synopsys, Inc. All rights reserved. 22

• HDL-in Methods: analyze+elaborate VS. read_file

© 2015 Synopsys, Inc. All rights reserved. 23

© 2015 Synopsys, Inc. All rights reserved. 24

© 2015 Synopsys, Inc. All rights reserved. 25

1 Wire Loading Model:

• set_wire_load_model -library slow -name TSMC18_Conservative

© 2015 Synopsys, Inc. All rights reserved. 26

Automatic Area Ungrouping