Advance Digital System Design Advance Digital System Design Advance Digital System Design Advance Digital System Design (VHDL) (VHDL) (VHDL) (VHDL)

Advance Digital System Design
[VHDL]
Charoen Vongchumyen
Computer engineering
King Mongkut’s Institute of Technology Ladkrabang, Thailand
Jan 2010
2 VHDL : Tong+ Jan 2010
VHDL
What is VHDL?
Why we have to learn VHDL?
How do we learn VHDL?
When do we learn VHDL?
Where do we learn VHDL?

Digital design
What is Digital design

&
Why ?

Introduction
I t d ti
&
Overview
What is VHDL ?
VHSIC ((Veryy High
g Speed
p Integrated
g Circuit))
Hardware Description Language
Modeling DIGITAL Electronic Systems
Both Concurrent and Sequential statements

VHDL History
Department of Defense (DoD) developed in

1981
IEEE 1076-1987 Standard (VHDL’87)
IEEE 1076-1993
1076 1993 Standard (VHDL
(VHDL’93)
93)
VHDL Limitation

Hardware Description
p Language
g g ((HDL))
“The VHDL is
“Th i a software
ft programmingi language
l usedd to
t
model the intended operation of a piece of hardware, similar
t Verilog-HDL.”
to V il HDL ”
U off th
Use the VHDL LLanguage
1. Documentation Language: To provide human and machine
readable
d bl documentation
d i
2. Design Language: To provide a structure reflecting
hardware design and hierarchy and provide methods to
handle complexity by partitioning the design.

Hardware Description Language (HDL)
3. Verification Language : To provide a concurrent method

verifying hardware interaction and provide constructs for
stimulating a design.
4. Test Language : To provide ability to generate test vectors,
multiple testbench strategies and method to write self
checking code.
5. Synthesis Language : To provide high-level constructs that
can be translated to Boolean equations and then translate
them to ggate as well as to pprovide
constructs that can be optimized.

Electronic System
y Design
g
S
System D
Design
i S Specification
ifi i
Hardware/Software
Co Design
Co-Design
Hardware Design
g Software Design
Specification Specification
ASIC
FPGA
Boards and
PLD Systems
Std Parts

Top
Top-
p-Down Design
g
PCB 1 PCB 2
SYSTEM
The top-level
top level system is modeled for
uP ROM RAM
ASIC1 ASIC2 FPGA functionality and performance using a high-
A B
level behavioral description.
p
RTL code RTL code
C
RTL code
ASIC
RTL
synthesis
RTL
synthesis
RTL
synthesis Each major component is modeled at the
behavioral level and the design is simulated
again for functionality and performance.
ASIC
Test synthesis
A B Each major component is modeled at the gate

C
ASIC level and the design
g is simulated again
g for
Layout synthesis
timing, functionality and performance.

Levels of Abstraction : Capture
p
Editing VHDL Code Behavioral

Block Capture Behavioral Synthesis
V System Level Tools
H
D RTL
L
Logic Synthesis
Schematic Capture Logic
Place and Route
Layout Tools Layout

Levels of Abstraction : Definition
inputs outputs Hardware system specification

Function Behavioral Standard parts models
ASIC/FPGA design for synthesis

Dff Dff RTL Synthesizable models
Gate level design

Logic PLD design
Full custom design

Layout

Tradeoffs Between Abstraction Levels
Faster
simulation/entry
i l ti / t Less detailed
Behavioral
RTL
Logic
Layout
L t
Slower More detailed
simulation/entry

The Benefits of Usingg VHDL
D
Design
i att a higher
hi h llevell
¾Find problems earlier
Implementation
I l t ti independent
i d d t
¾Last minute changes
¾D l implementation
¾Delay i l i decisions
d ii
Flexibility
¾Re-use
¾Choice of tools, vendors
Language based
¾Faster design capture
¾Easier to manage
VHDL Organizations
g
VHDL International
¾ Promoting use of VHDL
¾ Quarterly publication, “Resource Book”
¾ “Simulator
Simulator Certification Test Suite
Suite”
IEEE Committees
¾ VASG : defining the language : various others too (VASG :
VHDL Analysis and Standardization Group)
Europe
¾ European
E chapter
h off VASG
¾ VHDL Forum for CAD in Europe
¾ VHDL Newsletter, published by Esprit project
¾ Regional user groups : VHDL-UK, etc . . .
Newsgroups
¾ comp.lang.vhdl
Digital
i i design
i
with
FPGA & CPLD
Standard IC
DIP Package 4 Nand gate Dual binary counter

Evolution on digital
g design
g
TTL = Transistor Transistor Logic

CMOS p y Metal Oxide Silicon
= Complementary
PLD = Programmable Logic Device
CPLD = Complex Programmable Logic Device
FPGA = Field Programmable Gate Array

CPLD
Xilinx
XC9536XL
800 Gates

FPGA
Xilinx
Spartan-II XC2S15
15 00 Gates
15,00
• Delay-Locked Loop (DLL)

• Configurable Logic Block (CLB)

FPGA,, CPLD & MCU
Embedded MCU in FPGA : PicoBlaze
System On a Chip(SOC)

FPGA & CPLD Design
g flow

Design
g pprocess
Design entry
¾ Schematic
¾ HDL : VHDL
VHDL, Verilog
¾ State diagram
Design synthesis
¾ Netlist files
¾ XST
¾ EDIF

Design
g pprocess
Design testing & Verification
¾ Behavioral simulation
¾ Functional simulation
¾ Timing simulation
Design
g implementation
p
¾ Translate (Netlist + Constrains)
¾ Mapping
¾ Place & Route
¾ Programming file generation
¾ Fitting (CPLD)
Programming (.bit, .jed)
ISE WebPACKTM

Development
p board
Performance
Reliability
Functionality
Reasonable price
www.ailogictechnology.com

VHDL
VHDL
Basic & introduction
VHDL Basic & Introduction
VHDL = VHSIC Hardware Description Language

(VHSIC = Very High Speed Integrated Circuit)
Started by DoD, USA for military used

High
g level language
g g look like Pascal
IEEE standard 1076 - 1987 (VHDL87)
IEEE standard 1076 - 1993 (VHDL93)
( )
IEEE standard 1076 - 2000
IEEE standard 1076 - 2002
IEEE standard 1164 – 1993 (std_logic, std_ulogic)
IEEE standard 1076.3
1076 3 – 1997 (Synthesis packages )
VHDL Structural elements
Entity declaration
¾ Interface definition
¾ Input
p and output
p signal
g ((Ports))
Architecture
¾ Architecture bodyy
¾ Relation of input and output
¾ Circuit behavior
Package
¾ Library : Constants, Procedures, Data types, Components
Configuration
¾ Match entity declaration and architecture
VHDL Basic : Example
p
Example of 2 to 4 decoder

p
Entity declaration Architecture

p
VHDL 87 code

p
VHDL 93 code

Signal
g Concurrency
y
Concurrent statement

Compact
p style
y

Bus style
y

VHDL
#2
VHDL General rules
Case insensitive
¾ A_Bus = a_bus
¾ Address_aBC = aDDRESS_Abc
Each statement end with “;”
¾ A_Variable := B_Variable;;
¾ C := X; D := Y;
¾ Data_0 <= Data_5;; Data_1 <= Data_2;;
Comment with “- “-”
¾ Data_0
Data 0 <= Data_5;
Data 5; -- Signal Data_5
Data 5 to signal Data_0
Data 0

VHDL General rules

Namingg
VHDL 87 identifiers
Use only
¾ Letter
¾ Number
¾ Underscore “_”
Rules
¾ Start with letter
¾ No space
¾ No repetitive underscore
¾ Not end with underscore
¾ No reserved word
Reserved words

Example
p of naming
g
ARCHI, aRChi , archi Right; Same name

HALF_ADDER Right
g
HALF_ _ADDER No; Double underscore
HALF ADDER_ No; Space and end with underscore
74LS
74 LS00
00 No; Start with number
open No; Reserved word

Port mode
In : receive signal from other circuit

Out : send signal to other circuit
Inout : receive/send signal to/from other circuit
((bidirectional))
Buffer : Output that can feed back signal to circuit
(A id thi
(Avoid this mode)
d )

std_logic
g & std_logic
g _vector
'U'
U = Uninitialized
'X' = Unknown
'0' = Low (Logic‘0’)
g (Logic‘1’)
'1' = High g
'Z' = High impedance
'W' = Weak
W k unknown
k
'L' = Weak low
'H' = Weak high
' - ' = Don
Don'tt care
std_ulogic
g VS std_logic
g
bit has only two state, “0” and “1”

std_logic
g is a subtype
yp of std_ulogic.
g
(including std_ulogic_vector)
Same logic with std_logic, 9 states
Resolve function for multiple driven
Not predefine type in IEEE Std 1076
Have to use IEEE std_logic_1164 package

std_ulogic
_ g & std_logic
_ g
2 to 4 decoder; std_logic type

std_ulogic
_ g & std_logic
_ g
2 to 4 decoder; std_logic_vector type

Objects
j
Four type of objects in VHDL

Constant
Signal
Variable
i
File

Constant
Use define constant value (never change)
constant CONSTANT
CONSTANT_NAME
NAME : TYPE [ :=
: VALUE ];
Ex. constant WIDTH : integer := 16 ;

constant PI : real := 3.141592 ;

Signal
g
Signal is an internal wire,

wire not port
Use to communicate with internal circuit
(Concurrent statement)
Use “<=” (signal assignment) to assign value
Have to be the same data type
Global, can use in every architect even procedure
If use in sequential
q statement,, Update
p its value
when end of process, procedure or function

Signal
g
Use define internal signal (can change its value)
signal SIGNAL_NAME : TYPE [ := INITIAL_VALUE ];
Ex. signal Q_tmp : integer range 0 to 9 ;

signal AX : integer range 0 to 15 := 0 ;
signal B : std_logic_vector (0
(0 to 31)
31) ;
- - B(
B(00) = MSB, B(31
B(31)) = LSB
signal C : std_logic_vector
std logic vector (3
(3 downto 0) ::= “0000
“0000
0000”” ;
- - C(
C(33) = MSB, C(0
C(0) = LSB
signal X_CLK
X CLK : std_logic
std logic ;
Signal
g
MUX 2:1
Define only the signal not in port list

Signal
g
MUX 2:1, Three

Th partial
ti l circuits
i it

Signal
g
MUX 2:1, One

O big
bi circuit
i it (No
(N signal
i l needed)
d d)

Variable
Like signal,
signal But use only in sequential statement
Use “:=” (variable assignment) to assign value
Have to be the same data type
Local, can use only in its process, procedure of function
Update its value immediately
Can not exchange data outside sequential statement
((have to assign
g to signal
g or p
port to exchange
g data))
Temporary storage in process

Variable
Use define internal process storage
signal VARIABLE_NAME : TYPE [ := INITIAL_VALUE ];
Ex. variable A_IN : integer range 0 to 9 ;

variable B : std_logic_vector (3
(3 downto 0) := ““0000
0000”” ;
- - B(
B(33) = MSB, B(0
B(0) = LSB
variable QX : std_logic_vector (0
(0 to 7) ;
- - QX(
QX(00) = MSB, QX(7
QX(7) = LSB
variable X : std_logic ;
variable Y : std_logic
std logic := ‘0
‘0’ ;
Data Types
yp & Subtypes
yp
Bit type in IEEE Std 1076

Note : can not use with + - *
Data Types
yp & Subtypes
yp
Integer type in IEEE Std 1076

Note : range -2,147
147,,483
483,,647 to 2,147
147,,483
483,,647
Data Types
yp
Four class of data types in VHDL

Scalar
Composite
Access
File
Note : Only
y scalar and composite
p types
yp are synthesizable,
y
The other two are for simulation or RAM initialization.

Scalar Type
yp
Four types of scalar

Enumeration
Integer
Physical
Floating point
Note : Enumeration and integer
g are “Discrete types”,
yp
Integer, physical and floating point are “Numeric types”.

Enumeration Type
yp
Predefined in IEEE Std 1076 (Standard package)

Character : Alphabets in ISO 8859
8859--1:1987;
1987; 256 chars
Bit : Logic ‘0’ and ‘1’
Boolean : FALSE or TRUE
SEVERITY_LEVEL : NOTE, WARNING, ERROR and
FAILURE
FILE_OPEN_KIND : READ_MODE, WRITE_MODE and
APPEND_MODE
APPEND MODE
FILE_OPEN_STATUS : OPEN_OK, STATUS_ERROR,
NAME_ERROR, MODE_ERROR
User Defined : Enumeration Type
yp
type
yp BOOLEAN is ((FALSE,, TRUE)) ;
type BIT is (‘0
(‘0’, ‘1
‘1’) ;
type COLOR is (BLUE
(BLUE, GREEN
GREEN, YELLOW
YELLOW, RED);
type LOGIC_LEVEL is (‘0
(‘0’, ‘1
‘1’, ‘Z’); - - Base type
subtype BIT_LOGIC is LOGIC_LEVEL range ‘0
‘0’ to ‘1
‘1’ ; - - Subtype
Subtype is better than new type,

Can use the same operator with base type
type.

Integer
g Type
yp

– (231 - 1) range -2,147
147,,483
483,,647 to 2,147
147,,483
483,,647
“Natural” is a predefined subtype of integer (base type)
range 0 to 2,147
147,,483
483,,647
“Positive”
Positive is a predefined subtype of integer (base type)
range 1 to 2,147
147,,483
483,,647

Integer
g Type
yp
type
yp INTEGER is range
g -2147483647 to 2147483647;
2147483647;
subtype NATURAL is integer range 0 to 2147483647;

2147483647;
subtype
b POSITIVE iis iinteger range 1 to 2147483647
2147483647;;
type WORD_INDEX is range 31 downto 0;
type BYTE_LENGTH is range 0 to 255;

255;
subtype HIGH_BIT_LOW
HIGH BIT LOW is BYTE_LENGTH
BYTE LENGTH range 0 to 127
127;;

Physical
y Type
yp
is “time” range -2,147
147,,483
483,,647 to 2,147
147,,483
483,,647
type
yp DURATION is range
g -2147483647 to 2147483647
units
fs; - - femtosecond
ps = 1000 fs; - - picosecond
ns = 1000 ps; - - nanosecond
us = 1000 ns; - - microsecond
ms = 1000 us; - - millisecond
sec = 1000 ms; - - second
min = 60 sec; - - minute
end units ;
Note : Xilinx synthesis tool is ignore.
Floatingg Point Type
yp ((Real))

range -1.0E38 to +1.0E38
+1
10
10..2
- 15
15..264
12
15
15..3 ns
12
12..7 E-6
- 2.35 E10
N
Note: Whi
Which
h one iis wrong
Composite
p Type
yp
Tow types of composite types

Array
Record

Arrayy Type
yp
Multi
Multi--value of the same type
Up to 3 dimensional array (Xilinx tools)
Predefined in IEEE Std 1076 (Standard package) are
“string” and “bit_vector”
¾ “string”
g is one dimensional arrayy of character
¾ “bit_vector” is on dimensional array of bit

Arrayy Type
yp
User defined : Constrained and Un constrained array

type BIT_VECTOR is array (NATURAL range <>) of BIT;
- - Unconstrained array
type STRING is array (POSITIVE range <>) of CHARACTER;
type NIBBLE is array (3

(3 downto 0) of BIT;
- - Constrained array
subtype BYTE is BIT_VECTOR ((7

7 downto 0);
- - Constrained array
y

Arrayy Type
yp
1 X 1 Dimensional
type
y DATA_ROM
_ is array
y (4095
(4095 downto 0) of
BIT_VECTOR (7
(7 downto 0);
- - If all ready defined BYTE
subtype BYTE is BIT_VECTOR (7

(7 downto 0);
type
t DATA_ROM
DATA ROM iis array (4095
(4095 downto
d t 0) off BYTE;
BYTE

Record Type
yp
Same as array type BUT
Multi
Multi--value of the “DIFFERENCE” type
type CONTROL_BUS is record
R_W : bit;
DATA_BUS
_ : bit_vector
_ (7 downto 0);
(7
ADDR_BUS : integer range 0 to 1023;

1023;
CE : bit;
bit
end record;

Access & File
Later explain.

IEEE Std 1164
1164--1993 Data Type
yp
In practical “0
“0”, “1
“1” and “Z”
Z ( high impedance ) are enough
But “Bit” have only ““0

0” and ““11”
std_logic ( std_logic_vector) and
std_ulogic ( std_ulogic_vector) are needed
std_logic
g & std_logic
g _vector are “Resolved” type
yp
std_ulogic & std_ulogic_vector are “Unresolved” type
Resovled type use resolved function for “Multiple driven”

std_logic
g and std_ulogic
g
Predefined in IEEE Std 1164

type STD_ULOGIC is ( ‘U’, - - Uninitialized
‘X’,, - - Forcingg Unknown
‘0’, - - Forcing 0
‘1’, - - Forcing 1
‘Z’, - - High Impedance
‘W’ - - Weak
‘W’, W kU Unknown
k
‘L’, - - Weak 0
‘H’, - - Weak 1
‘ - ’ - - Don’t care
);
std_logic
g and std_ulogic
g
subtype
yp STD_LOGIC is resolved STD_ULOGIC;;
subtype X
X01
01 is resolved STD_ULOGIC range ‘X’ to ‘1
‘1’;
- - (‘X’,
(‘X’ ‘0
‘0’,
’ ‘1
‘1’)
subtype X01
X01ZZ is resolved STD_ULOGIC range ‘X’ to ‘Z’;
- - (‘X’, ‘‘00’, ‘1
‘1’, ‘Z’)
subtype UX01
UX01 is resolved STD
STD_ULOGIC
ULOGIC range ‘U’
U to ‘1
‘1’;;
- - (‘U’, ‘X’, ‘0
‘0’, ‘1
‘1’)
subtype UX
UX01
01Z
Z is resolved STD_ULOGIC range ‘U’ to ‘Z’;
- - (‘U’, ‘X’, ‘‘0

0’, ‘1
‘1’, ‘Z’)

Resolved Function in Std_logic
g 1164

std_logic
g _vector and std_ulogic
g _vector
type STD
STD_ULOGIC_VECTOR
ULOGIC VECTOR is array (natural range <>) of STD_ULOGIC;
STD ULOGIC;
t pe STD_LOGIC_VECTOR
type STD LOGIC VECTOR is array
arra (natural
(nat ral range <>) of STD_LOGIC;
STD LOGIC;

User Predefined
type NIBBLE is array ((33 downto 0) of STD_LOGIC;
subtype BYTE is std_logic_vector (7

(7 downto 0);
1 X 1 dimensional array
type DATA_ROM is array (4095

(4095 downto 0) of std_logic_vector ((7
7 downto 0);
Or
type DATA
DATA_ROM
ROM is array (4095
(4095 downto 0) of BYTE;

2 and 3 Dimensionals User Predefined
2 dimensionals array
type DATA_
DATA_22D is array ((15
15 downto 0, 7 downto 0) of std_logic
type A_DATA is array (0

(0 to 255,
255, 7 downto 0) of std_logic
3 dimensionals array
type DATA_
DATA_33D is array (0
(0 to 255,
255, 15 downto 0, 7 downto 0) of std_logic

IEEE Std 1164 Operators
p
Edge detection function

¾ rising_edge
ii d (CLK
CLK)) is
i CLK’event
CLK’ d CLK = ‘1’
t and
; CLK trigged with positive edge
¾ falling_edge (CLK
CLK)) is CLK’event and CLK = ‘0’
;CLK trigged with negative edge

IEEE Std 1164 Functions
Conversion function ((Types)

yp )

IEEE Std 1076
1076..3 Data Types
yp
“Unsigned” and “Signed” in Numeric_std

Numeric std or Numeric
Numeric_bit
bit
In form of 2’s complement

p
Use the same operators with integer
type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;
type SIGNED is array (NATURAL range <>) of STD_LOGIC;

IEEE Std 1076
1076..3 Functions
Conversion function (Types)
“*” = Explicit type conversions

7 Segments
g Decoder
Patterns and Truth table

7 Segments
g Decoder
std logic vector 1 x 1 dimensional constrained array

std_logic_vector
7 Segments
g Decoder
std logic vector 1 x 1 dimensional unconstrained array

std_logic_vector
7 Segments
g Decoder
unsigned
i d 1 x 1 dimensional
di i l constrained
t i d array
7 Segments
g Decoder
unsigned
i d 1 x 1 dimensional
di i l unconstrained
t i d array
VHDL
#3
VHDL Operator
p
Predefined operator IEEE Std 1076

Logical operator : and , or , nand , nor , xor และ xnor
Relational operator : = , /= , < , <= , > และ >=
Shift operator : sll , srl , sla , sra , rol และ ror
Adding operator : + , – และ &
Sign :+ , –
Multiplying operator : * , / , mod และ rem
Miscellaneous operator : ** , abs และ not
Order by priority
Logical
g Operators
p
IEEE Std 1076

bit, bit_vector and boolean only
Array : same size
IEEE Std 1164
std_logic
td l i (std_ulogic),
( td l i ) std_logic_vector
td l i t (std_ulogic_vector)
( td l i t )
Array : same size
O l d d llogical
Overloaded i l operators,
t Overloaded
O l d d function
f ti from
f 1076
IEEE Std 1076
1076..3
unsigned, signed
Array : same size
Overloaded operators
Highest
g priority
p y : not
No ( ) needed
Relational Operators
p
=, //=, >
>=, >,
> <<=, <
Equal priority
IEEE Std 1076 : Scalar and Discrete
IEEE Std 1076.
1076.3 : Signed and Unsigned
IEEE Std 1164 : Not supported
But Xilinx Synthesis Tool (XST) supported
std_logic
std logic (std_ulogic),
(std ulogic) std
std_logic_vector
logic vector (std
(std_ulogic_vector)
ulogic vector)
Left alignment with unequal array
01111 (Compare ?)
1110

Concatenation Operators
p
&
Concatenate two of 1 dimensional arrays
IEEE Std 1076
1076,, 1076
1076..3 supported
IEEE Std 1164 : Not supported
But Xilinx Synthesis Tool (XST) supported
<= “01
A <= 01”” & “1101
“1101
1101”;
”;; Equal to <= “011101
A <= 011101”;
”;;
<= ‘0’ & ““111
B <= 111”” & ““0011
0011”;
”; Equal to <== “01110011
B< 01110011”;
”;
<= A & B;
C <= Equal to <= “01110101110011
C <= 01110101110011””

Aggregate
gg g
Use to concatenate signal
Aggregate ::= ([choice => ] identifier {, [choice => ] identifier })
::= mean “can be replacement with”

Ex.
Ex
signal A : std_logic_vector (3
(3 downto 0); - - Assume
A <=
< ((‘0
(‘0’, ‘1
‘1’, ‘0
‘0’, ‘0
‘0’);
); - - Positional notation
A <= ((00 => ‘0
‘0’, 2 => ‘1
‘1’, 1 => ‘0
‘0’, 3 => ‘0
‘0’); - - Named notation
A <= ““0100 ”;;
0100”;

Arithmetic Operators
p
+,
+ - , *, /,
/ **, MOD,
MOD REM,
REM ABS
IEEE Std 1076
+ -, ABS
+, : numeric (Integer
(Integer, Floating point
point, Physical)
*, /, ** : Integer, Floating point
MOD, REM : Integer
g
None for bit and bit_vector
IEEE Std 1164
None for std_logic (std_ulogic), std_logic_vector (std_ulogic_vector)
Have to use packages : std_logic_signed or std_logic_unsigned (IEEE; Synopsis)
IEEE Std 1076.
1076.3
unsigned, signed
Have to use packages : Numeric_std
i
Type
yp conversion
VHDL did not allow to assign

g value to difference data type,
yp
So type conversion is needed.
Explicit type conversion, Closely related data type
Type conversion ::= type

Type_conversion type_mark
mark (expression)
::= mean “can be replacement with”

Type_mark mean resulted type

Explicit
p Type
yp Conversion
1) Integer
g or floatingg p
point
Same type but difference range
Integer
g to Floatingg p
point or vice versa
type
yp X is range
g 0 to 100 ; - - defined data
type Y is range 0 to 1000
1000;;
g
signal Q
QT : X;; - - defined signal
g
signal Q : Y ;
Q <= Y (QT) ; - - type conversion

Explicit
p Type
yp Conversion
2) Array
y
Same type of member and dimensional

Explicit
p Type
yp Conversion
2) Array
y
Same type of member and dimensional
signal QT : unsigned ((33 downto 0) ; - - defined data

signal Q : std_logic_vector (3
(3 downto 0) ;
Q <= std_logic_vector (QT) ; - - type conversion
Q(0
Q( 0) <= QT(
QT(0
0) ; - - same result
Q(1
Q( 1) <= QT(1
QT(1) ;
Q(2
Q( 2) <= QT(
QT(2
2) ;
Q(3
Q( 3) <= QT(3
QT(3) ;

Adder
Package
P k : std_logic_unsiged
d l i i d

Adder
P k
Package : Numeric_std;
N i d IIn/Out
/O std_logic_vector
d l i

Adder
Package
g : Numeric_std;
_ In/Out unsigned
g
Note : Top
Top--level port declaration must be
std_logic or std_logic_vector
Shift Operators
p
IEEE Std 1076
sll
ll : Shift Left
L ft Logical
L i l
srl : Shift Right Logical
sla
l : Shift Left
L ft Arithmetic
A ith ti
sra : Shift Right Aritgmetic
roll : Rotate
R t t LLeft
ft
ror : Rotate Right
sll srl rol

Shift Operators
p : IEEE Std 1076
signal A : bit_vector (7
(7 downto 0) := ““01110001
01110001”;
”; - - Assume
B <= A sll 2; B <= A(

A(55 downto 0) & ““00
00”;
”; B <= ““11000100
11000100””
C <= A srl 2; C <= ““00
00”” & A(
A(77 downto 2); C <= ““00011100
00011100””
D <= A sla 2; B <= A(
A(55 downto 0) & A(
A(00) & A(
A(00);
D <= ““11000111
11000111””
E <= A sra 2; E <= A(
A(77) & A(
A(77) & A(
A(77 downto 2);
E <= ““00011100
00011100””
1) A(
A(55 downto 0) is “Slices of array” A =
A(55)&A(
A( )&A(44)&A(
)&A(33)&A(
)&A(22)&A(
)&A(11)&A(
)&A(00)
2) A(
A(77 downto 2) is “Slices of array” A =
A(7
A( 7)&A(
)&A(66)&A(
)&A(55)&A(
)&A(44)&A(
)&A(33)&A(
)&A(22)
Shift Operators
p : IEEE Std 1164
Can not use shift operator with std_logic_vector ( Not supported )

But can use this technique.
q
signal A : bit
bit_vector
vector (7
(7 downto 0) := “01110001
“01110001
01110001”;
”;; - - Assume
B <= A ssll 2; - - not

o supported
suppo ed
B <= A(
A(55 downto 0) & ““00
00”;
”; B <= ““11000100
11000100”” - - use this technique

Shift Operators
p : IEEE Std 1076.
1076.3
Unsigned and Signed.
signal U1
U1 : UNSIGNED (7
(7 downto 0) := “01101011
“01101011”” ;
signal U2
U2 : UNSIGNED ((7
7 downto 0) := “11101011
“11101011”” ;
signal S1
S1 : SIGNED ((7
7 downto 0) := ““01101011
01101011”” ;
signal
i l S2
S2 : SIGNED (7
(7 downto
d t 0) := “11101011
“11101011”” ;
signal N : NATURAL := 3 ;

Shift Operator
p
U & iinstead
Use d off ““sll”
ll” iin IEEE Std
S d 1164

Shift Operator
p
U ““sll”
Use ll” iin IEEE Std
S d 1076
1076..3

VHDL
General coding
General Codingg in VHDL
Only std_logic or std_logic_vector for

top-
p-level design
top g ( I/O port
p )
Three necessary parts
¾ Using the package
¾ Entity declaration
¾ Architecture body

General Codingg in VHDL
2 to 4 Decoder

Package
g Usingg
Must be place on top of the code
library LIBRARY_NAME;
use LIBRARY_NAME.PACKAGE_NAME.PACKAGE_PARTS;
Library
Lib : IEEE
Package : std_logic_1164
std_logic_1164
library IEEE;
use IEEE.std_logic_1164
IEEE.std_logic_1164.all;
.all;
Note : std.standard and work.work are already

y used

Entityy Declaration
Define input output of the system, Port.
entity ENTITY_NAME is
[ generic
i ( GENERIC DECLARATIONS) ; ]
[ port ( PORT DECLARATIONS) ; ]
end
d [[entity]
tit ] [ENTITY
[ENTITY_NAME]
NAME] ;
generic ( [GENERIC_NAME : TYPE [ := VALUE ] ] { ; GENERIC_NAME : TYPE [ := VALUE ] } ) ;
port ( [ PORT_NAME : mode TYPE ] { ; PORT_NAME : mode TYPE } ) ;
{...} = Multiple existed or not

[...] = Existed or not

Architecture
Describe behavior of designed circuit.
architecture ARCHITECTURE_NAME
ARCHITECTURE NAME of ENTITY
ENTITY_NAME
NAME is
{ DECLARATIVE_ITEM }
b i
begin
{ CONCURRENT_STATEMENT }
end [architecture] [ARCHITECTURE_NAME] ;

Declarative Items
Subprogram declaration and Subprogram body

Type
yp declaration and/or Subtype
yp declaration
Constant declaration and/or Signal declaration
Component declaration
File declaration
Attribute declaration and/or Attribute specification

Attributes
More detail on VHDL objects

objects. ( Signal or Variable )
Ex. Trig
Use for simulation and subprogram.
X ’ attribute_name
attribute_name = Name of attribute
X = Name of objects
“ ’” = Tick
Ti k
Note : (not “,”)

Attributes
LENGTH
LOW
RANGE

Attributes
Have 2 classes
¾ Predefined attributes
¾ User defined attributes
Kinds of attribute depend on its return value
¾ Value
¾ Type
¾ Range
¾ Function
¾ Signal
g

Predefined Attributes
1) Type attribute
Use with Enumeration,
Enumeration Integer and Physical

Type
yp Attribute
Ascending range ( 0 to 15 ) Descending range ( 15 downto 0 )
¾ T
T’left
left = T
T’low
low ¾ T
T’left
left = T
T’high
high
¾ T’right = T’high ¾ T’right = T’low
¾ T’leftof(X) = T’pred(X) ¾ T’leftof(X) = T’succ(X)
¾ T’rightof(X)
g ( ) = T’succ(X)
( ) ¾ T’rightof(X)
g ( ) = T’pred(X)
p ( )

Type
yp Attribute
type WORD is range 15 downto 0; - - 15
15,,14
14,,13
13,,12
12,,11
11,,10,
10,9,8,7,6,5,4,3,2,1,0 Descending
type ADDR is range -5 to 5 - - -5,-4,-3,-2,-1,0,1,2,3,4,5 Ascending range
type COLOR is (BL, G, Y, R);

2) Array attribute
Unconstrained 1 dimensional array,
array
Constrained X dimensional array.

127
tyype A
A11D is arrayy (3
(3 down
nto 0) of sstd_logic;
tyype A
A22D is arrayy (0
(0 to 15
15,, 7 downtto 0) of std_logic;
s ;
siignal Y : std_logiic_vector (31 down
nto 0);
VHDL : Tong+
Arrayy Attribute
Jan 2010
3) Signal attribute
Use with signal.
signal
Normally, Use for simulation.

‘event is use for synthesis.
Type
yp Attribute
C’event : Transition of signal, Edge trig.
C’event
C event and C = ‘1
‘1’ : rising_edge(
rising edge( C )
C’event and C = ‘0
‘0’ : falling_edge( C )
Rising
g_edge
g and Fallingg_edge
g are p
predefined in IEEE Std 1164
XST supported only : high, low, left, right, range, reverse_range,
length, pos, ascending, event and last_value
Other are ignored.

User Defined Attribute
User defined attribute is user constraints
Later
L t explain
l i

VHDL
Coding
VHDL Statements
Concurrent
C t statement
t t t
¾ All lines work in parallel.
Sequential statement

Concurrent Statements
Concurrent statements ( Dataflow descriptions )

¾ Simple signal assignment statement
¾ Selected signal assignment statement
¾ Conditional signal assignment statement
¾ Component
C t iinstantiation
t ti ti statement
t t t
¾ Generate statement
¾ Block statement
¾ Process statement
¾ Concurrent procedure calls

Simple
p signal
g assignment
g statement
Assign value to signal or port.
[ label : ] TARGET <= EXPRESSION ;
C <= A and B ;
X <= “00000000
“00000000”” ;
X <= (others => ‘0
‘0’) equal to X <= “00000000
“00000000””
X <= (others => ‘1
‘1’) equal to X <= “11111111
“11111111””

Selected signal
g assignment
g statement
Assign EXPRESSION to TARGET

when CHOICE match CHOICE_EXPRESSION.
[ label : ] with CHOICE_EXPRESSION select

TARGET <= { EXPRESSION when CHOICE { | CHOICE}
CHOICE}, }
EXPRESSION when CHOICE { | CHOICE};

[...]
[ ] = Existed or not

Selected signal
g assignment
g statement
Static expression - - > 3

Static range - - > 7 downto 4
Multi
Multi--value --> “0001
“0001
0001”” | “1000
“1000
1000””
Other left value --> “OTHERS”

Conditional signal
g assignment
g statement
Assign
A i EXPRESSION to
t TARGET
when CONDITION is “true”.
[ label :] TARGET <= { EXPRESSION when CONDITION else }

EXPRESSION ;

[...]
[ ] = Existed or not

MUX 4 : 1
Truth table

MUX 4 : 1
Selected signal assignment, MUX 4 : 1

MUX 4 : 1
Conditional signal assignment, MUX 4 : 1

MUX 4 : 1
Conditional signal assignment ( No concatenation ),

MUX 4 : 1

MUX 4 : 1 ( Bus )
Truth table

MUX 4 : 1 ( Bus )
Selected signal assignment, MUX 4 : 1 ( Bus )

MUX 4 : 1 ( Bus )
Conditional signal assignment, MUX 4 : 1 ( Bus )

VHDL
#4
Component
p
Hi
Hierarchical
hi l model
d l or Structural
St t l model.
d l
Component declaration.
¾ Declare the component before use.
Component instantiation statement.
¾ Create the declared component.
p

Component
p Declaration
Before using component

component.
Declare in architecture or package.
component COMPONENT_NAME
[ generic (GENERIC_DECLARATIONS)
(GENERIC DECLARATIONS) ]
[ port (PORT_DECLARATIONS) ]
end component ;
Generic and Port use the same format as Entity

Component
p Instantiation Statement
Concurrent statement.
statement
Create declared component as circuit.
INSTANCE_NAME : COMPONENT_NAME
[ generic map ( GENERIC_NAME => VALUE { , GENERIC_NAME => VALUE } ) ]
port map ( [PORT_NAME =>] SIGNAL_NAME { , [PORT_NAME =>] SIGNAL_NAME } );
Generic and Port use the same format as Entity

Positional and Named Association
[ PORT_NAME
PORT NAME =>
> ] iis th
the name off iinput/out
t/ t off th
the
component.
Positional association
¾ No PORT_NAME.
PORT NAME.
¾ SIGNAL_NAME must place in exactly order.
Named
N d association
i ti
¾ Must have PORT_NAME.
¾ Order in not necessary.

3 Bits adder usingg component
p

Generate Statement
For/Generate
¾ Suitable for repeatable statement.
¾ Suitable for duplication
p circuit.
If/Generate
¾ Operate only condition is TRUE.

Generate Statement
generate_label : for INDEX in DISCRETE_RANGE generate

{CONCURRENT_STATEMENT}
end generate [ generate_label ] ;
generate_label : if CONDITION generate

{CONCURRENT_STATEMENT}
end generate [ generate_label ] ;

1 Bit full adder
Truth table

1 Bit full adder

4 Bits adder usingg Generate

N Bits adder usingg Generate

2 – 32 Bits adder

Block Statement
Partition groups of concurrent statement.

For manage and verify.
Can have many blocks in code.
Nested block is acceptable
acceptable.
If have the same object name in nested block, use
local name firstly.
Simple and Guarded block
Only Simple is allow by XST

Simple
p Block
label : block
{BLOCK_DECLARATIVE_PART}
{BLOCK DECLARATIVE PART}
begin
{{CONCURRENT_STATEMENT}}
end block [ label ] ;
1) BLOCK_DECLARATIVE_PART
• use clause
• Subprogram declaration and Subprogram body
• Type declaration and/or Subtype declaration
• Constant declaration
• Signal declaration
• Component declaration
2) CONCURRENT STATEMENT
CONCURRENT_STATEMENT

Block Statement

Process Statement
[ label : ] process [ (SENSITIVITY LIST) ]
{PROCESS_DECLARATIVE_PART}
{PROCESS DECLARATIVE PART}
begin
{{SEQUENTIAL
Q _STATEMENT}}
end process [ label ] ;
1) PROCESS_DECLARATIVE_PART
• use clause
• Subprogram declaration and Subprogram body
• Type declaration and/or Subtype declaration
• Constant declaration
• Variable declaration
2) SENSITIVITY LIST; Every input that direct effect to the process
3) SEQUENTIAL STATEMENT
SEQUENTIAL_STATEMENT

Concurrent Procedure Calls
PROCEDURE_NAME [ ( [ NAME => ] EXPRESSION

{ ,[[ NAME =>
> ] EXPRESSION } ) ] ;
Call
C ll subprogram
b iinside
id architecture
hit t or block
bl k
Later explain

Sequential
q Statement
Orders are necessary.

Only in Process,
Process Function or Procedure
Procedure.
Every process is concurrent statement.
Describe behavior of the circuit.

Sequential
q Statement
Sequential Statement (Behavioral descriptions )

¾ Signal assignment statement
¾ Variable assignment statement
¾ if statement
¾ case statement
¾ Wait statement
¾ Loop statement

Signal
g Assignment
g Statement
Assign value to signal or port

port.
TARGET <= EXPRESSION ;

Variable Assignment
g Statement
Assign value to variable in Process,

Process Function or
Procedure only.
TARGET := EXPRESSION ;

If Statement
Look like Conditional signal assignment.

Only in Process.
Priorities of CONDITION are in order.
if CONDITION then {SEQUENTIAL_STATEMENT}

{ elsif CONDITION then {SEQUENTIAL_STATEMENT} }
[ else {SEQUENTIAL_STATEMENT} ]
end
d if
if;
If no “else”, Latch must be create to hold previous

output.

Case Statement
Look like Selected signal assignment.

Only in Process.
Priorities of CHOICES are NOT in order.
order
case EXPRESSION is
when CHOICES => {SEQUENTIAL_STATEMENT}
{ when CHOICES => {{SEQUENTIAL
Q _STATEMENT}} }
end case;
If no “OTHERS”, Latch must be create to hold previous

output
output.
MUX 4 : 1 usingg If Statement
With concatenation

MUX 4 : 1 usingg If Statement
Without concatenation

MUX 4 : 1 usingg Case Statement

D Flip
Flip-
p-Flop
p with Asynchronous
y Clear

D Flip-
Flip
p-Flop
p with Synchronous
y Clear

4 bits Countup
p Binary
y Counter

Decade Countup
p Binary
y Counter

Wait Statement
Use in Processes without sensitivity lists.

For stop process operation.
wait [ on SENSITIVITY_LIST ] ;
[ until CONDITION ] ;
[ for TIME¬_EXPRESSION ] ;
Wait on SENSITIVITY_LIST; wait till event occur.

Wait until CONDITION;; wait till condition is true.
Wait for TIME_EXPRESSION; time delay.

Wait Statement
Use in Processes without sensitivity lists.

For stop process operation.
wait [ on SENSITIVITY_LIST ] ;
[ until CONDITION ] ;
[ for TIME¬_EXPRESSION ] ;
Wait on, Wait until and Wait for.

Wait Statement as Risingg Edge
g Clock
Same operation as Rising_Edge(SIGNAL_CLOCK).
wait on CLK until CLK = ‘1

‘1’;
wait until CLK = ‘1
‘1’;
wait
i until
il CLK’event
CLK’ and
d CLK = ‘1
‘1’;
’
M t be
Must b first
fi t statement
t t t in
i the
th process.

D Flip-
Flip
p-Flop
p with Synchronous
y Clear

D Flip-
Flip
p-Flop
p with Synchronous
y Clear

Loop
p Statement
Like Generate statement, but use in sequencial.

For repeating the operation.
[ loop_label : ] [ ITERATION_SCHEME ] loop

{SEQUENTIAL_STATEMENT}
{ next [ loop_label ] [ when condition ] ; }
{ exit [ loop_label ] [ when condition ] ; }
end loop [ loop_label ] ;
1) ITERATION_SCHEME; Loop, For, While.
2) next; skip to next round(iteration)
3) exit; end loop

Basic Loop
p
Loop without ITERATION_SCHEME.

End with “next” and “exit”.
At least one “wait” in the loop.
[ loop_label : ] loop
end loop [ loop_label
loop label ] ;

While/Loop
p
Loop while CONDITION is TRUE.

Can not synthesis to circuit.
[ loop_label : ] while CONDITION loop


For/Loop
p
Loop while INDEX_NAME is in DISCRETE_RANGE.

No “Wait” in the loop.
[ loop_label : ] INDEX_NAME in DISCRETE_RANGE loop


4 Bits Shift Left Register
g

VHDL
Package Library
Package, Library, Subprogram
ROM,, RAM
VHDL
#6
VHDL
Testbench and TEXTIO

Testbench
Use to test circuit with simulation technique.

Test bench will p
provide test vector to testing
g component,
p ,
Unit under test (UUT) or Design under test (DUT) .
Output will be show in waveform, error report or data
file.
Testbench entity has no port (internal work only).

Testbench
Compare actual results to expected results are complex.

Report error on transcript windows in Xilinx should be
better.

Testbench Basic Statement
Wait : Stop
p the p
process.
Wait for : Stop the process for the time “wait for 100 ns;”
Assert
A t :W
Working
ki when
h condition
diti iis “FALSE”
working with “Report” and “Severity”
assert CONDITION_EXPRESSION
report TEXT_STRING
severity SEVERITY
SEVERITY_LEVEL;
LEVEL;
SEVERITY_LEVEL : NOTE, WARNING, ERROR and FAILURE

Testbench
And gate 2 inputs

Testbench
And gate 2 inputs

Testbench
And gate 2 inputs

Testbench with Assert Statement

Testbench with Assert Statement

Testbench : Too much p
propagation
p g delay
y

Testbench Construction
Not synthesis circuit.

Consists of 4 parts.
Entity declaration and Architecture (No ports).
Signal declaration; connect stimulus signal to UUT
port.
Instantiation of Top-
Top-level design.
Provide stimulus;; Gen clock,, reset and test vectors.

Clock Generation
constant Period : TIME := 200 ns; - - Declare a clock period constant
Clock <= not Clock after Period / 2; - - Clock generation
Clock <= not Clock after 100 ns; - - Clock generation : Period =
(100+
100+100)
100) ns, F = 5 MHz

Clock Generation
Process
constant Period : TIME := 200 ns;
- - Declare a clock period constant
begin
Clock <= ‘1
‘1’;;
wait for (Period / 2);
Clock <
<= ‘0
‘0’;
wait for (Period / 2);
end process;

Stimulus Generation
Stimulus1
Stimulus 1 : process
begin
Reset <= ‘1
‘1’;
wait for 100 ns;
CE <= ‘‘1
1’;
Reset <= ‘0
‘0’;
’
wait for 800 ns;
CE <= ‘0
‘0’;
wait for 100 ns;
wait ;
end process Stimulus
Stimulus11;

Stimulus Generation
S <= "00
00",
",
"01
01"" after 30 ns,
"11
11"" after 120 ns,
ns
"01
01"" after 150 ns;

Stimulus Generation Usingg TEXTIO
Read text file for test vector and send to UUT.

Using TEXTIO package.
STD_LOGIC_TEXTIO package for std_logic and
std_logic_vector.
_ g _

File Access
VHDL have no display

p y statement,, Using
g read and write
file for input and output.
Using TEXTIO package.
type LINE is access STRING ; - - A LINE is a pointer to a STRING value.

type TEXT is file of STRING ; - - A file of variable-
variable-length ASCII records
records.

File Type
yp Declaration
type FILE_TYPE_NAME
A iis file
fi off TYPE_NAME;
A
TYPE_NAME = Scalar type, Record type or Constrained array subtype

Object
j Declaration : File
file INPUT_OBJECT_FILE READ_MODE

INPUT OBJECT FILE : text open READ INPUT_FILE.text
MODE is “INPUT FILE.text’’ ;
- - VHDL
VHDL93
93
file OUTPUT_OBJECT_FILE
OUTPUT OBJECT FILE : text open WRITE_MODE
WRITE MODE is “OUTPUT
OUTPUT_FILE.text
FILE.text” ;
- - VHDL
VHDL93
93
file INPUT_OBJECT_FILE
INPUT OBJECT FILE : text in is “INPUT
INPUT_FILE.text
FILE text’’ ;
- - VHDL
VHDL87
87
file OUTPUT_OBJECT_FILE
OUTPUT OBJECT FILE : text out is “OUTPUT
OUTPUT_FILE.text
FILE text” ;
- - VHDL
VHDL87
87
INPUT FILE text OUTPUT FILE text = Text file
INPUT_FILE.text,OUTPUT_FILE.text file.
INPUT_OBJECT_FILE,OUTPUT_OBJECT_FILE = Temporary storage.

File Command
readline (INPUT_OBJECT_FILE,
(INPUT OBJECT FILE INPUT_LINE)
INPUT LINE) - - Reads new line from temp file
read (INPUT_LINE, VALUE) ; - - Reads a new object from the line.
write (OUTPUT_LINE, VALUE) ; - - Writes a new object into the line.
writeline (OUTPUT_OBJECT_FILE, OUTPUT_LINE) - - Writes a new line to temp
fileendfile (FILE_NAME) ; - - Returns boolean true if the end of file is reached.
use STD.TEXTIO.all ; or use IEEE. STD_LOGIC_TEXTIO.all ;

4 Bits Adder,, Testbench Using
g File

g File

g File
Input file Output file

g File

VHDL
END,
END EPISODE I

Advance Digital System Design Advance Digital System Design Advance Digital System Design Advance Digital System Design (VHDL) (VHDL) (VHDL) (VHDL)

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Advance Digital System Design

 Why we have to learn VHDL?

 How do we learn VHDL?

 When do we learn VHDL?

 Where do we learn VHDL?

3 VHDL : Tong+ Jan 2010

What is Digital design

4 VHDL : Tong+ Jan 2010

6 VHDL : Tong+ Jan 2010

 Department of Defense (DoD) developed in

8 VHDL : Tong+ Jan 2010

9 VHDL : Tong+ Jan 2010

3. Verification Language : To provide a concurrent method

10 VHDL : Tong+ Jan 2010

11 VHDL : Tong+ Jan 2010

A B Each major component is modeled at the gate

timing, functionality and performance.

12 VHDL : Tong+ Jan 2010

Editing VHDL Code Behavioral

Schematic Capture Logic

Place and Route

Layout Tools Layout

13 VHDL : Tong+ Jan 2010

inputs outputs Hardware system specification

ASIC/FPGA design for synthesis

Gate level design

Full custom design

14 VHDL : Tong+ Jan 2010

15 VHDL : Tong+ Jan 2010

DIP Package 4 Nand gate Dual binary counter

19 VHDL : Tong+ Jan 2010

TTL = Transistor Transistor Logic

20 VHDL : Tong+ Jan 2010

21 VHDL : Tong+ Jan 2010

• Delay-Locked Loop (DLL)

22 VHDL : Tong+ Jan 2010

Embedded MCU in FPGA : PicoBlaze

23 VHDL : Tong+ Jan 2010

24 VHDL : Tong+ Jan 2010

25 VHDL : Tong+ Jan 2010

27 VHDL : Tong+ Jan 2010

28 VHDL : Tong+ Jan 2010

VHDL = VHSIC Hardware Description Language

 Started by DoD, USA for military used

33 VHDL : Tong+ Jan 2010

Entity declaration Architecture

34 VHDL : Tong+ Jan 2010

35 VHDL : Tong+ Jan 2010

36 VHDL : Tong+ Jan 2010

37 VHDL : Tong+ Jan 2010

38 VHDL : Tong+ Jan 2010

39 VHDL : Tong+ Jan 2010

41 VHDL : Tong+ Jan 2010

42 VHDL : Tong+ Jan 2010

44 VHDL : Tong+ Jan 2010

ARCHI, aRChi , archi Right; Same name

45 VHDL : Tong+ Jan 2010

 In : receive signal from other circuit

46 VHDL : Tong+ Jan 2010

 bit has only two state, “0” and “1”

48 VHDL : Tong+ Jan 2010

2 to 4 decoder; std_logic type

Why we have to learn VHDL?

How do we learn VHDL?

When do we learn VHDL?

Where do we learn VHDL?

Department of Defense (DoD) developed in

Started by DoD, USA for military used

In : receive signal from other circuit

bit has only two state, “0” and “1”

Signal is an internal wire,

“Natural” is a predefined subtype of integer (base type)

subtype NATURAL is integer range 0 to 2147483647;

type WORD_INDEX is range 31 downto 0;

type BYTE_LENGTH is range 0 to 255;

Up to 3 dimensional array (Xilinx tools)

Predefined in IEEE Std 1076 (Standard package) are

type STRING is array (POSITIVE range <>) of CHARACTER;

type NIBBLE is array (3

subtype BYTE is BIT_VECTOR ((7

subtype BYTE is BIT_VECTOR (7

Same as array type BUT

But “Bit” have only ““0

std_logic ( std_logic_vector) and

std_ulogic & std_ulogic_vector are “Unresolved” type

Resovled type use resolved function for “Multiple driven”

Predefined in IEEE Std 1164