Sheikh Ashfaq Nabi

ashfaqsaraf@gmail.com

Koramangala,
Bangalore
Phone: +91-9717771517

Objectives

Looking forward to work with a team that provides an opportunity for growth not only technically but in
honing leadership qualities as well; also, a kind of environment that helps move forward in a manner so as
to encourage challenging the old work I have done in my previous companies. Open to leadership roles as
well.

Summary

▪ A total Experience of 9 (approx) years with the industry, and all 9 in DFT
• Experience of over 17 months at Wipro Technologies Ltd. in DFT domain in vector generation
(ATPG), Memory Bist and Top level activities from February 2010 to June 2011. Working as Team
Member, independently handling testing of multiple blocks.
• Worked with Freescale Semiconductors from July 2011 to June 2014 as DFT Design engineer
in the automotive division. During my time in Freescale I have worked on complex projects
implementing and verifying features like LBIST, Analog Expose mode, Complex clocking
features in DFT, Scan Insertion, LBIST verification, etcetera.
• Working with STMicroelectronics from June 2014 to January 2018 as a Technical Lead.
Worked on AC boundary Scan, Scan Insertion with Synopsys tools, A TPG vector generation,
Pattern simulation, Debug, Ip verification etcetera.
• Worked with Intel Singapore from 26 th January 2018 till the end of October 2018 as senior
Design engineer. During this period worked on the High-speed, like USB interface verification
and integration for Intel’s smart home division.
• B.Tech. (Electronics and Communication Engineering), 9.09 CGPA
• Designation (Last): Senior Design engineer
• Last Company: Intel Technologies Singapore.
• Current Job Status: Working on a personal project.

Project Specific Technical Skills

Technology Tools

Cadence NcSim, Cadence Encounter Test, TestKompress, Fastscan,

EDA Tools Mentor’s Lbist Architect, Fitsmem, Cadence RC, Integration tools like
tortoise from cadence,
 Design Compiler Synopsys, TetraMax, Formality.

Programming Languages C, Verilog, PERL, tcl.

Software Tools/Technologies MS Office, Vi.

VLSI DOMAIN/DESIGN
ASIC DESIGN.
SKILLS
Projects done at Wipro Technologies Ltd

1. ATPG Vector generation, testing, Mapping and Rambist for SRCv8x blocks.
The SRCv 8x6G is a PCIe Gen 3 to 8-port, 6 Gb/s SAS RAIDon- Chip (RoC)
controller designed for volume servers and blade applications. The SRCv 8x6G
Description
supports the SAS 2.1 specification.

Role DFT Engineer

Operating System(s) Unix, Windows
Skills MS Office, VLSI Design, Verilog, Vi
NCSim for Simulations, Encounter Test for vector generation and simulation, Verilog
Environment
for RTL
Owning blocks for ATPG vector generation and subsequent simulations of the same
Contribution with timing constraints and then translating these vectors for simulation at various
hierarchal levels inside the top level module.
Period From April 2010 to December 2010
Team Size 7 Engineers

2. ATPG Vector generation, testing, Mapping and Rambist for SRCv24x blocks.

The PM8015 SRCv 24x6G is a PCIe Gen 3 to 24-port, 6 Gb/s SAS RAID-on-Chip
Description (RoC) controller designed for enterprise servers and RBODs. The SRCv 24x6G
supports the SAS 2.1 specification.
Role DFT Engineer
Operating System(s) Unix,Windows NT
Skills MS Office,VLSI Design,Verilog,vi
NCSim for Simulations, Encounter Test for vector generation and simulation, Verilog
Environment
for RTL
Owning blocks for ATPG vector generation and subsequent simulations of the same
Contribution with timing constraints and then translating these vectors for simulation at various
hierarchal levels inside the top level module.
Period December 2010 to present
Team Size 6 Engineers

Projects done at Freescale semiconductors limited

1. MBIST generation, verification and simulation of vectors; BSDl verification on Anguilla

Silver taping out on 1st February 2012

Anguilla Silver is intended for industrial control, motion control, home appliances,
general-purpose inverters, smart sensors, fire and security systems, switched-mode
Description power supply, power management, UPS, Solar inverter, and medical monitoring
applications. It is a based on a HawkV3R1 32 bit DSC processor and is fabricated
using CMOS 90nm technology.
Role DFT Engineer
Operating System(s) Unix,Windows NT
Skills MS Office,Verilog,vi,Mbist architect, Wgl processor
Environment NCSim for Simulations, Mentors Mbist architect for generation, Verilog for RTL
Generation of MBIST logic, RTL verification, Testcase writing, Wgl generation,
Contribution Timing simulation of the wgls.
BSDL generation and the testcase verification for all JTAG needed requirements.
Period October 2011 to January 2012
Team Size 2 Engineers

2. MBIST integration and standalone verification; LBIST verification setup flow; LBIST
verification; Analog expose mode verification for Racerunner.

Racerunner is a is high end automotive MCU designed to support computation

intensive
application
• Customer Specific High End RADAR Systems: 10MSamples/sec, multiple
antennas,
hardware accelerated 16/24bit integer FFT
• Low/mid end RADAR: <= 10MSamples/sec, multiple antennas, hardware integer
FFT or software floating point FFT
• Motor Control for 2 Motors
• Braking
Description
• Safety application
• using one lockstep core (z4)
• optionally using two cores for non-safety functions (2x z7)
• using various communication interface incl. Ethernet, FlexRay, CAN, SPI, LIN,
IIC, SENT
• optionally keeping one or both z7 cores clocked off
• Data processing using two cores in decoupled mode (2x z7)
• booting from one of the z7 cores
• keeping the safety core (z4 lockstep system) clocked off
• optionally keeping the second z7 core clocked off
Role DFT Engineer
Operating System(s) Unix,Windows NT
Skills MS Office,Verilog,vi,Mbist architect, Wgl processor, Testkompress, Lbist architect
Environment NCSim for Simulations, Mentors Mbist architect for generation, Verilog for RTL
Mbist integration, standalone verification; Lbist verification setup flow, lbist
Contribution verification; Analog expose mode verification; ATPG vector generation(expected
with the flow of the project)
Period January 2012 to, expectedly November 2012
Team Size 7 Engineers

3. LBIST, EDT generations and Integration; LBIST verification setup flow; LBIST verification; Scan
Insertion; Testpoint Insertion; X-bounding and ATPG activities for Rainier.
 Rainier is a member of a new family of devices based on the eTPU timer. The device
will build on the legacy of the family, while introducing new features coupled with
higher throughput to provide substantial reduction of cost per feature and significant
performance improvement.
Description One paramount consideration in the implementation is the need to minimize power
dissipation while maintaining commercially acceptable die size. To assist in this goal,
low Vt transistors should be avoided in the design flow wherever possible, and if
necessary, must be limited to less that 0.5% of the transistor count. Additionally, quad
flop must be used to reduce power.
Role DFT Engineer
Operating System(s) Unix,Windows NT
MS Office,Verilog,vi,Mbist architect, Wgl processor, Testkompress, Lbist architect,
Skills RC,
Synopsys VCS, Mentor tools, perl
NCSim for Simulations, Mentors Mbist architect for generation, Verilog for RTL,
Environment
VCS for RTL,
LBIST, EDT generations and Integration; LBIST verification setup flow; LBIST
verification; Scan Insertion; Testpoint Insertion; X-bounding and ATPG activities for
Contribution
Rainier.

Period August 2012 to, expectedly March 2013

Team Size 5 Engineers

4. Working in the Position of DFT Design implantation Engineer for Halo.

The Halo is a 32-bit dual core, ARM Cortex based microcontroller unit (MCU) for
Automotive instrument cluster applications. It includes a CortexM4 core as the
vehicle interface processor and a CortexA5 as an applications processor. Halo
incorporates an I/O processor that integrates a third core, the CortexM0+.
Description
The maximum system frequency shall be 160MHz. The CortexA5 will
operate optionally at 1x or 2x system frequency. The CortexM4 will operate only at
the system frequency. The I/O processor subsystem will operate optionally at 80MHz
or sub-divisions of that frequency.
Role DFT Design Enginner
Operating System(s) Unix,Windows NT
Rabbit Integration tool, Verilog,vi,Mbist architect, Wgl processor, Testkompress,
Skills Lbist architect, Cadence RC,
Synopsys VCS, Mentor tools, perl.
NCSim for Simulations, Mentors Mbist architect for generation, Verilog for RTL,
Environment
VCS for RTL,
DFT implantation work, from designing to implementing the DFT logic. Clocking
Contribution verification, Scan Insertion, ATPG DRC analysis, ATPG pattern generation of
Atspeed.
Period June 2013 to, expectedly April 2014
Team Size 5 Engineers
Projects done at STMicroelectronics Limited

1. AC boundary scan Implementation on Baltar using Synopsys Design Compiler, verification

of its features, pattern simulation, and ATPG activities.

Description Baltar (6 million flops) was Networking ASIC to be delivered to Cisco.

Role DFT design Engineer
Operating System(s) Unix,Windows NT
Skills MS Office,Verilog,vi, tcl, perl.
NCSim for Simulations, Design compiler for DFT insertion, Tetra Max for ATPG
Environment
pattern generation, Verilog for RTL.
AC boundary scan specification study, and implementation. Generation and
Contribution verification of the Vectors for AC boundary scan. ATPG pattern generation and
simulation.
Period June 2014 to November 2014
Team Size 4 Engineers

2. Scan Insertion on EyeQ4 multiple blocks using Synopsys Design Compiler, verification of its
features, and ATPG activities like coverage stabilization etc.

Description EyeQ4 (5 hundred thousand flops) was an Automotive product.

Role DFT design Engineer
Operating System(s) Unix,Windows NT
Skills MS Office,Verilog,vi, tcl, perl.
NCSim for Simulations, Design compiler for DFT insertion, Tetra Max for ATPG
Environment
pattern generation, Verilog for RTL.
Scan Insertion Specification decisions, Scan insertion using Design Compiler. ATPG
Contribution
pattern generation and Coverage analysis.
Period December 2014 to February 2015
Team Size 2 Engineers

3. Scan Insertion, ATPG activities, IP testing activity on L2B

Description L2B is a Set-top box product (2 million flops) designed for low end market like India.
Role DFT design Engineer
Operating System(s) Unix,Windows NT
Skills MS Office,Verilog,vi, tcl, perl.
NCSim for Simulations, Design compiler for DFT insertion, Tetra Max for ATPG
Environment
pattern generation, Verilog for RTL.
Contribution Scan Insertion Specification decisions, Scan insertion using Design Compiler. ATPG
 pattern generation and Coverage analysis. IP testing, including study of IP’s test
specifications, developing patterns, and simulating them.
Period March 2015 to December 2015
Team Size 6 Engineers

4. Pattern Generation, pattern simulation STUCK-AT for Accordo5 Device.

Description Accordo5 (8 hundred thousand flops) is an Automotive product.

Role DFT design Engineer
Operating System(s) Unix,Windows NT
Skills MS Office,Verilog,vi, tcl, perl.
NCSim for Simulations, Prime Time for STA debug, Tetra Max for ATPG pattern
Environment
generation, Verilog for RTL.
ATPG pattern generation and Coverage analysis for transition; Pattern simulation,
Contribution pattern debug; ECO work; pattern delivery to Test Engineering; Silicon bring up;
diagnosis work with TEST engineering.
Period February 2016 to June 2016
Team Size 3 Engineers

5. Pattern generation, pattern simulation TRANSITION for Craton2 device.

Description Craton2 (7 hundred thousand flops) is an Automotive product.

Role DFT design Engineer
Operating System(s) Unix,Windows NT
Skills MS Office,Verilog,vi, tcl, perl.
Tetra Max for ATPG pattern generation, Verilog for RTL, Prime Time for STA
Environment
debug.
ATPG pattern generation and Coverage analysis for stuck-at; Pattern simulation,
Contribution pattern debug; ECO work; pattern delivery to Test Engineering; Silicon bring up;
diagnosis work with TEST engineering.
Period July 2016 to December 2016
Team Size 3 Engineers

6. DFT implementation work for Craton2 (cut2) device.

Description Craton2 (cut2) (7 hundred thousand flops) is an Automotive product.

Role DFT design Engineer
Operating System(s) Unix,Windows NT
Skills MS Office,Verilog,vi, tcl, perl.
Tetra Max for ATPG pattern generation, Verilog for RTL, Prime Time for STA
Environment
debug.
Contribution DFT implementation work for Craton cut2 Device. ATPG pattern generation and
 Coverage analysis for Transition; Pattern simulation, pattern debug; ECO work.
Period July 2016 to December 2016
Team Size Three Engineers

Projects done at Intel Technologies Singapore

1. Integration and verification of the test/Bist aspects of high-speed IO interfaces for gateway
SOCs like Ligthening Mountain.

Description Lightening Mountain is a gateway SOC done by the Smart Home division of Intel.
Role Senior Design Engineer
Operating System(s) Unix,Windows NT
Skills MS Office,Verilog,vi, tcl, perl, VHDL, Simulators from cadence and Synopsys.
Environment NCSim for Simulations, Verilog and VHDL for RTL.
Took care of the Test integration and verification, Self-test and other associated tests,
for various High-speed IO interfaces (10 in total) for the Soc called Lightening
Contribution
Mountain. The IIO interfaces included different flavors of USB, SATA, ethernet,
SerDes, etc. The SOC size is 7 million flops.
Period February 2018 to October 2018
Team Size 6 Engineers

Extra Curricular Activities / Awards

▪ WINNING STARTS HERE award for exemplary contribution to the Rainier and Racerunner chips
in Freescale semiconductors.
▪ Peer appreciation awards.
▪ Organized and participated in many technical and fun activities at workplace.
▪ Won many prizes in debate and seminar participations.
▪ An active participant and organizer in activities related as well as addendum to the work
requirements.

Academic Background:

Qualification Institute Examining Percentage

Authority
B. Tech. National institute of NIT Srinagar (Deemed 9.09 C.G.P.A.
Technology, Srinagar. University) (out 0f 10)

Senior Secondary Govt. Boys Higher J&K Board of 85 %

Examination/XII Class. Secondary, Baramulla. School Education

Higher secondary Gousia Educational J&K Board of 84 %

Examination/X Class Trust, Baramulla. School Education

Personal Details

▪ Date of Birth: 08 June 1986

▪ Nationality:
▪ Permanent Address
▪ Linguistic ability
▪ Hobbies
▪ Highest Qualification
▪ College
▪ Branch Of study
Indian
Housing Colony Sangri,
Baramulla, J&k, 193101.
English (read, speak and write),
Urdu (read, speak and write),
Hindi (speak)
Kashmiri, Arabic (read).
Reading books, listening to music, watching movies.
Bachelor of Technology.
National Institute of Technology, Srinagar.
Electronics and Communication Engineering.