Yee-Wen Leung

YEE-WEN LEUNG
2732 Buck Hill Drive
Plano, TX 75025
SUMMARY:
 Highly motivated senior design engineer with experiences in ASIC/FPGA design.
 Experienced with digital and analog/digital mix-signal SoC integration and verifcation, synthesis,
verification, DFT, ATPG, STA, chip bonding, floorplan, clock tree synthesis, Place and Rout.
 Experienced in microprocessor-based system design. Developed chips and functional blocks
including RTL coding, verification. Developed FPGA systems.
 Experienced in embedded system programming, firmware design and development.

EDUCATION:
The University of Texas at Arlington, Arlington, Texas M.S. in Electrical Engineering
Fung Chia University Taiwan, R.O.C. B.S. in Electrical Engineering

TECHNICAL SKILLS:
Tools Usage:
 Cadence – Xcellum, NCSim, VerilogXL, SOCEncounter, UltraSim, AMS.
 Synopsys - DC, PT, VCS, Fomarity, HSPICE, CustomSim, Discovery AMS, PrimeRail, ICCompiler,
SiliconSmart.
 Others - ModelSim, OVM/UVM, MATLAB, SPICE, FreePCB, EaglePCB, DipTrace, MathCad, Zeni
DM, Oscilloscopes, Logic Analyser, signal generators.
Programming Language:
 Verilog, SystemVerilog, VHDL, C/C++, Assembly, PERL, TCL/TK, FORTRAN, Pascal, Visual Basic.
Architecture:
 I2C/I3C, SPI, P1500, JTAG, MIPI, miniLVDS, ATM, X.25, OSI, TCP/IP, Digital communications,
Digital signal processing.
 I/O interfacing, memory accessing and other relevant hardware design.
 ARM, Z8, 80x86, TMS320 C50, V850E embedded processors system and architecture.

EXPERIENCE:
Texas Instruments, Inc. Dallas, TX Sep 2019 – Aug 2020
Verification Engineer (Contract via Talent 101, Inc.)
 Design verification setup. Functional test case generation.
 Test bench setup and development with SystemVerilog based environment.
 Verification and debug I2C/I3C and SPI communication systems.
 Gate level verification setup and simulation.
 Debug on functional and timing failure.
 RTL development .

BAE Systems Austin, TX May 2019 – Sep 2019

Verification Engineer (Contract via Paradigm-Works)
 Design and verification environment auditing.
 Cross check on design and verification preform for mismatching.
 Design verification based on UVM environment.

Doosan HFC, Carrollton, TX Nov 2017 – Mar 2019

FPGA Design Engineer
 Architecture and RTL development for FPGA designs. Generate timing constraint for FPGA
synthesis and PNR.
 Design verification plan generation and environment setup.

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 Design and development of due FPGA control system.
 System integration and verification for power plant controller.

AMD Austin, TX Sep 2016 – Nov 2017

Senior RTL Design Engineer (Contract via USTech Solution)
 RTL development and debug for ASIC-SOC integration of test chip for new technology development.
 DFT development and insertion.
 Design verification environment setup and test case development.

Solomon-Systech Limited, Hong Kong Apr 2011 – May 2016

Senior Design Engineer
 Chip level ASIC-SOC integration and verification of touch panel controller. Auto P&R and timing
closure on digital section. Logic design from RTL to GDSII for digital controller.
 Chip level verification with function patterns generation and analog/digital mixed signal co-simulation
with OVM/UVM environment. Functional vectors generation for image processing and display.
Tester vectors generation. Firmware design for touch digitizer.
 FPGA design to verify display control logic. Design system and logic for miniLVDS interface circuit
for display system.
 Post silicon verification for touch control chip.
 Custom IC design flow development and maintenance. New libraries characterization.

ASTRI Hong Kong Oct 2008 – Mar 2011

Consultant (Contract)
 Lead technology team for new design memory device design.
 Develope new algorithm and circuit for analog-digital conversion (ADC) with new searching
methodology. Layout prototype board and IC block. Pattern filed for ADC circuit.
 Design memory address circuit by 3-dimension location concept used basic CMOS circuit and demo
the circuit on PCB. Map new memory device input/output signals to the ROM addressing format that
can be used in current market without major change in application system interface.
 Define control interface between memory chip and PC for reading and writing procedure. Define
testing system for memory chip. Finalize memory testing system architecture and communication
protocol.

NEC Electronics America, Inc. Irving, TX Jun 2000 – Apr 2008

Design Engineer
 Custom IC design from RTL to GDSII. Design flow support.
 Develop control program for macro operation in block level to verify detail function of existing macro
based on verification plan. Verify the functionality of automobile control chip by assembly.
 Develop macros including HDL coding, synthesis, simulation, timing-closure, and final verification.
Generate verification plan of new macro design for both macro and top level verifications. Develop
functional verification patterns for new developed macros.

STMicroelectronics, Inc. Carrollton, TX May 1997 – Jun 2000

ASIC Design Engineer
 Physical design for consumer ASIC including bonding, floorplan, Place & Route, back-annotation,
GDSII generation, and post-layout verification.
 Support custom IC design back-end flow and tools. Design and maintain design environment for
ASIC design by update flow and tools.
 Train new engineer for bonding and back-end design flow.

Curtis Mathes Corp. Dallas, TX Dec 1996 – May 1997

Hardware Design Engineer

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 Define guideline for software engineers to develop the translation of displaying web page content on
traditional analog TVs. Define IR code for web TV based on universal remote control code.

Macrochip Research, Inc. Richardson TX Jul 1995 - Jun1996

Associate Systems Engineer
 Develop firmware for real-time embedded system utilizes JTAG/Boundary scan technology.
 Generate control program for data passing between different protocol layers by C and assembly
language.

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