Hassan Ullah Khan

Research Officer (FPGA)

ihassankhattak@gmail.com
+9231359894488
6 Road, Chandani chowk, Rawalpindi Pakistan.
www.linkedin.com/in/hassanullahkhan

CAREER OBJECTIVES
A dedicated and motivated FPGA Engineer, and my aim is to contribute my skills in digital logic design, FPGA-
based systems, and System Verification. I am actively seeking a challenging position as an FPGA hardware
design engineer, where I can apply my expertise and leverage opportunities for continuous learning and
professional growth.

EXPERIENCES
National Aerospace Technology Park (NASTP)
Research Officer FPGA: 1 Dec, 2023 - Present
Responsibility:
o HDL (Hardware description language)/ VHDL on Xilinx Vivado, System Verilog.
o Utilizing LabVIEW FPGA and MATLAB for digital signal processing in the context of aerospace
technology.
o Proficient in Xilinx Vivado for FPGA design and implementation.
o Expertise in PCIe, AXI, DDR protocol for data communication.
o Collaborating with a multidisciplinary team to contribute to cutting-edge research in the field of
aerospace technology.

Re-Engineering with Research (RWR) Pvt Limited

Hardware Design Engineer FPGA 1 Oct, 2023 – 30 Nov 2023.
Responsibility:
o Designing and implementing FPGA solutions utilizing Zynq Ultra Scale SoC and Artix-7 platforms.
o Working extensively with IP cores of Zynq for accelerated development.
o Proficient in JTAG debugging techniques for efficient troubleshooting and optimization.
o Utilizing MATLAB Simulink for modeling and simulation in FPGA projects.
o Implementing Universal Verification Methodology (UVM) for thorough testing and validation of
FPGA designs.
o Leveraging High-Level Synthesis (HLS) tools for efficient FPGA design.
o Expertise in scripting languages such as Tcl and Perl for automation and workflow optimization.

Bestway Cement Limited (BCL)

Instrumentation and Control Engineer 1 Aug, 2022 – 27 April, 2023
Responsibility:
o Expertise in communication protocols including ModBus, TCP/IP industrial communication, and
serial communication.
o Debugging communication problems between field instruments and the control room DCS.
PUBLICATION:
Design of Three Level Neutral Point Clamped Inverter with Fuzzy Logic based MPPT for PV
Applications (Proceedings of the Pakistan Academy of Sciences): A Physical and Computational Sciences
59(3): 69-80 (2022) https://doi.org/10.53560/PPASA(59-3)775

EDUCATION:
BE: Electronics Engineering
University of Engineering & Technology Peshawar Electronic Engineering (November 2020)
CGPA: 3.41/4.00

TECHNICAL AND SOFT SKILLS:

Software tools: Xilinx vivado, Matlab/Simulink, LabVIEW, Keil uVision, Cadence Virtuoso (Basic). Quartus
Prime, ModelSim, EasyEDA, Eagle, Altium Designer.
Programming: Verilog(HDL), VHDL, System Verilog, UVM, Tcl Perl, C/C++, Embedded C, Python, Matlab
coding,
Microcontroller: ESP32, STM32, 8085, Arduino, AVR, PICs.
Protocols: UART, SPI, I2C, I2S, I3C, PCle, DDR, AXI.
Others: Digital and Analogue Electronics, Control system, VLSI, digital Signal Processing.

PROJECTs:
1. UART, SPI, I2C Implementation on Verilog with Artix-7 Spartan 3E Board:
- Developed Verilog code to implement UART, SPI, and I2C communication protocols on an Artix-7 Spartan 3E FPGA
- Demonstrated effective communication between the FPGA board and external devices using these protocols.
2. Pipline core and Signal Cycle RISC – V Implementation on Verilog:
- Implemented a Signal Cycle RISC-V processor using Verilog HDL.
- Executed and verified various instructions, showcasing proficiency in processor design.
3. Digital Filter IIR and FIR Implementation on Verilog (Spartan 3E board):
- Developed Verilog code to implement both IIR and FIR digital filters.
- Executed simulations and successfully implemented the filters on a Spartan 3E FPGA board.
4. VLSI Project: RF-based WIRELESS Data Transmission between Two FPGAs using SPI and NRF24L01:
- Implemented a VLSI project involving RF-based wireless data transmission between two FPGAs.
- Developed Verilog code for seamless communication using SPI and NRF24L01 modules.
- Successfully demonstrated wireless data transfer, highlighting skills in VLSI design and communication protocols.
5. Accurate Delay Generation using Verilog (Stopwatch Implementation on Spartan 3 FPGA):
- Implemented an accurate delay generator using Verilog for a stopwatch application on a Spartan 3 FPGA.
- Demonstrated precise timing control and FPGA-based delay functionality.
6. VLSI Project: ADC (Analog to Digital Converter) & SENSOR Interfacing with FPGA using SPI:
- Designed and implemented an Analog to Digital Converter (ADC) interfaced with an FPGA using the SPI protocol.
- Successfully integrated sensor data acquisition, showcasing expertise in FPGA-based sensor interfacing.
7. Design of 32-bit Microprocessor using Verilog HDL:
- Developed a 32-bit microprocessor architecture using Verilog HDL.
- Demonstrated proficiency in microprocessor design and system integration.
8. Designing Four Hundred Deep FIFO with Verilog HDL:
- Implemented a deep FIFO (First-In-First-Out) memory using Verilog HDL.
- Successfully simulated and verified the functionality of the FIFO.
9. DAC (Digital to Analog Converter) Interfacing with FPGA using SPI, Spartan 3:
- Designed and implemented the interfacing of a Digital to Analog Converter (DAC) with an FPGA using the SPI
protocol on a Spartan 3 FPGA. - Achieved successful data conversion and integration.