Objective

To gain hands-on experience as a hardware design engineer intern, utilize my skills in

digital and analog circuit design, FPGA programming, and PCB layout, while learning
from experienced professionals and contributing to the success of the team.

Education
January Student at Posts and Telecommunications Institute of Technology
2023-Present - Ho Chi Minh City
Major: Electronics and Telecommunication Engineering
GPA: 6.48
DANG DUC TIEN
3rd-year student Course Project
g June 05 2002 Application of object detection algorithm on SOC-FPGA using
Mar
Tang Nhon Phu A Ward, Thu Duc City, 2023-Present OPENCL
Knowlegde: CNN, Tiny YOLO, OpenCL, SOC-FPGA.
Ho Chi Minh City. Responsibility:
- Research OpenCL and Tiny YOLO.
Ó 037 7766861
Πwww.linkedin.com/in/tiennn0506/ May-Jun 2023 Verification-of-FIFO-using-SystemVerilog
tiendang0605@gmail.com Knowlegde: System Verilog, Verilog, Digital Design.
Tool: Xilinx Vivado.
Responsibility:
Languages - Build a testbench environment to verify the FIFO.
- Code testbench component and debug: generator, driver,...
Results:
English ○ ○
- The testbench works well when running simulations on Vivado.
· TOEIC 575 point 2022
Apr-May 2023 Implementation of high speed of D FLIP-FLOP
Qualifications Knowlegde: Digital Design, transistor MOSFET(nMOS and pMOS)
Tool: Synopsys Custom Designer.
Responsibility:
Certificate of Cloud Architecture by - Analysis of characteristics of nMOS and pMOS.
·
AWS Academy - Draw the D FLip-Flop schematic.
Results:
Hard Skills - The maximum frequency the D Flip-Flop can operate at is 10GHz.

FPGA Implementation of CORDIC Algorithms for Sine and

Programming language: C/C++, Sep-Dec 2022
· Cosine Floating-Point Calculations
Python Knowlegde: Cordic algorithm, Verilog language, Digital Design
· RTL: Verilog, System Verilog Tool: Intel Quartus, Intel ModelSim-Altera.
Responsibility:
IDE: Visual Studio Code, Code
· - The team leader of 3 people.
Block, Sublime Text
- Research about the Cordic algorithm.
EDA tool: Intel Quartus, Synopsys - Plan the general architecture idea of the design.
· Hspice, Synopsys Custom Designer, - Code module and debug.
Xilinx Vivado Results:
· OS: Window, Linux - The sine and cosine results achieve accuracy up to 6 decimal places.
Microsoft tool: Word, PowerPoint, - The maximum frequency the circuit can operate at is 50MHz.
·
Excel - The fastest calculation speed is 0.56 µs.

Soft Skills Nov 2022 A simple processor design

Knowlegde: Digital Design, computer architecture, Verilog language,
· Adapt quickly into new environment assembly languages.
Tool: Intel Quartus,Intel ModelSim-Altera.
· Hard working Resposibility:
· Team-working - Design a simple processor consisting of two blocks, Controller and
Datapath, to implement some instructions: sw, lw, add,...
· Good at self-study and research
results.
· Friendly Results:
- The design works well when running simulations on Quartus and
when verifying on the DE2 kit.