Incentia Test Synthesis Solution

TestCraft

Incentia Design Systems, Inc.

October, 2010

incentia 1
 Company Introduction

Mission: SoC nanometer timing and synthesis technology leader

Channels

Direct Offices: Distributors:

USA: Silicon Valley Japan (Marubeni), India (ICON),
Southern California China (OnePass Solutions),
Taiwan: Hsinchu Korea (ED&C), Israel (AST)

incentia Confidential 2
 Incentia Product Offering

Logic, Low Power, DFT Synthesis solution
DesignCraft, PowerCraft, TestCraft

Timing analysis solution

TimeCraft: World fastest Static Timing Analyzer (STA)
TimeCraft-LOCV: Location Based OCV
TimeCraft-SSTA: Statistical STA
TimeCraft-SI: Signal Integrity
TimeCrfaft-PCA: Power Analysis
ConstraintCraft: Constraint Management

Design closure solution

ECOCraft-Timing: Hold-time & Setup-time ECO
ECOCraft-Power: Leakage power ECO

incentia Confidential 3
 How Incentia Products Fit into Design Flow
IC Design Flow Incentia Products
RTL

Logic Synthesis DesignCraft

(Logic, DFT, Low Power Synthesis)
Netlist
Placement & Route
Netlist, DEF/GDSII Complete Timing Analysis
RC Extraction - TimeCraft (Static Timing Analysis)
Netlist, SPEF - TimeCraft–LOCV (90, 65, 45 nm)
Delay Calculation - TimeCraft–SSTA (45, 30nm)
Timing, Power - TimeCraft–SI (Signal Integrity Analysis)
Analysis - TimeCraft-PCA (Power Analysis)
- ConstraintCraft (Constraint Mgmt, Validation)
Yes
Meet Constraints? OK
No
Hold-Time, Power
Design Closure
ECO - ECOCraft-Timing (Hold-time & Setup=time ECO)
- ECOCraft-Power (Leakage Power ECO)

incentia Confidential 4
 TestCraft Key Features

One pass logic and DFT synthesis

Top-down or bottom-up design methodology

Scan cell replacement

DFT rule checking

Automatic fixing of DFT rule violations

Scan chain ordering, stitching, balancing

Smooth integration to Incentia low power solution

Smooth interface to 3rd-party ATPG tools: STIL format
Mentor (FastScan), Synopsys (TetraMax), SynTest
(TurboScan)

Shorter downstream ATPG runtime
More DFT violations can be fixed during DFT synthesis

incentia Confidential 5
 Typical DFT Flow (RTL or Netlist Input)
compile_lib, read_design, link_design
Import Data (Design, Library) make_unique, set target_lib

Load SDC constraints

Set Design Constraints
Define Scan Chain Architecture
set_scan_implementation
set_dft_rule_option
set_scan_port, set_scan_route
set_scan_cell_connect_style

Analyze Design for DFT check_design

check_dft_rule
No
Result OK?
Yes
Perform Scan Optimization optimize –scan (for RTL input)

set_scan_implementation -stitch false

Pre-show Scan Chains implement_scan
pre_show_dft

Stitch Scan Chains set_scan_implementation -stitch true

Report Scan Info implement_scan
report_dft
No
Result OK?
Yes write_design
Generate Outputs write_dft_interface

incentia Confidential 6
 Fastest Runtime: STA-based Technology

Fastest run time: up to 10X faster than any other solutions!

Key technology: STA based static analysis
(vs. event driven approach used in other tools)
Bigger designs show bigger speedup

top_design

DFT
dft_tm test_mode_port
PA2
PA3 test_gen
PA4 scan_enable_port
dft_se
clock_port
CLK
PA5 clk_gen
PA6 create_dft_clock
create_clock

incentia Confidential 7
 Efficient Scan Cell Replacement

Scan cell replacement

Preserve timing quality of pre-DFT design
SDFFX2
scan_in
1 q / scan_out
d
DFFX6 0
scan_enable
d q
 clk

clk SDFFX6

 scan_in
d
1 q / scan_out
0
scan_enable
clk

incentia Confidential 8
 Scan Chain Planning

Rich controls in scan chain ordering & stitching

Number of scan chains
Chain length
Balanced chaining
Chaining styles
• Chain with distinctive clock domain: (R1), (R2), (R3)
• Chain with merged clocks: (R1, R2, R3)
• Chain with merged edges: (R1), (R2, R3)
• Chain with merged clocks but not edges: (R1, R2), (R3)
R1 R2 R3
clk1 clk2 clk2

Lock-up latch insertion to avoid timing issues

• Automatic & user-control
incentia Confidential 9
 Scan Chaining: Example

dft_si1
si so si so si so
d d d dft_so1
dff1 dff2 dff1
clk1 clk1 clk1

dft_si2 Inst1 Inst2
Chain by distinctive

dft_so2
clock domain
dft_si3
si so si so
d d
dff1 dff2
clk2 clk2 dft_so3

Top Inst3
Inserted lock-up latch

dft_si si so si so si so si so
d d d
dff1 dff2 dff1 lat
clk1 clk1 clk1 clk1

Inst1 Inst2

Chain by merged clocks si so si so

dft_so

d d
dff1 dff2
clk2 clk2

Top Inst3

incentia Confidential 10
 Clock Tree Based Scan Chaining

Clock tree based scan ordering and chaining

Clock tree grouping and ordering
Example: buf1 group first, following by buf2, and buf3 groups

dft_si si so si so si so si so dft_so dft_si

si so si so si so si so
d d d d d d
dff1 dff2 dff1 dff2 dff1 dff2 dff1 dff2

Inst1 Inst2 Inst1 Inst2

buf1 buf1
dft_so
si so si so si so si so
CLK buf2 d d buf2 d d
dff1 dff2 CLK dff1 dff2
buf3
buf3 Inst3 Inst3
Top Top

One possible result if clock tree Clock tree information is given { buf1/o,
information is not considered buf2/o, buf3/o} to guide scan chaining

incentia Confidential 11
 Scan Chain Re-chaining

Scan chain re-chained

Re-balance scan chains on existing scan chains
Scan Section
dft_si1
si so si so
sdff sdff

dft_si2 dft_so1
si so si so
sdff sdff
dft_so2

Scan Section
dft_so1
dft_si1
si so si so
sdff sdff

dft_si2 dft_so2
si so si so
sdff sdff

incentia Confidential 12
 DFT Rule Checking & Fixing

DFT rule violations will cause

Shorter or incorrect scan chains
Lower fault coverage or failure in later ATPG

Checking of over 25 rule violations

Clock, latch, asynchronous signals, gated clock,
tri-state bus, bi-direction port, etc.

Automatic fixing of over 15 rule violations
MUX-style, disable-style

Fastest runtime for checking & fixing

Unique patented STA-bases approach

incentia Confidential 13
 Automatic Fixing of DFT Rule Violations

DFT Violation Fixing (MUX-Style)

Uncontrollable, Gated, Generated Clock Violation Fixing
Uncontrollable Asynchronous Set/Reset Violation Fixing

dft_fix_async 1
1’b0 1’b0 0

d q
d q
si

clk dft_fix_clk 1
clk 0
en
en
dft_tm

incentia Confidential 14
 Automatic Fixing of DFT Rule Violations (Cont)

DFT Violation Fixing (Disable-Style)

Uncontrollable, Gated, Generated Clock Violation Fixing
Uncontrollable Asynchronous Set/Reset Violation Fixing

1’b0 dft_tm
1’b0

d q d q
si
clk dft_tm
en
en clk

incentia Confidential 15
 Automatic Fixing of DFT Rule Violations (Cont)

Same Clock Source Fixing

This fixing can help to reduce buffer insertion by clock tree
synthesis.

clk
clk
en 0 0
en
1 1
dft_fix_clk

Default Fixing CTS Specific Fixing

incentia Confidential 16
 Automatic Fixing of DFT Rule Violations (Cont)

Cross Hierarchy Fixing

Reduce the logic count, thus reduce area

FIX VIOLATION VIOLATION

FIX

FIX VIOLATION VIOLATION

incentia Confidential 17
 Testability Estimation

Testability estimator before ATPG CONTROLLABILITY

Test Point Insertion & Testability Report Level of Terminal Pin

Net
Logics (Starting pt)
Insert test point to hard observe or
control point 5 N340 reg2/SO
4 N23 reg1/SO
Report hard to observe or control
point 2 N3 Top_in1

HARD TO
OBSERVE/CONTROL OBSERVABILITY
LOGICS
Level of Terminal Pin
Net
Logics (Ending pt)
CONTROL OBSERVE
7 N55 reg7/D
4 N402 reg6/CK
1 N2 Top_out6

incentia Confidential 18
 Test Point Insertion

Insert test points at hard to control or observe locations

Input
0 Output
ctrl Main Function
Inserting control test point d q 1 Block
=> A Reg & a MUX are added 1’b0 (so)

dft_tm
dft_fix_clock

Inserting observe test point Input Output

Main Function
=> A MUX is added Block obs
d q

si

dft_fix_clock

incentia Confidential 19
 Observation Test Point Compression

Compress multiple observation test points into one test

point logic to reduce the logic
Can control # of compressed points
Example: compress obs1, obs2, obs3 into 1 test point logic

Scan Chain scan_enable

obs3

obs2 D Q
TD
obs1

>CK
test_mode
obsreg
test_clk

Output
Observability Logic
Function Block

incentia Confidential 20
 Sharing Control & Observe Test Point

Control & observe logic at the same point can be shared

Example: NET1 is hard to control & observe

Input Function Block NET1 NET1

0 Output
A obs ctrl Function Block
d q d q 1 B
1’b0 (so)
si
dft_tm
dft_fix_clock dft_fix_clock

NET1
Input 0 Output
Function Block ctrl Function Block
A d q 1 B
(so)

dft_tm
dft_fix_clock

incentia Confidential 21
 Bypass Logic

Adding bypass logic for memory blocks or black boxes

Insert observable and/or controllable logics to increase
testability

Din_1 Dout_1
0
. .
For Observability
. . y
Din_n Dout_n 1 x
D Q
READ
SI
test_mode
SE SO WRITE
CLK D Q
1’b0 SI
SFF_OBS
SE SO
For Controllability
SFF_CTRL

incentia Confidential 22
 Seamless DFT and Low Power Integration

Smooth DFT & low power integration

Automatic DFT insertion for clock gating in Incentia environment

obs3 Observability Logic

obs2 D Q

obs1 obsreg
>CK

test_mode
select D Q
gated_clk
latch

EN
top_clk Clock Gating Logic

incentia Confidential 23
 Multiple Supply Voltages

DFT for multiple supply voltages

Automatic level shifter insertion when chaining registers from
different voltage domains
Scan chain order by voltages

1.0v

si so
Auto Level Auto Level
Shifter insertion Shifter insertion

…
…

1.2v
0.8v
scan_in scan_out
si so si so

incentia Confidential 24
 Enhancement for Low Power

CPF interface support

Auto library reading and target library link when
sourcing CPF script

Control of scan-chain crossing voltage domain

Level-shifter Insertion control of scan-chain crossing
voltage domain.

Level shifter covering IO port and special voltage
domain through IO of certain IP

Support multi-bit scan cell to further reduce
area/power

incentia Confidential 25
 TestCraft Runtime Data

Perform DFT rule checking, fixing, chaining, and reporting

Runs 2x to 8x faster than others

Design1 1.4M logic instances, 90nm

Design2 2.8M logic instances; 90nm
Design3 5.4M logic instances; 65nm
Design4 6.2M logic instances; 65nm

Runtime speedup ratio

8
7
6
5
4 TestCraft
3 Competitor
2
1
0
Design1 Design2 Design3 Design4
incentia Confidential 26
 Summary

Complete integrated synthesis solution
Logic, Low Power, DFT

Very fast runtime with big capacity
2X to 5X faster than other solutions!

Most aggressive reduction in chip area and power consumption
Up to 30% less synthesized gate counts
Up to 20% less power

Many customer tape-outs in different applications

Communication, networking, wireless, consumer electronics,
multi-media, graphics
Easy to adopt

incentia Confidential 27