CE-210 Digital Systems I

Assignment # 9 – Chapter 9 - Solution

1- The following waveforms are applied to the two mode-select inputs (S1 & S0) of a 74x194 chip, a
universal shift register. Assume that “A B C D”, LIN and RIN are tied to “1100”, 1 and 0,
respectively. For each clock edge in this timing diagram write the operation mode of the 74x194 in
the last row of the diagram. Also obtain the 4-bit output, QA, QB, QC and QD, after each clock edge
and write it right after the corresponding edge in the diagram.

Clk

S1

S0

QD QC QB QA 1100 1001 0100 0001 0011 1111 0110 0001

1100 1001 0010 0001 0111 1100 0011 0000
QA: MSB

Operation LD LD SL NC SR SR SR NC SL SL SL LD SR SR SR SR SR
Mode
RIN = 0 LIN = 1
Legend: LD: Load, SR: Shift Right, SL: Shift Left, NC: No change QA QB QC QD

2- Use a 74x194 chip to design a 4-bit Johnson counter, and then draw a timing diagram for this
counter. Tie the CLR input to logic 1 permanently.

0
74x194
Clk
Clock
Clk
Reset
1 CLR
Reset S1 QA
QD
1 S0
QC QB
X LIN
QB
0 D QC
QA
0 C
QD
0 B
0 A
RIN The same circuit used for a ring counter, but now QD is inverted before it is
fed back to the shift register.
3- Use a 74x194 chip to design a 4-bit ring counter, and then draw a timing diagram for this counter.
Do not use LIN.

74x194

Clk
Clk
1 CLR
Load S1 Load
QD
1 S0
QC QA
X LIN
QB
0 D QB
QA
0 C
QC
0 B
1 A QD
RIN

4- Use a 74x163 chip to design a counter with the following counting sequence:
0, 1, 2, 5, 6, 7, 8, 10, 11, 12, 13, 14, 15, 0, 1, 2, 5 ...

QD: MSB
There are 2 jumps in this counting
sequence: 2 to 5 and 8 to ten. 74x163
Clock
Clk
1 Decodes 2
CLR
LE QA
1 ENP QB
1 ENT QC
1
0 QD
1 0 A
0 B
0 C
1 1 D
0
1
Decodes 8

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 5- What digital component is implemented in the following VHDL code?

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY test3 IS
PORT (D, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC ) ;
END test3 ;

ARCHITECTURE Behavior OF test3 IS

BEGIN

PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ;
Q <= D ;
END PROCESS ;

END Behavior ;

Answer: This is a D flipflop using a WAIT UNTIL statement

6- Complete the following VHDL code to implement a 2-to-4 decoder with an enable input.
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY dec2to4 IS
PORT (w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
En : IN STD_LOGIC ;
y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;
END dec2to4 ;
ARCHITECTURE Behavior OF dec2to4 IS
SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;
BEGIN
Enw <= En & w ;
WITH Enw SELECT
y <= "1000" WHEN "100",
"0100" WHEN "101",
"0010" WHEN "110",
"0001" WHEN "111",
"0000" WHEN OTHERS ;
END Behavior ;

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