CE-210 Digital Systems I

Assignment # 8 – Ch 8 - Solution
Summer – 2016

1- A synchronous bit-serial input stream is received on a single line, A. Develop a (Mealy) state diagram
with one output, Z, such that Z goes up only with the third ‘0’ of any three consecutive ‘0’s on A;
otherwise, Z must be low. Sequences may overlap. An input bit pattern on A and the corresponding
output bit pattern on Z are shown below as an example:

A: 10000000100000
Z: 00011111000111

A/Z 1/0
External
Reset
r
0/0

1/0
a

1/0
0/0
b
0/1

2- The Moore machine: A synchronous bit-serial input stream is received on a single line, A. Develop a
(Moore) state diagram with one output, Z, such that Z goes up for one cycle, only (immediately) after
the fourth ‘0’ of any four consecutive ‘0’s on A has been sampled. Sequences may overlap.
1
S/Z External
X Reset
0 r,0
1

1 1
a,0 d,1
0
1
0
b,0 c,0
0
0
3- Realize the transition diagram shown below with D-FFs.

X/Z 0/0 00
0/1
1/1
1/1
01 11

0/0 , 1/1 0/1

10 1/1

Transition Table Partial Transition Tables Output Map

X X X X
0 1 0 1 0 1 0 1
Q1Q0 Q1 Q0 Q1Q0
00 01, 0 11, 1 0 0 1 0 1 1 00 0 1

01 10, 0 10, 1 0 1 1 1 0 0 01 0 1

11 00, 1 11, 1 1 0 1 1 0 1 11 1 1

10 01, 1 11, 1 1 0 1 0 1 1 10 1 1

Q1n+1 Q0n+1, Z Q1n+1 Q0n+1 Z

Z =X + Q1

The above steps are the same for all types of FFs

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 Use D-FFs
Excitation Maps

X X
0 1 0 1
Q1Q0 Q1Q0
00 0 1 00 1 1
01 1 1 01 0 0
11 0 1 11 0 1
10 0 1 10 1 1

D1 D0

D1= X + Q1’Q0 D0 = Q0’ + XQ1

Logic Circuits

Q0 D1 X D0
Q1’ Q1
X Q0’

Q1 Z

4- Realize the transition diagram of the previous problem with T-FFs.

Partial transition tables were obtained above.

Excitation Maps
X X
0 1 0 1
Q1Q0 Q1Q0
00 0 1 00 1 1

01 1 1 01 1 1

11 1 0 11 1 0

10 1 0 10 1 1

T1 T0

T1= (X +Q1 + Q) . (X’ + Q1’) T0 = X’ + Q1’ + Q0’

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 Logic Circuits
X
Q1
Q0 T1 Q0’
T0
Q1’
X’
X’
Q1’

Q1
Z

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