Lecture 9: Registers

 Basic registers (parallel in/ parallel out)

 The illustration of shift function
 Shift left registers
 Shift right registers
 Bidirectional universal shift registers
 (parallel in/ parallel out)

Basic registers 0 0

Data storage is a basic function of registers

(Introduced in lecture 7 )
1 1
Timing diagram
D0 0 0
D1 1 0
D2 1 0
D3 0 0 1 1
CLR
CLK
Q0 0 0
Usually, add a
Q1 0 1 0 0
enable input to
Q2 0 1
control its CLK
Q3 0 0
operation EN

Clear Storage
1
 The illustration of shift function
 Serial in/serial out (Four bits are used for illustration)
There are two shift directions that they are called “left” and “right”.
Shift left Shift right
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0

Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3

QA QB QC QD QA QB QC QD

Shifted from right to left Shifted from left to right

 The illustration of shift function
 Serial in/serial out (Four bits are used for illustration)
If the diagram like these styles, what shift directions are they?

Notice:
In practical circuit, according to the definition of
manufacturer
QA QA
For example QB QB
In the MSI shift register 74HC194, the shift left QC QC
means that the data is shifted from QD to QA; the QD QD
shift right means that the data is shifted from QA to
QD.
 The illustration of shift function
 Parallel in/serial out  Serial in/parallel out
The movement direction can
be reversed

 Rotate left  Rotate right

Shift right registers
Enter four bits 1011 into the register then follow 0s. Notice that the rightest bit is
first entered. Assuming the register is initially reset.
1
0 Q0 0
1 Q1 0
1 Q2 0
1 Q3 0
1
Serial data D0 D1 D2 D3 Serial data
input C C C C output
DSL

Clock
CLK
FF0 FF1 FF2 FF3 Q0Q1Q2Q3
pulse
0 0 0 0 0
CLK 1 2 3 4 5 6 7 8 1 1 0 0 0
DSL 2 1 1 0 0
Q3 3 0 1 1 0
4 1 0 1 1
Q2
5 0 1 0 1
Q1 6 0 0 1 0
Q0 7 0 0 0 1
8 0 0 0 0
 Shift left registers
Enter four bits 1011 into the register then follow 0s. Notice that the most left bit is
first entered. Assuming the register is initially reset.
Serial data 01 Serial data
output 1 0
Q0 0 Q1 0 Q2 0 Q3 0 input
D0
1 D1
1 D2
1 D3
1
DSL
C C C C

Clock
FF0 FF1 FF2 FF3 Q0Q1Q2Q3
CLK pulse
0 0 0 0 0
CLK 1 2 3 4 5 6 7 8 1 0 0 0 1
DSL 2 0 0 1 0
Q3 3 0 1 0 1
4 1 0 1 1
Q2
5 0 1 1 0
Q1 6 1 1 0 0
Q0 7 1 0 0 0
8 0 0 0 0
Bidirectional universal shift registers
Serial output for Serial output
shift-left for shift-right
 Bidirectional universal shift registers
 Parallel load
When S1S0 = 11
Clear = 1
MUX selects input 3
D inputs of flip-flops
equal to the parallel
inputs
QD  DD 1
QC  DC 1

QB  DB
Q A  DA
 Bidirectional universal shift registers
 Shift left
When S1S0 = 10
Clear = 1
MUX selects input 2
D input of each flip-
flop equals to the
output of the right
adjacent flip-flop
1
The D input of the
0
most right flip-flop
equals to serial shift
left input
QD  DSL QB  QC
QC  QD QA  QB
 Bidirectional universal shift registers
 Shift right
When S1S0 = 01
Clear = 1
MUX selects input 1
D input of each flip-
flop equals to the
output of the left
adjacent flip-flop
0
The D input of the
1
most left flip-flop
equals to serial shift
right input
QA  DSR QC  QB
QB  QA QD  QC
 Bidirectional universal shift registers
 Inhibit (no change)
When S1S0 = 00
Clear = 1
MUX selects input 0
D input of each flip-
flop equals to its output

QA  QA
0
QB  QB
0
QC  QC
QD  QD
 Bidirectional universal shift registers
 Clear
When Clear = 0

All flip-flops reset

0
asynchronously.
QD  0
QC  0
QB  0
QA  0
 Bidirectional universal shift registers
 Function table
The function table
Clear CLK S1S0 QAQBQCQD Function

0   0000 Clear
1 ↑ 11 DADBDCDD Parallel load
1 ↑ 10 QBQCQDDSL Shift left
1 ↑ 01 DSRQAQBQC Shift right
1 ↑ 00 QAQBQCQD No change

Logic symbol
An MSI universal shift QA QB QC QD
CLR QA QB QC QD CLR
S1 DSR register is 74HC194 S1 DSR
SRG 4 74HC194
S0 C DSL S0 C DSL
DA DB DC DD DA DB DC DD
 Bidirectional universal shift registers
 Example
CLR QA QB QC QD
A bidirectional universal shift register and DSR
1 S1 SRG 4
input waveforms are shown in figure, DSL
0 S0
C
determine the waveforms of DSL, QA, QB, DA DB DC DD

QC, QD. CLK

Clock pulse QAQBQCQD

CLR 0 0 0 0 0
1 0 0 0 1
CLK 1 2 3 4 5 6 7 8 9 2 0 0 1 1
3 0 1 1 1
DSL 4 1 1 1 1
5 1 1 1 0
QD 6 1 1 0 0
7 1 0 0 0
QC 8 0 0 0 0
QB It is a Johson counter.
QA The 4-bit sequence has a
total of 8 states.
 Serial-to-parallel data converter
Clear
CLK 0 1 2 3 4 5 6 7 8 9

LOAD
S1, S0
161 state xxxx 1111 0000 0001 0010 0011 0000 0001 0010 0011 0000 (Parallel data output)
194(1) 0000 0000 shift1 shift2 shift3 shift4 shift1 shift2 shift3 shift4 shift1
194(2) 0000 hold hold CLR QA QB QC QD
load load
S1 DSR
74HC194(2)
S0 C DSL
DA DB DC DD

1 CLR Q3 Q2 Q1 Q0
CLR QA QB QC QD
ENP
74HC161 RCO 1 S1 DSR
ENT 74HC194(1)
Clear LOAD C 0 S0 C DSL
D3 D2 D1 D0 DA DB DC DD

0 0 0 0
CLK
(Serial data input) D