TON DUC THANG UNIVERSITY

FACULTY OF ELECTRICAL AND ELECTRONICS

ENGINEERING

402061
DIGITAL SYSTEM DESIGN 1
CHAPTER 9: SHIFT REGISTERS

Thien T. Huynh, PhD.

2/15/2024 402061 – Chapter 9: Shift Registers 1
 CHAPTER 9: SHIFT REGISTERS

9.1 Shift register operations

9.2 Types of shift register data I/O
9.3 Bidirectional shift registers
9.4 Shift register counters
9.5 Shift register applications

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 OBJECTIVES

IN THIS CHAPTER WE WILL LEARN

 Identify the basic forms of data movement in shift
registers
 Explain how serial in/serial out, serial in/ parallel
out, parallel in/serial out, and parallel in/parallel
out shift registers operate
 Describe how a bidirectional shift register operates
 Determine the sequence of a Johnson counter

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 OBJECTIVES

 Set up a ring counter to produce a specified

sequence
 Construct a ring counter from a shift register
 Use a shift register as a time-delay device
 Use a shift register to implement a serial-to-
parallel data converter
 Implement a basic shift-register-controlled
keyboard encoder

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 CHAPTER 9: SHIFT REGISTERS

9.1 Shift register operations

9.2 Types of shift register data I/O
9.3 Bidirectional shift registers
9.4 Shift register counters
9.5 Shift register applications

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 BASIC SHIFT REGISTER OPERATION

 A shift register is an arrangement of flip-

flops with important applications in storage
and movement of data

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 CHAPTER 9: SHIFT REGISTERS

9.1 Shift register operations

9.2 Types of shift register data I/O
9.3 Bidirectional shift registers
9.4 Shift register counters
9.5 Shift register applications

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 SERIAL IN/SERIAL OUT SHIFT
REGISTER

1 1 1 1 1

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 SERIAL IN/PARALLEL OUT SHIFT
REGISTER

 For example, assume the binary number

1011 is loaded sequentially, one bit at each
clock pulse.
After 4 clock pulses, the data is available at the
parallel output.

FF0 FF1 FF2

FF2 FF3
FF3
Serial
Serial 1
X
0 1
0 0
11 10 11
data
data D00
D Q00
Q D11
D Q11
Q D22
D Q22
Q D33
D Q33
Q
input
input
C
C C
C C
C C
C

CLK
CLK
CLK

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 SERIAL IN/PARALLEL OUT SHIFT
REGISTER

 The 74HC164A is a CMOS 8-bit serial

in/parallel out shift register. VCC can be from
+2.0 V to +6.0 V.
(9)
CLR
(8)
CLK
(1)
Serial A
R R R R R R R R
inputs B (2)
C C C C C C C C

S S S S S S S S

(3) (4) (5) (6) (10) (11) (12) (13)

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

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 PARALLEL IN/SERIAL OUT SHIFT
REGISTER

2/15/2024 402061 – Chapter 9: Shift Registers 11

 PARALLEL IN/SERIAL OUT SHIFT
REGISTER

 The 74HC165 is a CMOS 8-bit parallel

in/serial out shift register.

D0 D1 D2 D3 D4 D5 D6 D7
(11) (12) (13) (14) (3) (4) (5) (6)
(1) (9) Q7
SH/LD SRG 8
(10)
SER
(15)
CLK INH (2) (7)
CLK C Q7

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 CHAPTER 9: SHIFT REGISTERS

9.1 Shift register operations

9.2 Types of shift register data I/O
9.3 Bidirectional shift registers
9.4 Shift register counters
9.5 Shift register applications

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 BIDIRECTIONAL SHIFT REGISTERS

 A bidirectional shift register is one in which

the data can be shifted either left or right.

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 CHAPTER 9: SHIFT REGISTERS

9.1 Shift register operations

9.2 Types of shift register data I/O
9.3 Bidirectional shift registers
9.4 Shift register counters
9.5 Shift register applications

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 SHIFT REGISTER COUNTER

 Johnson counter

2/15/2024 402061 – Chapter 9: Shift Registers 16

 SHIFT REGISTER COUNTER

 Johnson counter

FF0 FF1 FF2 FF3

Q3
J0 Q0 J1 Q1 J2 Q2 J3 Q3

C C C C

Q3
K0 Q0 K1 Q1 K2 Q2 K3 Q3

CLK

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 SHIFT REGISTER COUNTER

 Johnson counter
 Redrawing the same Johnson counter (without
the clock shown) FF0

J0 Q0

“twist” K0
C

Q0

Q3
Q3
Q3

Q3

K1

J1
C
FF3

FF1
C

Q1

Q1
J3

K3

Q2 K2

Q2 2 J

2 FF

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 SHIFT REGISTER COUNTER

 Ring counter

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 SHIFT REGISTER COUNTER

 Ring counter
 Redrawing the Ring counter (without the clock
shown) shows why it is a “ring”.
FF0

J0 Q0

Q3 K0 Q0
Q3
Q3

Q3

K1

J1
C
FF3

FF1
C

Q1

Q1
J3

K3

Q2 K2

Q2 2 J

2 FF

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 CHAPTER 9: SHIFT REGISTERS

9.1 Shift register operations

9.2 Types of shift register data I/O
9.3 Bidirectional shift registers
9.4 Shift register counters
9.5 Shift register applications

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 APPLICATIONS

 Shift registers can be used to delay a digital signal

by a predetermined amount.
 Example: An 8-bit serial in/serial out shift register
has a 40 MHz clock. What is the total delay
through the register?
A SRG 8 Q7
Data in Data out
B
Q7
The delay for each clock CLK
40 MHz
C

is 1/40 MHz = 25 ns 25 ns
CLK
The total delay is 8
Data in
x 25 ns = 200 ns
Data out
td = 200 ns

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 APPLICATIONS

 Universal Asynchronous Receiver

Transmitter (UART)

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 APPLICATIONS

 Simplified logic diagram of a serial-to-

parallel converter

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