Combination Logic Circuit

Sequential Logic Circuit

- Changes state depending upon the actual
signals being applied to the inputs at the time
- Have some form of inherent “memory” built
into them
- Able to take into account the:
o Previous input state
o Current input state
o Previous output state
- Generally termed as the two-state or bistable
devices, which can have their outputs in two
state 0 or 1
Latches – level triggered
Flipflops – edge-triggered

Classification
 1. Event-driven
- A synchronous circuit that changes stakes
immediately when enabled

2. Clock-driven
- Synchronous circuits that are synchronized by
a specific clock signal

3. Pulse-driven
- Combination of the first two which responds
to triggering pulses – switch or a clock

 A sequential logic circuit occurs when a

fraction of the output is fedback to the input
Bistable Element – designed using 2 inverters
The metastable condition of the states in
transition

- Latches - are made of gates

- Flipflops – “
 Timing Diagram
- Illustrate the logical behaviour of signals in
digital circuit as a function of time (t0, t1, …)
- Explains the timing relationships among
signals win a system and define the timing
requirements of external signals applied to
the system.
- Ex. Clock and/or enable switch
o Clock
 Constant interval/tick
 Level (ON-1, OFF – 0)
 Edge
o Falling(1 going to 0) – negative
going transition
o Rising(0 going to 1) – positive
going transition
o Switch – the interval in not constant –
long (ON), shorter(OFF)
 Bistable Element

Latches
1. NAND gate latch
a.S-R (Set-Reset)
b. S-C (Set-Clear)
Tracing the S’R’ latch outputs Q and Q’ given the
inputs S’ and R’

The truth table of the S’R’ latch

SR Latch with Enable

Tracing the SR latch with enable given the input
signal

Truth table SR latch with enable that can be used

in the determining the timing diagram
SR Latch with Enable Truth table which can be
used in the transition diagrams and truth tables
requiring Q and Qnext values

D Latch
Tracing the D latch outputs with the given input

D Latch with Enable

Tracing the D Latch with enable with the given
input D

Tracing the D latch with enable with the given

input signal D
Tracing the outputs of the given D latch with
enable and D F/F

Flip/Flop (F/F)
1. SR F/F
2. D F/F
3. JK F/F (Jack Kilby)
4. T F/F (Toggle)

Review
Latch – level sensitive
F/F – edge-sensitive (NGT, PGT)

1. S-R F/F (enable/clk)

Truth Table
clk S R Q Q’
Pgt/ngt 0 0 NC/ Retain
previous
output

Pgt/ngt 0 1 0 1
Pgt/ngt 1 0 1 0
Pgt/ngt 1 1 1/avoid 1/avoid
2. D F/F
clk D Q Q’
Pgt/ngt 0 0 1
Pgt/ngt 1 1 1
3. J-K F/F
clk J K Q Q’
Pgt/ngt 0 0 NC Retain
Pgt/ngt 0 1 0 1
Pgt/ngt 1 0 1 0
Pgt/ngt 1 1 Toggle Toggle

4. T F/F
Clk T Q Q’
Pgt/ngt 0 NC Retain
Pgt/ngt 1 Toggle Toggle
Asynchronous Sequential Circuit
Asynchronous Counter
 Count-up
 Count-down

Single Digit 0 – 9 (1 seven segment)

 Modulus (MOD) of a counter
- The number of different states that the
counter may take
Mod # = 2n ; n = no. of F/F
MOD 8 = 23 ; n = 3
- Has 8 different states (0 – 7)
o Count – up (Q’)
o Count – down (Q)
 Problem statement: design an asynchronous
count-up counter for MOD-8 using negative
edge-triggered J-K F/F

Synchronous Counter
- The series of F/F each clocked at the same
time
 Random sequence
  Ex. 5 – 0 – 3 – 1 – 6
Step 1
 Last count = 6 (can use the 3 – F/F)
 Use the negative-edge triggered F/F
Step 2 : Create a truth Table
Truth table of J-K F/F
00 0X
01 1X
10 X1
11 X0
Sequence QC QB QA JC KC JB KB JA KA
5 1 0 1 X 1 0 X X 1
0 0 0 0 0 X 1 X 1 X
3 0 1 1 0 X X 1 X 0
1 0 0 1 1 X 1 X X 1
6 1 1 0 X 0 X 1 1 X
J-K Excitation Table
Q Qnext J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Example that will require 4 F/F
Will at least include 8 or 9 (as the single digit)
Mod 8 (0-7) = 23 = 8 ; 3 F/F

Example Sequence: 1 – 4 – 2 – 7 – 9 – 5
Step 1:
24 = 16 ( 0 – 15) ; 4 F/F
Q Qnext J K //based from the Excitation Table
00 0X
01 1X
10 X1
11 X0
Truth Table
Sequence D C B A JD KD JC KC JB KB JA KA
1 0 0 0 1 0 X 1 X 0 X X 1
4 0 1 0 0 0 X X 1 1 X 0 X
2 0 0 1 0 0 X 1 X X 0 1 X
7 0 1 1 1 1 X X 1 X 1 X 0
9 1 0 0 1 X 1 1 X 0 X X 0
5 0 1 0 1 0 X X 1 0 X X 0
Step 4 – Logic Circuit
 Non-Single Digit Counter Design

Example. Design an asynchronous MOD-16

counter(COUNT – UP)using Negative edge-
triggered JK F/F
- Asynchronous – one after another clocking
- MOD – 16 (counts 0 – 15)

Steps:
00
01
02
03
04
05
06
07
08
09 – ones (0-9) – MOD -10
10
11
12
13
14
15 – tens (0 – 15) – MOD - 16

100
(0 – 99)
9(ones) – 4 F/F
9 (tens) – 4 F/F

156
000 – 009 (ones) – 4 F/F
010 – 099 (tens) – 4 F/F
100 – 155 (hundredths) – 1 F/F

Devices to be used in
Simulation(CircuitMaker2000)
Using 4 – F/F
count - up counter connect all Q' in the decoder
4321

L2

D C B A
V2
Q J Q J Q J Q J Q1 CP1
_ CP _ CP _ CP S2 Q2 CP2
_ CP
Q K Q K Q K Q K
V4 R R R
R 10V
+V

MOD-16 R2
1k

4321

8 2 1 L3
4
D C B A
V5
Q J Q J Q J Q J Q1 CP1
_ CP _ CP _ CP S3 Q2 CP2
_ CP
Q K Q K Q K Q K
R R R R

R3
1k

MOD - 2 Count-up Counter

4321

L5
8 4 2 1
D C B A
V9
Q J Q J Q J Q J Q1 CP1
_ CP _ CP _ CP S5 Q2 CP2
_ CP
Q K Q K Q K Q K
R R R R

R5
1k

MOD -6 count-up counter

Count-up MOD-16
tens ones

count-up(0-15)
4321
4321

1 0 1 1 0 trapping of MOD-16
1 1 0 1 0 trapping
L1 of MOD - 10
8 4 2 1
E D C B A
V1
Q J Q J Q J Q J Q J Q1 CP1
_ CP _ CP _ CP S1 Q2 CP2
_ CP _ CP
Q K Q K Q K Q K Q K
R R R R R

R1
1k

0 output of MOD -10

Maximum of 9
Trap - 10

U9B

output of MOD -16

Maximum is 15
Trap maximum ones - 6
Trap maximum tens - 1

Count-up (MOD-56)
 4321 4321

4 2 1 8 4 2 1
G F E D C B A
Q J Q J Q J Q J Q J Q J Q J Q1 CP1
_ CP _ CP _ CP _ CP _ CP _ CP _ CP Q2 CP2
Q K Q K Q K Q K Q K Q K Q K
R R R R R R R

1k

1 0 1 0 MOD - 10 (0 - 9)

(MOD-10)

Trap Output of MOD-10

MOD - 56

5 (tens) 6 (ones)

1 0 1 0 1 1 0

MOD - 56 trapping output

trapping for the Tens
Quiz – tracing -
 SET A

Set B

 Description of a F/F
1.Characteristic Table
- Specifies the functional behaviour of the F/F
 2.Characteristic Equation
- The Boolean equation that is derived directly
from the characteristic table
3.State Diagram
- Graph with nodes and directed edges
connecting the nodes

 Register
o Register set – in the processor [register,
control unit(cu), arithmetic & logic unit(alu)]
o Associated as a location in the ROM, in the
RAM, and in the Cache (part of the main
memory system) ex. In the RAM each
location is represented as an 8-bit register
o F/F - can store only one bit of data
o ASCII(American standard code for
information interchange) – 7 bit code,
UNICODE (universal code – 16 bit, 2n, n = 7
or 16 – will determine the total number of
characters that a language, ex in ASCII 2n, n
= 7, total characters – 128, every character
like “ a “ should be represented as 7 bits,
“0” to represent as a 8-bit ascii code, 30h =
00110000h
o To store a byte(8 bits) of data, <bit, nibble,
byte, word, doubleword>
 o 1 F/F = can only store 1 bit, to store a
byte(8 bits) – there’s a need to combine 8-
F/F
o 1 MB – 1 mega byte , 1, 048, 576 byte (220),
1, 048, 576 - 8-bit register locations

 Memories
- Large storage areas, store both data and
instruction (as bit representation),
transformation levels that a program needs to
 undergo until such time that it will become
signal. [user level (in between transformations)
machine level]
- Computer system – hardware design[transistor
to functional circuits(memory system,
processor system, i/o systems )], software
design (4th generation language/3rd gen
language) – high level//understood more by
the programmer, (2nd generation languages –
mid level, ex. compiler) - low level , ex.
assembly language, depending on the
instruction set of the computer, ex. X86
instruction set (Control ROM) – machine level –
representation using the HEX Values, - signal
level (logic – 0,1; circuit level – 0 volts, 5 volts)
- Work (higher – application, programmer) (mid
– computer architect)(low level – machine
language programmer designer)
o ROM (Read-Only Memory)
  Non-volatile – retains its memory
content even when the power is
removed (EX. ROM – BIOS //basic input
output system)
 Typically used to store the boot loader
for the operating system (hard disk)
 Types -


o RAM (Random – Access Memory)
 Volatile – the processor is capable of
reading and writing data
 DRAM(transistor & capacitor) &
SRAM(F/F)
FSM Finite State Machines
 Microprocessor
- Control unit
- Datapath
o ALU
o Registers