Subject : ANALOG AND DIGITAL ELECTRONICS

Regulation: R18, Sem-I.

Unit-V Sequential Circuits
Branch: II CSE- Section A&B

By
Mrs P SRIVANI
Assistant Professor, ECE Dept
 SHIFT REGISTERS

• Shift registers are constructed using several flip- flop,

connected in such a way to STORE and
TRANSFER/ Shift digital data.

• Basically, D flip-flop is used. The input data (either ‘0’ or

‘1’) is applied to the D terminal and the data will be stored
at Q during positive/negative-edge transition of the clock
pulse.
D Q

Q
 SHIFT REGISTERS

• number of
One D FF is used to store 1-bit of data. Thus, the
flip-flops used is the same with the number of bit
stored.
• Shift register mean that the data in each FF can be
transferred/move to other FF upon edge
triggering of the clock signal.
Four types of data movement in shift register are:-
• a) SISO-Serial In Serial Out
• b)SIPO- Serial In Parallel Out
• c)PISO-Parallel In Serial Out
• d)PIPO-Parallel In Parallel Out
 SHIFT REGISTERS

This registers are of two types for load

SISO (SHIFT RIGHT )
SHIFT LEFT
1. Serial load registers:

Data in
Data in Data out

Data out
(a) Serial in/shift right/serial out
(b) Serial in/parallel out

SIPO
SISO
2.Parallel load register:
PISO
Data in

Data out

(c) Parallel in/serial out

Data in
PIPO

Data out

(d) Parallel in / parallel out

 Serial
• Movement of N-bit data
require N number of CLK
pulses. Thus, the operation is
slow.
• Only one FF is required to be
connected at the output
terminal, thus only one wire is
required.
Parallel
• Require only one CLK pulse
to transfer all N-bit of data.
Thus, operation is faster than
serial.
• Required N number of
connection to the output
terminal, which is proportional
to the number of bit. Thus, too
many connection is required.
 Flip-flop connection for SISO.

1st CLK 2nd CLK 3rd CLK 4th CLK

DIN
D Q0 D Q1 D Q2 D Q3
CLK CP CP CP CP

FF0 FF1 FF2 FF3

SERIAL IN PARALLEL OUT:( SIPO)
Same as in SISO after 4 clock pulses data is loaded into the
register and the data will be available at the output after 4 clock
pulses where as in SISO the will be available at the out put after
8 clock pulses.
 PARALLEL IN PARALLEL OUT:( PIPO)
Flip-flop configuration for 4bit PIPO register.

Parallel data inputs

D0 D1 D2 D3

D Q D Q D Q D Q
C C C C

CLK

Q0 Q1 Q2 Q3

Parallel data outputs

 Flip-flop connection for PISO
Do D1 D2 D3
SHIFT/LOAD

Serial
data
out

D Q0 D Q1 D Q2 D Q3
CLK CP CP CP CP

FF0 FF1 FF2 FF3

 UNIVERSAL SHIFT REGISTER
Parallel outputs

A4 A3 A2 A1

Q Q Q Q
Clear D D D D

CLK

s1 4x1 4x1 4x1 4x1

s0 MUX MUX MUX MUX
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0

Serial
input for Serial
shift-right input for
I4 I3 I2 I1 shift-left

Parallel inputs

A bidirectional shift register. Capable of shifting contents either left or right depending upon the signals
present on appropriate control input lines.
Universal shift register: Depending on the signal values on the select lines of the multiplexers, the
register can retain its current state, shift right, shift left or be loaded in parallel. Each operation is the
result of a positive edge on the clock line.
4-bit Universal shift register selection modes.

Mode Control
s1 s0 Register Operation
0 0 No change
0 1 Shift right
1 0 Shift left
1 1 Parallel load
 APPLICATIONS

• Pseudo random pattern generator

• Ring counter

• Johnson counter or twisted counter

 COUNTERS
Counter is a sequential circuit. A digital circuit which is used for a counting pulses is known
counter. Counter is the widest application of flip-flops. It is a group of flip-flops with a clock
signal applied.

Counters are sequential logic devices that are activated or triggered by an external timing pulse
or clock signal.

Counters are of two types.

1.Asynchronous or ripple counters.

2. Synchronous counters.
 Types

Synchronous Asynchronous

independent of the
all the data bits input clock so the
change data bits change
synchronously with state at different
the application of times one after the
a clock signal other
 COUNTERS

1.ASYNCHRONOUS (RIPPLE) COUNTER :

• Definition : Type of counters in which each flip flop output
serves as the clock input signal for the next FF in the sequence.
• In Asynchronous counters , the input of some or all FFs are
triggered not by the common clock pulse, but rather by the
transition that occurs in other FF output.
• The FFs don’t change states at exactly the same time as they
don’t have a common clock pulse.
• For a ripple counter consists of n FFs , the number of its states
equals 2n , and It can count from 0 to (2n -1).

Notes :
 To operate the toggle mode , the FFs must be connected with J=K=1
 Remember that the FFs are connected in series in Asynchronous systems.
 4-bitBinary Ripple Counter
(ASYNCHRONOUS COUNTER):
Binary counter : Group of FFs connected in a special
arrangement in which the states of FF represent the binary
number equivalent to the number of pulses that have
occurred at the input of the counter.
Binary Ripple counter is called also, a Mod-X counter, where X is the number
of counter states and its equal to 2n , for n FFs .

The first FF in the counter is called LSB , and the last FF is called MSB.
The output of MSB divides the input clock frequency by X
The figure below shows a 4-bit binary counter (Mod-16) :
1. The clock pulse applied only to the Clk input of flip flop A.
2. The input for each of the next FFs is the output of the previous FF. So the
output of FF A is the input of FF B , the output of FF B is the input of FF C
, and the output of FF C is the input of FF D.
3. FF A will toggle each time the clock pulse make a transition.
4. Since The output of FF A is the input of FF B ,FF B will toggle each time
the output of FF A goes from 1 to 0 , and so on.

LOGIC DIAGRAM
5. This means only FF A responds to the clock
pulses. FF B has to wait for FF A to change states Truth table for 4-bit binary counter
before its toggled , and so on.

6. Thus, all FFs don’t changes states in exact

synchronism with the clock pulse. And because of
that it is called asynchronous counters.

7. Because of the phenomenon we talked about in 5 ,

there is a delay between the response of sequential
FFs.

8. So , this type of counters is also commonly called

a ripple counter. (simply we can say that the input
clock ripples through the counter.)

9. After 15 clock pulse , the counter has finished its

first complete cycle (0000 through 1111), and in
its 16 clock pulse it will recycle back to (0000) .

Note : . A counter may count up or count down or count up and down

depending on the input control.
 Timing diagram of a 4-bit binary ripple counter

1 1 1 1 1 1 1 1
Q 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
Q 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
Q 0 0 0 0 0
0 0 0
1 1 1 1 1 1 1 1
Q 0 0 0 0 0 0 0 0
 DETERMINING THE MODULUS OF COUNTER :

• Mod counters are defined based on the number of states that the counter will
sequence through before returning back to its original value
• For example, a 2-bit counter that counts from 002 to 112 in binary,has a modulus value
of 4 ( 00 → 01 → 10 → 11 , return back to 00 ) so would therefore be called a modulo-
4,. Note also that it has taken 4 clock pulses to get from 00 to 11.
• The maximum number of possible output states (maximum modulus) for the
counter is: 2n

• Therefore, a “mod-n” counter will require “n” number of flip-flops connected together
to count a single data bit while providing 2n different output states

• 2-BIT COUNTER MOD 4 COUNTER

• 3-BIT COUNTER MOD 8 COUNTER
Example :

A 2-bit binary counter (Mod-4) .

2- bit binary ripple counter using JK FF

Truth table State diagram

 Timing diagram

2
3
Example :

A 3-bit binary counter (Mod-8) .

3- bit binary ripple counter using JK FF

Timing diagram State diagram

24
General procedure to design a Mod-X counter ( or a X-bit
binary ripple counter) :
 State Diagram
Example :

Design a Mod-10 counter.

23 = 8 , 24 = 16 .
Thus, the number of FFs we have to use are
4 FFs.
Connect the FFs as a counter
Mod-16 counter

A B C D
 DCBA
0000
Connect the NAND gate to the asynchronous Clear inputs of all FFs.
Mod-10 counter will count from 0000 through 1001. 0001
0010
So, it must be rest to 0000 state when the count of 1010 is reached.
0011
Therefore, FF outputs B and D must be connected as the NAND gate inputs.
0100
In other words , the NAND gate will go low when B=D=1 (1010 state), thin 0101
the low at NAND output will immediately clear the counter to 0000 state.
0110
0111
1000
1001
1010

Mod-10 counter
 2.SYNCHRONOUS (PARALLEL) COUNTER :

•We see that an asynchronous suffers from what is known as

“Propagation Delay” in which the timing signal is delayed a fraction
through each flip-flop.

•All the individual output bits changing state at exactly the same
time in response to the common clock signal with no ripple effect
and therefore, no propagation delay.

•The flip-flops are clocked at the same time by a common clock

pulse. If the "clock" pulses are applied to all the flip-flops in a
counter simultaneously, then such a counter is called as synchronous
counter.
2-bit synchronous binary counter (using T flip-flops, or JK flip-flops
with identical J,K inputs).
Synchronous (Parallel) Counters

Present Next Flip-flop

state state inputs
A1 A0 A1+ A0+ TA1 TA0 TA1 = A0
0 0 0 1 0 1
0 1 1 0 1 1 TA0 = 1
1 0 1 1 0 1
1 1 0 0 1 1

A0 J A1
00 01 J Q Q
C C
Q' K Q'
K
11 10
CLK

Synchronous (Parallel) Counters

4-bit synchronous binary counters (MOD-16):
• The external clock pulses are fed directly to each of
the J-K flip flops in the counter chain and that both the
J and K inputs are all tied together in toggle mode.

•but only in the first flip-flop, flip-flop FFA (LSB) are

they connected HIGH, logic “1” allowing the flip-flop
to toggle on every clock pulse. Then the synchronous
counter follows a predetermined sequence of states in
response to the common clock signal, advancing one
state for each pulse.

•The J and K inputs of flip-flop FFB are connected

directly to the output QA of flip-flop FFA
•The J and K inputs of flip-flops FFC and FFD are driven from separate
AND gates which are also supplied with signals from the input and output
of the previous stage.

•And the additional AND gates generate the required logic for the JK
inputs of the next stage.
Timing diagram of 4-bit synchronous up counter
Truth table of 4-bit synchronous up counter
4-BIT SYNCHRONOUS DOWN COUNTER
It is obtained by connecting the AND gates to the Q
output of the flip-flops.
SYNCHRONOUS BIDIRECTIONAL COUNTER :
The figure below shows a parallel up/down counter .

The control input up/down controls whether the normal FF outputs or the
inverted once, are fed to the J&K /(T) input of the successive FFs.
Timing diagram of 4-bit synchronous up & down counter
Mealy and Moore models
 The Mealy model: The outputs are functions of
both the present state and inputs
 The outputs may change if the inputs change during
the clock pulse period
 The outputs may have momentary false values unless the inputs
are synchronized with the clocks
 The Moore model: The outputs are functions of
the present state only
 The outputs are synchronous with the clocks
 State Reduction and Assignment
 State Reduction
 reductions on the number
of flip-flops and the
number of gates
 a reduction in the number
of states may result in a
reduction in the number of
flip-flops
 a example state diagram
 only the input-output sequences
are important
two circuits are equivalent
 have identical outputs for all input
sequences
 The number of states is not important

Synchronous
Sequential Logic
 Equivalent states

 Two states are said to be equivalent

 for each member of the set of inputs, they give exactly the
same output and send the circuit to the same state or to
an equivalent state
 one of them can be removed

-51
 Reducing the state table
 e=f


d=?
 The reduced finite state machine
 The checking of each pair of states for
possible equivalence can be done
systematically
The unused states are treated as don't-care
condition  fewer combinational gates
State assignment
 To minimize the cost of the combinational
circuits
 Three possible binary state assignments
 Any binary number assignment is satisfactory
as long as each state is assigned a unique
number
use binary assignment 1