ECO Timing Optimization Using Spare Cells

Yen-Pin Chen, Jia-Wei Fang, and Yao-Wen Chang

ICCAD2007, Pages 530-535

Outline

Introduction Problem Formulation The Spare-Cell Selection Algorithm Experimental Results Conclusions

Outline

Introduction Problem Formulation The Spare-Cell Selection Algorithm Experimental Results Conclusions

Introduction

Spare cells are often used to perform ECO (Engineering Change Order) after the placement stage to change/fix a design. They are often evenly placed on the chip layout; the type and number of spare cells vary from different chip designs and are usually determined by designers empirically.

Introduction

Using spare cells is an efficient way to do netlist changes.

Save time and effort of re-placing the netlist Save production cost of masks

Outline

Introduction Problem Formulation The Spare-Cell Selection Algorithm Experimental Results Conclusions

Problem Formulation

A timing path is defined as

(1) A path from a primary input to a primary output (2) A path from a primary input to a flip-flop input (3) A path from a flip-flop output to a primary output (4) A path between a flip-flop output and a flip-flop input

An ECO path is a timing path that violates the timing constraint.

Problem Formulation

A buffering operation is to insert a buffer-type spare cell gS(i) into a net nE(j) along an ECO path. A gate sizing operation is to exchange a spare cell gS(i) with a gate gE(j) along an ECO path by rewiring.

Outline

Introduction Problem Formulation The Spare-Cell Selection Algorithm Experimental Results Conclusions

Timing Model and Properties

Synopsys Liberty library format

Use lookup table to calculate gate delays. The gate delay and the output transition time are functions

of the output loading and the input transition time.

Timing Model and Properties

Loading dominance

The effect of its output capacitance to the gate delay is much larger than that of the input transition time .(28x vs 1x)
Change of the netlist effects delay of neighbor gates only.

Shielding effect

Algorithm Overview

Buffer Insertion

We keep the solution if d(gE(M1))+d(gS(j)) < d(gE(M1)) , M: size of GE

Gate Sizing

Spare-Cell Selection inside a Bounding Polygon

Let the width of the square bounding box of gE(i) centered at gE(i) be

Let the width of the square bounding box of g(j) (g(j) G(j)) centered at g(j) be

: the capacitance per unit wirelength CEO(i) : the output pin capacitance of gate gE(i). FO(gE(i)) : the set of fan-out gates of gE(i) G(j) : the fan-outs of the gate gE(i) to be sized

Spare-Cell Selection inside a Bounding Polygon

Spare-Cell Selection inside a Bounding Polygon

Spare-Cell Selection inside a Bounding Polygon

Let the width of the square bounding box of g(k) (g(k) G(k)) centered at g(k) be

Let the width of the square bounding box of g(j) (g(j) G(j)) centered at g(j) be

G(k) : the fan-ins of the gate gE(i) to be sized G(j) : the fan-outs of the gate gE(i) to be sized

Solution Control

For each set of solutions, we keep at most k solutions. (k is a user-defined parameter)

Discard non-dominant solutions. Classify these solutions by the number of used buffers. Keep the best K solutions for each class.

Outline

Introduction Problem Formulation The Spare-Cell Selection Algorithm Experimental Results Conclusions

Shielding Effect

Shielding Effect

ECO Timing Optimization

ECO Timing Optimization

Outline

Introduction Problem Formulation The Spare-Cell Selection Algorithm Experimental Results Conclusions

Conclusions

This paper present the first work for this problem of ECO timing optimization using spare-cell rewiring.

They didnt solve the competition for using a spare cell among multiple paths. They cant insert multiple buffers in a single net.

Thanks

Timing Model and Properties

Output loading consists of

input pin capacitance output pin capacitance wire loading

c : is the capacitance per unit wirelength, FO(g(i)) : the set of fan-out gates of g(i) CO(i) : output pin capacitance of gate g(i) CI (j) : input pin capacitance of the fan-outs of the gate g(i)

Gate Sizing and Buffer Insertion

Buffering on the net nE(i) changes the delay of the driving gate and driven gates of nE(i), while other gates are little or not affected. Thus the impact of buffering on the timing of the ECO path is the delay change of gE(i), gE(i + 1), and the delay increase of the inserted buffer. Sizing the gate gE(i) changes the delay of the fan-in/fanout gates of gE(i), while other gates are little or not affected. Thus the impact of sizing gE(i) on the timing of the ECO path is the delay change of gE(i 1), gE(i + 1), and the sized gate.

Gate Sizing

We keep the solution if

d(gE(M 2))+d(gS(j)) < d(gE(M 2))+d(gE(M 1)),and d(gE(M 2)) < d(gE(M 2)),

Spare-Cell Selection inside a Bounding Polygon

Theorem 1: Given a net nE(i) with the source gE(i) and the sinks in G(j) to be buffered, inserting any buffer-type spare cell, whose output transition time is not smaller than gE(i) and with the same output loading, outside the bounding polygon (i) into the net increases the path delay.