Delay Definitions

Propagation Delay
Contamination delay
Propagation delay definition
Propagation delay
Contamination delay definition
Contamination delay
Rise and Fall time
Rise and Fall time
Delay Estimation
Switch-level RC delay models
RC delay model
Effective R & C : 3-input NAND
Effective R & C : 3-input NAND capacitance
RC delay model-Inverter
Delay of Fanout of 1 inverter
Analysis of propagation delay
Effective resistance & capacitance
Elmore delay model
Delay of 3-input NAND gate
Falling(input 111) and rising(input 110 ) equivalent circuits

t pdr  9 RC

t pdf 

(3C )( R / 3)  (3C )(2 R / 3)  (3R / 3)(9C )  12C

Rising & Falling delay example
Two components of delay
Linear delay model
Computing Logical effort
Catalog of gates: Logical effort
Calculate g, p for the complex
gate
Catalog of gates: Parasitic delay
Delay in logic gate
Delay in logic gate
Multistage Logic networks
Multistage Logic networks-Path that branch
Multistage Logic networks-Branching Effort
Multistage Logic networks- Multistage delays
Multistage Logic networks-Designing Fast
circuits
Multistage Logic networks-Gate sizes
Multistage Logic networks: 3 -stage path
3 -stage path :Example
Problem:
 Consider the path from A to B involving three two-input nand gates shown
in Figure below. The input capacitance of the first gate is C, and the load
capacitance is also C.
 What is the least delay of this path, and how should the transistors be sized
to achieve least delay
 N=3
 G=g1.g2.g3= 4/3.4/3.4/3=2.37
 H=C/C=1
 P=p1+p2+p3=2+2+2=6
 No branches B=1
 F=GBH=2.37
 fˆ=(F)1/N =(2.37)1/3 =1.29
 D=N(F)1/N +P=9.87
 Transistor size:cin=cout.gi/ fˆ
 Z=(c.4/3)/1.29 = c
 Y=(c.4/3)/1.29 = c
 C=(c.4/3)/1.29 = c
Review
 Logical effort is useful for thinking of delay in circuits
 – Numeric logical effort characterizes gates
 – NANDs are faster than NORs in CMOS
 – Paths are fastest when effort delays are ~4
 – Path delay is weakly sensitive to stages, sizes
 – But using fewer stages doesn’t mean faster paths
 – Delay of path is about log4F FO4 inverter delays
 – Inverters and NAND2 best for driving large caps
 • Provides language for discussing fast circuits
 – But requires practice to master
Power and Energy

 Power is drawn from a voltage source attached to the VDD pin(s) of a

chip.

 Instantaneous Power: P(t )  iDD (t )VDD

T T
 Energy: E   P (t )dt   iDD (t )VDD dt
0 0
T
 Average Power: E 1
Pavg    iDD (t )VDD dt
T T 0
Power dissipation
Power dissipation in CMOS circuits comes from two components:

Static dissipation
 subthreshold conduction through OFF transistors
 tunneling current through gate oxide
 leakage through reverse-biased diodes
 contention current in ratioed circuits

Dynamic dissipation
 charging and discharging of load capacitances
 "short-circuit" current while both pMOS and nMOS networks are partially ON
Ptotal=Pstatic + Pdynamic
Static Dissipation

CMOS inverter model for static power dissipation evaluation

 The power dissipation is zero when the circuit is quiescent, i.e., when
no transistors are switching.
 secondary effects subthreshold conduction, tunneling, and leakage
small amounts of static current flowing through off transistor
Pstatic = Istatic VDD
Secondary effects

 Tunneling current important for transistors around the 130 nm

generation with gate oxides of 20A °thinner.

 Diode leakage is generally smaller and can be neglected.

 static dissipation can occur in gates such as pseudo-nMOS gates
Dynamic Power dissipation
 Dynamic power is required to charge and discharge load capacitances
when transistors switch.
 One cycle involves a rising and falling output.
 On rising output, charge Q = CVDD is required
 On falling output, charge is dumped to GND
 This repeats Tfsw times over an interval of T

VDD
iDD(t)

C
fsw
Dynamic Power Cont.
T
1
Pdynamic   iDD (t )VDD dt
T 0
T
VDD

T 0 iDD (t )dt

VDD VDD
  TfswCVDD  iDD(t)
T
 CVDD 2 f sw
C
fsw
Activity Factor (α)

 Suppose the system clock frequency = f

 Let fsw = α f, where α = activity factor
 If the signal is a clock, α = 1
 If the signal switches once per cycle, α = 0.5
 Static gates
 Depends on design, but typically α = 0.1

 Dynamic power

Pdynamic   CVDD 2 f
Dynamic power cont..

 Input rise/fall time is greater than zero, both nMOS and pMOS
transistors will be ON for a short period of time additional "short
circuit" current pulse from VDD to GND increases power dissipation
by about 10% .