Physical verification

Agenda
Basics of CMOS devices
Basic DRC rules
Basics of Finfet
Double patterning
DFM
Basics of LVS
Prakash Deep Verma
Mirafra technologies
CMOS Devices

lComplementary metal–oxide–semiconductor
lAdvantage of CMOS

lHigh Noise immunity

lLow static Power consumption

Cross section of two transistor in CMOS gate
 CMOS fabrication Process

20 Steps of CMOS Fabrication Process

The CMOS can be fabricated using different
processes such as:
1. N-well process for CMOS fabrication
2. P-well process
3. Twin tub-CMOS-fabrication process
Step 1 & 2
Step 3 & 4
Step 5 & 6
Step 7 & 8
Step 9 & 10
Step 11 & 12
Step 13 & 14
Step 15 & 16
Step 17 & 18
Step 19 & 20
Twin tub CMOS Process
MOS Device Structure
MOSFET Layout
 Terminals

• Bulk - Used to make an ohmic contact to the substrate

• Gate - The gate voltage is applied in such a manner as to
invert the doping of the material directly beneath the gate
to form a channel between the source and drain.
• Source - Source of the carriers flowing in the channel
• Drain - Collects the carriers flowing in the channel
Parameter Definition
 Symbols

If the Bulk terminal is not explicitly drawn, for

NMOS (PMOS) devices, Bulk terminal to most
negative (positive) power supply terminal.
 I/V characteristic

With zero voltage across all terminal pairs, device is "off"

– Back to back reverse biased PN junctions
 Threshold voltage

NMOS with a positive gate bias applied VG

(a) Formation of a depletion region (b) Onset of inversion
 Threshold voltage

Formation of inversion layer

Threshold voltage
 I/V characteristic

NMOS with VGS and VDS

If we now apply a positive drain voltage, current will flow
How can we calculate this current as a function of VGS, VDS?
NMOS IV Characteristic
NMOS IV Characterstic
NMOS IV characteristic
PMOS IV Characteristic
PMOS IV Characteristic
PMOS IV Characterstic
 Short Channel Effect MOSFET
Short-channel effect is an effect whereby a MOSFET in
which the channel length is the same order of magnitude
as the depletion-layer widths (xdD, xdS) of the source
and drain junction, behaves differently from other
MOSFETs

As the channel length L is reduced to increase both the

operation speed and the number of components per chip,
the so-called short-channel effects arise
Five Different short channel effect

Drain-induced barrier lowering and punch-through

Surface scattering
Velocity saturation
Impact ionization
Hot electron effect
 DRC rules
Design rule checking or check(s) (DRC) is the
l

area of electronic design automation that

determines whether the physical layout of a
particular chip layout satisfies a series of
recommended parameters called design rules.
Typical Cross-section( 28nm technology)
Mask Name ID key process Sequence for typical 28nm-I
Mask Name ID key process Sequence for typical 28nm-II
Special Definition 28nm
Derived Geometry
DRC Rule :Width
DRC Rule Width
Distance of interior
l

facing edges of single

layer (W)
DRC Rule :Spacing (S)
DRC Rule :Spacing (S)
Distance of exterior
l

facing edge of one or

two layer (S)
DRC Rule :Overlap (O)
DRC Rule :Overlap (O)
Distance of interior
l

facing edge of two

layers
DRC Rule :Enclosure (EN)
DRC Rule :Enclosure (EN)
Distance of inside edge
l

to outside edge Fully

inside (EN)
DRC Rule :Extension (EX)
DRC Rule :Extension (EX)
Distance of outside
l

edge to inside edge

Interact
Inside
Outside
Area
Enclosed Area
Hole Width
Enclosed Space
3 Neighboring :
Projection
Individual Projection
l

(L1,L2)

l Union Projection (L1,L2)

Parallel run Length
Size up a , Size down b
Butted
 Notch Vs Gap

The notch

The notch command checks the spacing within the

same polygon and the gap command checks the
spacing between two different polygons
Cut
Channel Width
Channel length
Pattern Definition of Design layers
DRC rules Recap
DRC Rules Recap-I
DRC Rules Recap -II
DRC Rules Recap -III
DRC Rules Recap -IV
DRC Rules Recap -V
DRC Diffusion Related rules
DRC NWELL Rules
DRC Poly Rules
DRC Contact rules
DRC Metal 1 Rules
CMOS Inverter Layout
DRC Fixing case study –I
Minimum Length Rule
DRC Fixing case study-II
Total min Edge length rule
 DRC Fixing Case study-III
U Shaped metal spacing rule
rerouting the wire.

DRC Fixing case study – IV

Protrusion Length Rule
DRC Quiz 1
DRC Quiz Answer 1
 DRC : Anteena effect

It is plasma induced gate oxide damage which causes yield and

reliability problems during the manufacture of MOS integrated circuits
 Antenna rules in DRM

Antenna rules are normally expressed as an allowable ratio of metal area

to gate area.

There is one such ratio for each interconnect layer

 How to fix Anteena Violations
Change the order of the routing layers. If the gate(s) immediately
connects to the highest metal layer, no antenna violation will
normally occur. This solution is shown in Figure (a).

Add vias near the gate(s), to connect the gate to the highest layer
used. This adds more vias, but involves fewer changes to the rest
of the net. This is shown in Figure (b).

Add diode(s) to the net, as shown in Figure (c)

How to Fix Anteena Violations
 ERC violations
ERC (Electrical rule check) involves checking a
design for all well and substrate areas for proper
contacts and spacing thereby ensuring correct
power and ground connections
ERC steps can also involve checks for
unconnected inputs or shorted outputs.
 ERC Violations
There are certain checks like
Any Floating N-wells :
Any Floating Substrates: Then circuit will remaining uncompleted. So
that transistor will not be created .
Is N-well tap connected to GND : ( N-well Tap always connected to
VDD.)
Is P-Substrate tap connected to VDD : (P-substrate tap always
connected to VSS.)
Tap/Gate/SD Connections
Soft connections
Floating gate/substrate/metal
Valid device voltages
Voltage Dependent channel length check
Unconnected inputs/shorted outputs
 Double Patterning

Double patterning is a technique used in the lithographic

process that defines the features of integrated circuits at
advanced process nodes. It will enable designers to develop
chips for manufacture on sub-30nm process nodes using
current optical lithography systems
Patterning doubling or pitch split (DP)
Layer Decomposition (Coloring)
DRC Rules for DP
Rules unique to DP
TSMC PDK DP checks
Fixing odd path violation
DP Debugging Frustration
New Extrinsic violation
Techniques to avoid new extrinsic violation
New intrinsic violation
Debug hint to avoid new intrinsic violation -I
Debug hint to avoid new intrinsic violation -II
Example debug option
Fixing anchor path violation-1
Fixing Anchor path violation-II
Fixing multiple error type
Calibre Multi patterning
 DFM
Design for manufacturing (DFM) refers to
l

actions taken during the physical design

stage of IC development to ensure that the
design can be accurately manufactured
 DFM
lAs we moved from the 90nm node through 65nm,
40nm, 32nm, 28nm, 20nm and 16/14nm, the
industry had expected that we would transition to
EUV lithography to take advantage of shorter
wavelengths for the lithography process. But due
to delays in deploying EUV technology, the
industry is still using light-based steppers with a
wavelength of 193nm
14nm FinFET Vs Planer 28nm
Managing DP by dummy space or flipping space
 DFM:Silicon manufacturing and Process variation issue

Manufacturing Circuit Parameter Circuit operation CAD analysis

Process
Mask imperfection Channel length Temperature Timing Analysis
Alignment , Tilting Channel Width Supply voltage RC Extraction
Focus ,Dosage Threshold Voltage Aging PBTI/NBTI I-V curve
Resist thickness, Ovelap Capacitance Coupling Cell modelling
Etch capacitance
Doping Interconnect Multiple Input Process files
switching
CMP Circuit simulations
 DFM:LDE effect

t
 DFM:LDE effect

Well Proximity Effect where the closer you place

a transistor to a Well the higher the Vt value
becomes which impacts timing and leakage
DFM verification:Lithography Variability check
 Critical Area Analysis

l CAA Bridging and shorts create a failure

 CMP Hotspot check
l CMP Hotspot check flow
Manufacturing Analysis and scoring
MAS is a grading system which replicates how good your design is
in terms of DFM
lLarger the MAS value ,greater the yield
 DFM Solutions

1.Metal Filing with respect to RC extraction

analysis
2. Design rule check by pattern maching
 DFM Solution:Design rule by pattern matching

l Pattern matching flow

Number of DRC checks
 Via Optimization solution

Via failure is one of the most dominating cause of

lower reliability of the design
DFM recommendation for better reliability
1.Doubling of via
2.Insertion of via farm
3.Sufficient sized via enclosure
4.Sufficient sized via extension
Via Optimization solution
Lithography Road Map
LVS Layout Vs schematic

It comprises of three steps

1.Extraction
2.Reduction
3.comparison
result in poor circuit performance.

Typically, active and N-well layers are not routing layers, but it is still
possible to inadvertently use these layers to make electrical connections. The
problem with this is that the DRC Soft Connection
and LVS will pass, but the circuit performance
will be poor. Only a very detailed layout extraction and simulation will
find this type of “soft” error.

Typically, this type of work is not practical, so a correct-by-construction approach is taken

to avoid this effect.
 Typical Errors in LVS

lShorts: Two or more wires that should not be connected have been and
must be separated.
lOpens: Wires or components that should be connected are left dangling

or only partially connected. These must be connected properly to fix this.

lMissing component: An expected component has been left our of the

layout
 Typical Erros in LVS

Component Mismatches:Components of an incorrect type have been

used (e.g. a low Vt MOS device instead of a standard Vt MOS device)

Parameter Mismatch:Components in the netlist can contain properties.

The LVS tool can be configured to compare these properties to a desired
tolerance. If this tolerance is not met, then the LVS run is deemed to
have a Property Error
LVS:Extraction Error :Texted shorts
 LVS:Comparison Errors:Non texted shorts

Non-texted shorts are actual connectivity issues

that have been analyzed and found to be a short
by the comparison process.
 LVS Cross-Connect Errors

A cross-connect error is a common LVS

discrepancy that is caused by swapped signal
nets in the layout
 Ways to fix LVS-I

1 - Shorts
- Check LVS report's nets section.

- Number of nets in schematic > Number of nets in layout, most

probably there is a short in the layout.

- Run LVS with short isolation to detect the shorted nets.

 Ways to fix LVS-II

Opens
- Check LVS report's nets section.
- Number of nets in layout > Number of nets in
schematic, most probably there is an open in the
layout.
- Locate the open and fix the issue.
 Ways to fix LVS-III

missing text layers (calibre.txt file)

- power & ground locations should be given to calibre to allow

correct identification of the p/g nets (as a further help for
identification).

- Normally the tool can resolve these but biasing it a little helps in
terms of runtime & result
 Ways to fix LVS-IV

Missing libs in gds or in cdl or missing instance)

- Undefined cells may exist in merged gds or in merged schematic.

- Be sure the gds & schematic are generated without problems

 Ways to fix LVS-V

Missing soft layers (e.g. msub)

- msub layer, which can be used to isolate 2 different grounds may

be missing.

- This can produce thousands of errors

 Ways to fix LVS -VI

There can be many more causes, other than above. Above ones
are the most common problems encountered

The best way is to ensure that there is no drc & lvs violation at
place and route tool just before gds export (at least fix all shorts &
opens).

This will provide you a good reference starting point.

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