Engineer /Lead Engineer/Principal Engineer- Physical Design

 
·        Key Responsibilities

o   Would be responsible for hands-on physical implementation core platforms and SoC's.

o   Evaluateand deploy the evolving physical design methodologies to handle increasingly
complex SoC/IP designs within aggressive, market-driven schedules
o   Active participation in benchmarking of library, technology parameters, implementation
strategy to enable design requirements of die size, power & speed.
o   Ensure quality adherence during all stages of the project life cycle. Drive thorough analysis of
existing processes and recommend and implement the process improvements to ensure ‘Zero
Defect’ chips
o   Enable technological innovations from day to day learning & project experiences
o   Actively work as part of team both locally & also with remote or multi-site teams

Key Skills
o   Self starter with 2-12 years of experience on SOC/Chip level/IP physical design on
multimillion Gate and complex design with multiple clocks and power domains with minimal
supervision.
o   Expertise inPhysical implementation, floorplanning, partitioning, padring integration, Power
Estimation, Power Grid design, Power/IR analysis, Reliability and physical verification checks
using Synopsys/Cadence/Mentor tools
o   Sound knowledge of package type understanding, ESD integration, PI-SI analysis is desirable
o   Sound knowledge of timing closure flow with hands-on experience in synthesis, formal
equivalence, placement, optimization, low power checks, clock tree, routing, crosstalk delay/noise
analysis & repair using Cadence/Synopsys/Magma tools is desirable
o   Good control over scripting languages like PERL/TCL is MUST.
o   Knowledge of commonly used clocking, low power schemes, spice simulations, DFT
techniques are added advantage