IP Design Verification Requirement:

Label: Experience: 2+ years

IP Design Skills: IP Verification, System Verilog, UVM

Verification

1. Knowledge on Veloce – emulation tool. Or any one emulation tool

Emulation knowledge is needed
Verification
Engineer

2. Strong knowledge on SV, UVM, C based test development

3. 3+ years’ experience

Senior Engineer-Physical Design –

Experience: 2+ years

Label: PD Skills:

 RTL2GDSII implementation (40/28nm)

 Exposure on Low Power Implementations (multi-Voltage and switchable

domains)

 Prior experience handling extremely area and power sensitive designs

  Power Network Analysis and fix exposure a must

 STA-SI analysis and timing closure expertise at block level

 Traditional clock tree synthesis experience

 DRC/LVS/ANT/PERC run and fix expertise

RF integration exposure a big plus (WiFi, Bluetooth, ZigBee

Lead- Physical Design –

Experience: 8+ years

Skills:

 Experience handling Modem, DDR4, Camera subsystems

Label: PD  Good understanding of critical constraints and paths associated with these IPs
Lead
 Custom clock build exposure

 Block execution on designs with large number of feedthroughs

 Block execution on designs with voltage islands

 Netlist2GDSII exposure on <14nm designs

 7nm prior experience a big plus

 Should have lead teams

Senior Engineer - STA

Skills:

Experience: 2+ years

Label: STA Experience in post-layout constraint development to timing closure

Multi-voltage/Switching aware corner definitions

RC/C model selections based on net-lengths/block sizes/layer stack

SI parameter setting expertise

 Handshake with the design team and develop functional/DFT constraints

IP level constraint integration

Abstraction expertise like Hyperscale/ILM/ETM

RC Balancing and scaling analysis of full chip clock

RC Balancing and scaling analysis of critical data paths

DMSA @ full chip and custom scripts for timing fixes

Lead- IP Design Verification :

Skills

· 8+ years of experience in DV IP & SoC Verification.

· Experience in developing Verification environments from scratch.

Label : · Expertise in SV & UVM.

Lead IP Design · Expertise in ‘C’ based SoC or sub-system verification.
Verification

· Expertise in ARM M* series of processor.

· Experience in effort and schedule estimation, tracking and technical

leadership

Role: Senior Verification Lead / Verification Architect.

· Responsible for Leading DV efforts at IP, Sub-system and SoC level.

· Interfacing with customer and owning the technical deliverable.

Senior Verification Engineer – SoC Verification:

Skills:

This role will include-

• Technical execution of SOC Verification projects of complex ARM

based SOCs

• Test Planning, Environment Architecture, SV-UVM environments

Label: SOC Desired Skills and Experience-
Verification
• 2 - 7 years’ experience in Design Verification

• Excellent Communication and Presentation Skills

• Expert Knowledge in SOC Verification

• Expert at Verification - Coverage Driven Test Planning, Architecting

Environments, Verification Flow

• Strong knowledge in System Verilog

• Knowledge in at least one methodology, OVM, UVM, VMM or RVM

• Very Good knowledge of protocols, at least one protocol of SATA,

USB, Ethernet, PCIE

• Ability and desire to learn new methodologies, languages, protocols

etc. is required

Physical Design Implementation (2- 6 years) Skills:

Able to take up ownership of blocks independently

Need to be able to make smart decisions like optimal standard cell

selections based on PPA targets
Label: PD
Need to come up with strategies to control congestion through
Engineer
understanding of specific block level architectural challenges

Need to come up with strategies to fix RC inefficiencies built into layout

and achieve timing closure

Should be able to construct clocks on multi-clock, synchronous and

asynchronous clock domain partitions

Should be good in STA analysis

Should have owned DRC/LVS/ANT clean ups at block level

Implementation experience on IR/IVD/EM analysis & fix

Should be good in Innovus, Tempus & Genus

RTL
Experience : 4+ years
Skills:
Requirements and specifications, micro-architectural definition for
optimal area and power
Digital design RTL and verification
Synthesis, static timing analysis, formal verification, gate-level
simulations, and power estimation and optimization.
Project deliverables may include specification documents, micro-
architectural definitions, RTL code Verilog and/or System Verilog,
simulation models, test benches, gate-level netlists, timing constraints,
UPF files, and associated documentation and additional collateral.

DFT Engineer
Experience: 2- 6 years

DFT logic integration and verification.

Experience on debugging low coverage.
Gate Level DFT verification with and without timing.
Pattern generation, verification and delivery to ATE team.
Good experience on EDA tools of reputed vendor like Mentor, Synopsis.
LBIST experience is plus.
DFT mode STA and timing closer support.

Must have skills –

Good understanding on Linux comments and scripting
ATPG, LV tool knowledge
ATPG coverage enhancement
Nice to have skills –
PT run
Synthesis knowledge
Timing Knowledge
LEC

Senior/ Lead Engineer

Minimum Qualifications: BSEE and 10+ years in Design and DFT
experience. MSEE and 7+ years with DFT experience
Expertise in DFT solutions around Scan based logic testing as well
as memory testing
Expertise in DFT insertion in design with multiple power domains,
asynchronous clock domains and voltage islands.
Experience in DFT EDA tools like Mentor Tessent.
Expertise in RTL design, Synopsys DC, Prime Time, CDC.
Experience to debug patterns on tester in ATE environment.
 Understanding of SOC design flows
Preferred Qualifications: Verilog/System Verilog proficiency is
required.
FPGA usage with ARM debugger is preferred.C / C++
programming skills are highly desired.
Proficiency with scripting languages like Tcl, Perl, Python

Wafer Space
Wafer Space was founded with the ideals of providing true value to clients in product and
design services across industries.

We have achieved this by building a world class engineering team with intensive knowledge in
Chip Design, Embedded Software and Hardware. Our ability to execute complex turnkey
projects with a steadfast focus on quality is what differentiates us.

Wafer Space has a strong focus on R&D initiatives that are aligned with the market requirements
and it helps us work in areas of high complexity in Chip Design and Embedded Systems.

Wafer Space is well funded by a group of companies which have been in business for more than
50 years and are market leaders in their fields.

Openings:

We have multiple opening which are listed below with the details of each openings as listed on
the other side.

Why Work With Wafer Space

At Wafer Space, we believe that each position is a career path; not just a job. As a member of our
team you are valued for your efforts and career growth is driven entirely by your performance
and not by your years of experience. We will personally work with you to set up a career plan for
you to assist you in achieving your career goals.