Senior Mask Design Engineer

Job Responsibilities:

Place and Route

 Responsible for all aspects of RTL to GDS implementation for block level design.
 Working alongside with other team members to ensure on time delivery and high-quality
results.
 Possess strong hands-on working knowledge of deep sub-micron ASIC implementation.
 Wide experience with industry standard EDA tools for digital implementation and signoff
(Synopsys DC/ICC/ICC2/PrimeTime/Fusion Compiler, Cadence RC/Genus/Innovus/Tempus,
Menthor verification tool Calibre)
 Proven responsibility for full design flow through to design closure and tapeout
 Floor planning and power planning.
 Clock tree synthesis.
 Design optimization and timing closure.
 Proactive and self-starter.
 Proven problem solving, debug and organizational skills.
 Experience with scripting and flow automation to improve flow QoR and reduce TAT

Job Requirements:

 Bachelor’s Degree in Electrical/Electronics Engineering/Physics with VLSI exposure or equivalent

4 to 6 years of job experience in layout design & place and route field are preferred
 Proficient in TCL code.
 Good communication skills and good initiative at work
 Ability to work with multi-cultural team as a team member with strong drive to excel
 Preferred Skills and Qualifications for place and route:
 RTL Synthesis.
 Logical equivalence.
 Static timing analysis.
 Low power design implementation.
 Power analysis and IR drop signoff