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  • SNST 2

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    nguyen dinh phat
    9 views2 pages
    The responsibilities include: working with custom layouts and special floorplans, performing placement optimization to solve congestion and meet timing constraints, performing clock tree synthesis with complex clock structures and tight constraints, running DRC, LVS, and DFM for physical verification, and fixing IR drop and EM issues.

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    good document to look up

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    snst_2

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    The responsibilities include: working with custom layouts and special floorplans, performing placement optimization to solve congestion and meet timing constraints, performing clock tree synthesis with complex clock structures and tight constraints, running DRC, LVS, and DFM for physical verification, and fixing IR drop and EM issues.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    9 views2 pages

    SNST 2

    Uploaded by

    nguyen dinh phat
    The responsibilities include: working with custom layouts and special floorplans, performing placement optimization to solve congestion and meet timing constraints, performing clock tree synthesis with complex clock structures and tight constraints, running DRC, LVS, and DFM for physical verification, and fixing IR drop and EM issues.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 2

    Responsibilities:

     Work with custom layout, special floorplan instructions.


     Placement optimization for solving congestion and meeting timing critically
     Perform clock tree systhesis with complex clock structure and tight constraints
     Clean DRC. LVS. DFM (PM, LFD, VRC) for physical verification
     PISI fixing: static and dynamic IR drop, signal and power EM

    SUMMARY 1

     2.5 years of experience in Physical Design for 10nm and 8nm technologies using ICC2 tool.
     Good understanding of block level netlist to GDSII flow including PNR and Physical Verification.
     Experience in implementing high speed memory and custom layout design, including LPDDR4.
     Programming skills in Perl/TCL. Be able to debug/write scripts to reduce manual time.
     Experience in static and dynamic IR drop, signal and power EM fixing.
     Good English skills. Strong communication, time management and presentation skills.
     Gain lots of manager appreciation for good work and effective performace.
     Always be a highly-valued team member through supporting and teamwork with other engineers.
     Ability to provide mentorship and guidance to co-worker.

    Responsibilities:
     Work with custom layout, special floorplan instructions.
     Placement optimization for solving congestion and meeting timing critically
     Perform clock tree systhesis with complex clock structure and tight constraints
     Clean DRC. LVS. DFM (PM, LFD, VRC) for physical verification
     PISI fixing: static and dynamic IR drop, signal and power EM

    SUMMARY 1

     2.5 years of experience in Physical Design for 10nm and 8nm technologies using ICC2 tool.
     Good understanding of block level netlist to GDSII flow including PNR and Physical Verification.
     Experience in implementing high speed memory and custom layout design, including LPDDR4.
     Programming skills in Perl/TCL. Be able to debug/write scripts to reduce manual time.
     Experience in static and dynamic IR drop, signal and power EM fixing.
     Good English skills. Strong communication, time management and presentation skills.
     Gain lots of manager appreciation for good work and effective performace.
     Always be a highly-valued team member through supporting and teamwork with other engineers.
     Ability to provide mentorship and guidance to co-worker.

    Responsibilities:
     Work with custom layout, special floorplan instructions.
     Placement optimization for solving congestion and meeting timing critically
     Perform clock tree systhesis with complex clock structure and tight constraints
     Clean DRC. LVS. DFM (PM, LFD, VRC) for physical verification
     PISI fixing: static and dynamic IR drop, signal and power EM

    1
    SUMMARY

     2.5 years of experience in Physical Design for 10nm and 8nm technologies using ICC2 tool.
     Good understanding of block level netlist to GDSII flow including PNR and Physical Verification.
     Experience in implementing high speed memory and custom layout design, including LPDDR4.
     Programming skills in Perl/TCL. Be able to debug/write scripts to reduce manual time.
     Experience in static and dynamic IR drop, signal and power EM fixing.
     Good English skills. Strong communication, time management and presentation skills.
     Gain lots of manager appreciation for good work and effective performace.
     Always be a highly-valued team member through supporting and teamwork with other engineers.
     Ability to provide mentorship and guidance to co-worker.

    Responsibilities:
     Work with custom layout, special floorplan instructions.
     Placement optimization for solving congestion and meeting timing critically
     Perform clock tree systhesis with complex clock structure and tight constraints
     Clean DRC. LVS. DFM (PM, LFD, VRC) for physical verification
     PISI fixing: static and dynamic IR drop, signal and power EM

    SUMMARY 1

     2.5 years of experience in Physical Design for 10nm and 8nm technologies using ICC2 tool.
     Good understanding of block level netlist to GDSII flow including PNR and Physical Verification.
     Experience in implementing high speed memory and custom layout design, including LPDDR4.
     Programming skills in Perl/TCL. Be able to debug/write scripts to reduce manual time.
     Experience in static and dynamic IR drop, signal and power EM fixing.
     Good English skills. Strong communication, time management and presentation skills.
     Gain lots of manager appreciation for good work and effective performace.
     Always be a highly-valued team member through supporting and teamwork with other engineers.
     Ability to provide mentorship and guidance to co-worker.

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