Skills,Tools needed to get into different job titles in VLSI.

Credit-
*)Sreenivasa Reddy, Founder, VLSIGuru Institute (www.vlsiguru.com)
*)Krishnan R, DFT engineer@Mediatek
*)Avinash J V, Senior System Architect @ Nvidia
*)Dr Abhishek choubey, Associate professor, SNIST Hyderabad
*)Sriharsha Pudi Chip Design Engineer @Spicaworks
*)Rahul tiwari- SOC design @st microelectronics -Intern
*)Anand Saurabh-MTECH VLSI @ IIT-KGP
*)Devendar- HW engineer @ Intel
*)Sonal Shreya, Ph.D. IIT Roorkee
.*) saurav Kumar Bhardwaj analog layout design engineer Dxcorr Design Inc
*) Chaitanya Kumar- MS in Analog and Mixed Signal IC design, IIT Madras
*) Amjath Husain - RFIC Design Engineer at Qualcomm, Bangalore

NOTE:
1)Dear freshers ,
You dont need every skill,tools listed here for a fresher level job.
These skills are listed to give you an idea on which job title will be suitable to you as per
interest,skills needed.
2)Once you figure out few job titles you want to prepare ,connect with employee in that
field on linkedin take his guidance to know what are needed for freshers and prepare
only those topics

3)Visit VLSI training institute websites and check the different courses there .You will get
idea of skillset required as fresher .
.

.
*)System Architect
Please go through courses available in Coursera on Computer architecture by David Wentzlaff.
This is a free course for all VLSI architecture lovers. Also, go through Clubs Computer
architecture lecture videos in YouTube.
This role typically involves defining the architecture of an IP/System keeping in mind the
functional usecases and performance requirements. Need to closely work with SW and
HW(Design and Verif) to define the spec. Need to also model the architecture in SystemC or
equivalent to aid in early SW development and also validate the architecture in the process.
Skills
● Knowledge of computer architecture basics
● Digital design concepts
● Prior RTL design or Verification experience is an added bonus
● SystemC experience is an added bonus
● Good aptitude and problem solving skills
● Sound communication skills since it involves constant discussions with other teams
● Need to be able to appreciate the application level usage and not just the
implementation details.

*)Digital ckt design/RTL design engineer-

Skills-
1)Digital logic
2)Verilog/VHDL/System verilog.Language skills matter less than coding skills
3) computer architecture
4)timing analysis
5) fifo design: async fifo especially, fifo depth
6) point 5 needs cdc skills also
7). Power basics, as it’s becoming need of the hour as node is going down
8) some synthesis basics
9)even link basics
10) aptitude to solve puzzles, attitude
11) can do attitude
12) cmos basics
13) Knowledge on different types of synchronizers
14)state machine related problem solving skills.
Tools- Modelsim for simulation

PHD/research topics

*)SoC design engineer

Skills-Good embedded programming skills, assembly language programming ,good literature
survey of ARM Cortex series (if working on arm based SoC),good command over computer
architecture.

Tools-keil IDE (open-source from ARM), Coursera for computer architecture lessons

PHD/research topics

*)Verification engineer
Skills-
1) Digital logic
2) Verilog, System Verilog, UVM-
OOP's concepts, Assertions, coverage , Randomization, Clocking block, fork-join, reg-wire
concepts are very important
3. Ability to read a specification, understand the architecture, develop testplan, testbench
architecture, develop testbench components, testcase coding, test debug
4. Strong debug expertise.
5. Exposure to multiple protocols, at minimum SPI, APB, AXI, AHB
6. Exposure to Linux and any scripting language Perl/Tcl/Python
Tools- Mentor graphics (Questa sim ,vsim) ,EDA playground (free online compiler)

PHD/research topics
1. Low power verification
2. High speed protocols

*)Physical Design engineer

Skills:
Good tool knowledge on Innovus,ICC2 will be a good startpoint.
Should have good understanding of geometry and coordinate systems.
Good knowledge on setup/Hold checks, Clock gating checks and DFT will help in his/her career.
Strong device fundamentals starting from Semiconductors, Doping, Diode, BJT, CMOS, and
FinFET. Most importantly, exposure to all the short channel effects.
Good expertise on TCL scripting.

Tools:
Synopsys ICC2, Primetime, StarRC, ICValidator
Cadence Innovus

PHD/research topics

*)STA( Static Timing analysis) engineer-

Skills
For a Good STA engineer they should have atleast basic idea of how Physical Design happens.
Should be very good in constraints.
Should be good at synthesizing blocks. We need Design compiler or Genus Tool knowledge for
this.
DFT domain knowledge is a must today. Try attending any hands on workshops on tessent or
tetra max if possible.
Basic idea of Analog design is also a must. Since we need to handle high speed interfaces like
USB,SATA,PCIE,Serdes etc in daily basis.
There are lot of courses in Udemy to attend for STA.
https://www.udemy.com/course/asic-bootcamp-sta-basic-concepts/

Tools: PrimeTime

PHD/research topics

*)DFT (Design for testability)-

Skills-Basic electronics, Good understanding of latches and flip flops.
Can also learn from NPTEL Design for Test on JTAG,Boundry scan, scan insertion,lockup
latches, different coverage metrics required. ATPG and Mbist basic understanding.

Digital design fundamentals

Verilog basics, TB setup, running simulation, viewing the waveforms
Different types of faults, exposure to various violations
Implement DFT flow starting from RTL level using Tessent or Tetramax.

Tools-Synopsys Tetramax
Mentor graphics Tessent (more preferred)
Synopsys solvnet can be used as a reference manual to debug any errors which occur during
the test process.

PHD/research topics

*)Fabrication area (Job title ??)

Skills
1)Process information,Technology node (??)

Tools-

PHD/research topics

*)Post -Si Validation engineer/Testing

Skills-
Exposure to SOC architecture
Debug expertise on the tester

Tools-

PHD/research topics-

*)Tools Application Engineer

Application and Support Engineering role is a customer facing role
Skills: 1. Basic understanding of tool’s flow
2. Features & constraints supported by the tool
3. Knowledge on tool’s optimization techniques

Tools: SpyGlass (Lint & CDC), Zebu (Emulation), Design Compiler (synthesis)
IP application/support engineer need to have front end design and protocol knowledge like
PCIe, Ethernet etc.
SW application/Support engineering roles need to have a good understanding of SW skills.
All application engineering roles require good communication, presentation skills, multi-tasking
skills in addition to technical skills.

PHD/research topics
*)CAD engineers-(EDA tool engineer same ??)
Skill

Tool

PHD/research topics

*)R&D engineer
Skill

Tool

PHD/research topics
Vlsi architecture for machine learning
Hardware security

Analog Domain:
*)Analog /rf/mIxed signal circuit designer
Skills-
Analog circuit ,Signal and System ,Network theory
Control Systems, RC circuits, fiiters

Tools-Cadence

PHD/research topics
1. Power Management IC design:
● Energy Harvesting
● DC-DC converters
● Load transient improvement
● Battery Management
More details: http://www.ee.iitm.ac.in/qkhan/research.html
2. Data Converters:
● Delta Sigma Modulator
● Interleaved sampling systems
● Other architectures of ADCs and DACs
More Details: http://www.ee.iitm.ac.in/shanthi/publications.html
3. Broadband communications and PLL
● Equalization Techniques
● High speed open loop circuits
● Bandwidth extension techniques
 ● Transmitter design
4. RF
● Power amplifier
● Low Noise Amplifiers
● Mixers
● Narrowband circuits
● On-chip inductor design
● Transceiver end to end design, verification, validation
● RF systems testing

Links :
For lectures on various subjects in field of analog IC design:
http://www.ee.iitm.ac.in/videolectures/doku.php?id=start

Basics of RFIC design

http://www.ee.iitm.ac.in/vlsi/courses/ee6320_2020/start

https://www.youtube.com/c/RahsoftRadioFrequencyCertificate/videos

https://www.youtube.com/user/wallingphd/videos

Books -

RF Microelectronics - Behzad Razavi

High Frequency Integrated Circuits - Sorin Voinigescu
The Design of CMOS Radio-Frequency Integrated Circuits - Thomas H. Lee

*)Layout engineer-
Skills-
familiar with tools like Cadence virtuoso, Calibre
Physical verifications checks like DRC, LVS, DFM, Anteena check, Density check, emir

● A minimum of 3-4 months of training on industry certified tools would be the first step for
freshers if a company sponsors the training that would be great. Though you got trained
from a premier institute still it would take 3-4 months in a job for you to get acquainted
with industry standards.
● Should have basic understanding of tools like virtuoso and verification tools like PVS and
calibre, proficiency on these tools will be automatically gained while doing projects.
● Good understanding of semiconductor device physics which helps in understanding
different foundries device cross sections soon.
● All analog layout design concepts like matching, signal integrity, latchup and ESD etc all
concepts are explained in the book art of analog layout by alan hastings. Or follow
youtube videos link provided below
 ● Basic understanding of analog circuits like current mirror, diff pair, LDO etc
● Out of all a layout engineer needs to have great patience and attention to details.
Links :

Art of analog layout by alan hastings : https://kupdf.net/download/the-art-of-analog-layout-

alan-hastings_58e26aaddc0d606d2b8970dc_pdf

Analog electronics by Razavi :

https://www.youtube.com/watch?
v=yQDfVJzEymI&list=PL7qUW0KPfsIIOPOKL84wK_Qj9N7gvJX6v

Analog layout design concepts youtube channels :

https://www.youtube.com/channel/UCBVINEwQ_dba3FaatbXVAug

https://www.youtube.com/channel/UCgZEUbcl6Ma6r-Fi7SA6c9g

PHD/research topics

Semiconductor Devices area

*) (Job title ??)
Skill-
Attend the course called Operation of MOS transistor by Yannis Tsividis. It is free course and
can help for device modelling engineers.
Device physics,Device modelling

Tool-

PHD/research topics

Non -technical roles for engineers:

*)Technical Sales
technical understanding of products/solution/domain is highly desired/required.

*)Product manager/Program manager

*)Technical write and Content development

product guide/data sheet,writing technical blogs, creating product collateral, creating marketing
presentation slide deck
word editing skills and tools like Adobe, Framemaker is required

Academic roles
*)Professor/Lecturer

*)Coach-GATE , Skill training institute (VLSIGURU)

*)

Companies/Research labs to apply for job ,internship research fellow ,staff:

Companies

1. Mobiveil - jobs@mobiveil.com
2. Cerium Systems - resumes@cerium-systems.com
3. Savvychip - careers@savvychip.com
4. Innovium - careers@innovium.com
5. Mirafra - http://mirafra.com/careers/
6. Whizchip - https://whizchip.com/careers.php
7. Eximius - careers@eximiusdesign.com
8. Spicaworks - careers@spicaworks.com
9)Search placement section of training institutes like VLSIGURU ,Maven silicon ,Epitome
circuits etc. Their Companies hiring freshers can be found

Research labs/ universities for research position:

Credit: Madhuri V Huilgol (PD engineer at ON Semiconductor)

Pre-requisites for Interview:
1) Have good basic understanding on what is Physical design and its general flow.
2) Try to self learn physicl design and its methodologies through blogs and NPTEL
courses.
http://www.signoffsemi.com/blog/
http://www.vlsijunction.com/2015/08/physical-design.html
https://vlsipd.blogspot.com/
http://asicforphysicaldesign.blogspot.com/
www.physicaldesign4u.com
https://www.youtube.com/watch?v=lRpt1fCHd8Y&list=PLU8VFS-
HdvKtKswbcvvA8yVhzleTV7OE8

2) If you are enrolling for a paid course then try to get the maximum use of it through lab
sessions since no much theory questions will be asked in interview and its all practical scenario
questions only.

Skills Needed:
1) PD flow, (synthesis to signoff)
2) Various strategies used during every step to overcome challenges.
Eg: How to fix congestion issues during place_opt, how to improve transition without
using LVT etc
3) Understand various clock structures and Integrated clock gating techniques
4) Have good understanding on timing checks at every stage.
5) Understand various PV checks followed to make sure design is foundry specific
6) Try to learn and solve numericals on calculating setup/hold/latency etc.
7) Learn basic scripting in perl,tcl or python. Unix based environments will be there in most
of the EDA tools where these languages would be preferred for any automation or flows.
8) Understand UPF and SDCs and how are they decided and formed.
9) Understand how reliability checks are done.

Tools:
1) Synopsys tools knowledge as in ICC, ICC2, Prime time, Design compiler, StarRC XT to
certain level would be good.
2) Cadence tools like Innovus, Voltus’s basic understanding would be fine.
3) Tool related videos would be available in youtube to have a quick check on how tool is
designed and how it works.

Phd/Research topics: (Source: Google)

1) Many researches are happening in Ultra low power and Clock constraints area.
2) Some researches are over manufacturability and reliability.
Read the future work section of conference papers from proceedings of the following
conferences:
 1. Design Automation Conference (DAC)
2. International Conference on Computer-Aided Design (ICCAD)
3. International Symposium on Physical Design (ISPD)

The future work section of good papers, especially those from Prof. Yao-Wen Chang at
National Taiwan University, gives you a good idea of what are some emerging hot topics.
Don't look at hot topics because they may not be hot in a few years time. Look at emerging
topics that have a good/"good" chance of becoming a hot topic.

Alternatively, look at the "needs paper"/document from the "Call for White
Papers/Proposals" by the Global Research Collaboration (GRC) program of the
Semiconductor Research Corporation (SRC).