NAME: DAVID OLUWAFEMI JOSHUA

DEPARTMENT: COMPUTER SCIENCEAND ENGINEERING

MATRIC-NO: CSC/2018/072

OPEN FIVE
Lead Engineer - RTL Design
 Minimum 7 years of experience in RTL
 DesignCandidate must have Worked on RTL
 design of major blocks
 Worked on micro-arch of major blocks
 Strong knowledge in Design (Verilog) and verification aspects of design
 Experienced at least one complete delivery from start to finish
 Good analytical and Debug skills
 Capability to mentor Juniors in the team
 Good knowledge in at least one/two of these protocolsHBM or DDR , Ethernet, Interlaken,
AMBA
 Expected to have very deep knowledge/understanding on the blocks that you have worked
on

Senior Manager - VLSI

 Should have good understanding of ARM based architecture, CPU subsystems, interconnect,
boot process, memory subsystem
 Should have good knowledge of Interface IP blocks like PCIe or USB or Ethernet or DDRx
controller, QSPI, DMA, or other similar blocks
 Should have good understanding of IPs, integration/application requirement, work with RTL
team/vendors to achieve architecture goals
 Should have designed one or more ARM based ASIC/SoC and used one or more of PCIe,
DDRx, USB, SATA, …
 Should have good knowledge of multiple flavors of AMBA bus protocols & interconnect
solutions available
 Should have good understanding of process / flow to achieve power & performance goals
 Should understand and work on all aspects of VLSI development from SoC architecture,
micro architecture, RTL coding, RTL quality checks, silicon bring up.
 Should have good understanding of requirements from physical design, FPGA, Software,
DFT and verification team.Should have handled a design from Spec to GDS-II

RACYICS
Senior Digital Design Engineer
 Bachelor’s/Master’s Degree in Electrical Engineering or Information Technology or similar
requiredAt least 5+ years’ experience in digital design and verification
 Strong knowledge of hardware description languages (VHDL or Verilog and SystemVerilog)
 Experience in SoC designExperience in some majors IPs and SoC protocols (e.g. Arm
Cortex M3, AHB/APB)
 Experience in developing verification methodologies and infrastructure for test
benchesExperience in writing test cases in Verilog and C
 Experience in FPGA synthesis and mapping is a plusExperience in automotive reliability
applications is a plus
 Knowledge about synthesis constraints (SDC) and UPF