EE6306

EE6306 –
Digital Integrated Circuit Design
Course Instructor:
Associate Professor Goh Wang Ling
School of Electrical and Electronic Engineering
Room: S2-B2c-93
Tel: +65 6790-4943
e-mail: ewlgoh@ntu.edu.sg

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EE6306

Topics
• Review of Integrated Circuit Fundamentals 
• Layout and Design Issues 
• CMOS Digital Circuits
• BiCMOS Digital Circuits 
• Sub-System Design in Digital Circuits
• Design Methodologies

Course Coordinator Assoc Prof Jong Ching Chuen 15 hours

Other Faculty Assoc Prof Gwee Bah Hwee 9 hours

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EE6306

Content (week 1-3 and 7-8)

I. Review of Integrated Circuit Fundamentals (6 hrs)
• Characteristics of Digital Integrated Circuits
• CMOS Logic
• Other Competing Technologies
• Layout Design Rules

II. Circuit Characterization and Performance Estimation (4.5 hrs)

• Parasitic Loading Estimation
• Latch Up
• Electrostatic Discharge
• Speed and Power Trade-Off
• Ground Bounce and Interconnects

III. BiCMOS Digital Circuits (4.5 hrs)

• Introduction to BiCMOS Technology
• Low Power BiCMOS Digital Circuits
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EE6306

Text Books
1. Jan M. Rabaey, A Chandrakasan, and B Nikolic “Digital
Integrated Circuits”, 2nd Edition Prentice Hall, 2003. ISBN 0-13-
597444-5.
2. Yeo Kiat Seng, Samir S. Rofail and Goh Wang Ling,
“CMOS/BiCMOS ULSI: Low-Voltage Low-Power”, Prentice-Hall,
International Edition, 2002. ISBN 0-13-032162-1.
3. S.M. Kang and Y. Leblebici, "CMOS Digital Integrated Circuits:
Analysis and Design", 3rd Edition, McGraw-Hill, 2003. ISBN 0-07-
246053-9.

Reference Text
Neil H.E. Weste and David Harris "CMOS VLSI Design - A Circuits
and Systems Perspective", 3rd Edition, Pearson/Eddison Wesley,
2005. ISBN 0-321-26977-2.

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EE6306

What will we be learning?

1. Characteristics of Digital
Integrated Circuits
 Introduction
 pn junction & Diode Equation
 The MOSFET Transistor
 Body-Bias Effects
 I-V Relations – Linear & Saturation Modes

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EE6306

1. Introduction
A Brief History
History of semiconductor devices began in the 1930s, when
Lilienfeld and Heil first proposed the Metal Oxide
Semiconductor (MOS) Field-Effect Transistor (FET). However, it
took 30 years before this idea was applied to functioning
devices, and used in practical applications. Bipolar devices
were the mainstream digital technology up to the late 1970s.
This trend took a turn around 1980, when MOS technology
caught up and so a crossover between bipolar and MOS
shares.
Complementary-MOS (CMOS) has more widespread use due to
its low power dissipation, high packing density and simple
design, such that by 1990, CMOS covered more than 90% of the
total MOS sales where the relation between MOS and bipolar
sales was two to one. 6
EE6306

 Integrated circuits: many transistors on one chip.

 Very Large Scale Integration (VLSI): very many
 Complementary Metal Oxide Semiconductor
– Fast, cheap, low power transistors
 Today: How to build your own simple CMOS chip
– CMOS transistors
– Building logic gates from transistors
– Transistor layout and fabrication
 Rest of the course: How to build a good CMOS chip

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EE6306

This course aims to convey a knowledge of advanced

concepts of circuit design for digital LSI and VLSI
components in state of the art MOS technologies.
Emphasis is on the circuit design, and optimization of either
very high speed or low power circuits for use in applications
such as microprocessors, signal and multimedia processors,
communications, memory and periphery.
Special attention will be devoted to the most important
challenges facing digital circuit designers today and in the
coming decade, being the impact of scaling, deep sub-
micron effects, interconnect, signal integrity, power
distribution and consumption, and timing.

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EE6306

Brief History
Invention of the transistor (BJT) 1947
Shockley, Bardeen, Brattain – AT&T Bell Labs

Single-transistor integrated circuit 1958

Jack Kilby – Texas Instruments on Germanium

1st Commercially Available IC Chip

Robert Noyce – Fairchild Camera, 1961
Invented junction transistors on silicon using basic
process techniques of modern IC chips which
then served as a model for all subsequent ICs
Invention of CMOS logic gates 1963
Wanlass & Sah – Fairchild Semiconductor

First microprocessor (Intel 4004) 1970

2,300 MOS transistors, 740 kHz clock frequency

Very Large Scale Integration (VLSI) 1978

Chips with more than ~20,000 devices
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EE6306

Design Abstraction Levels

SYSTEM

MODULE
+

GATE

CIRCUIT
Vin Vout

DEVICE
G
S D
n+ n+

FIGURE 1 Design abstraction

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EE6306

Silicon Lattice
 Transistors are built on a silicon substrate
 Silicon is a Group IV material
 Forms crystal lattice with bonds to four neighbors

Si Si Si

Si Si Si

Si Si Si

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EE6306

Dopants
 Silicon is a semiconductor
 Pure silicon has no free carriers and conducts poorly
 Adding dopants increases the conductivity
 Group V: extra electron (n-type)
 Group III: missing electron, called hole (p-type)

Si Si Si Si Si Si
- +

+ -
Si As Si Si B Si

Si Si Si Si Si Si

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p-n Junctions
 A junction between p-type and n-type semiconductor
forms a diode.
 Current flows only in one direction

p-type n-type

anode cathode

FIGURE 4 pn junction
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Diode Equation
The ideal diode equation (for both forward & reverse-bias
conditions) is
ID = IS(eVD/T – 1) (1.1) +
VD
where: -
VD is the voltage applied to the 2.5
junction.
A forward-bias lowers the potential
1.5
barrier allowing carriers to flow across
the diode junction.
A reverse-bias raises the potential 0.5
barrier & the diode becomes
nonconducting.
Thermal voltage, T = kT/q = 26 mV at -0.5
-1 -0.8 -0.5 -0.3 0 0.25 0.5 0.75 1
300K.
IS is the saturation current of the diode. VD (V)
I-V curve of a diode
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EE6306

The MOS Transistor

Polysilicon Aluminum

Cross sectional schematic view of a typical nMOS transistor

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NMOS Transistor Cross Section

Gate oxide
Polysilicon
W Gate
Source Drain Field-Oxide
n+ n+ (SiO2)
L
p-substrate
p+ stopper

Bulk (Body)
Schematic cross-sectional view of a NMOSFET

n areas have been doped with donor ions (arsenic) of

concentration ND – electrons are the majority carriers
p areas have been doped with acceptor ions (boron) of
concentration NA – holes are the majority carriers
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nMOS Transistor
 Four terminals: gate, source, drain, body
 Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors
– SiO2 (oxide) is a very good insulator
– Called metal – oxide – semiconductor (MOS) capacitor
– Even though gate is no longer made of metal

Source Gate Drain Polysilicon

SiO2

n+ n+
p bulk Si
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nMOS Operation
 Body is commonly tied to ground (0 V)
 When the gate is at a low voltage:
– p-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF

Source Gate Drain

Polysilicon
SiO 2

0
n+ n+
S D
p bulk Si
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nMOS Operation Cont.

 When the gate is at a high voltage:
– Positive charge on gate of MOS capacitor
– Negative charge attracted to body
– Inverts a channel under gate to n-type
– Now current can flow through n-type silicon from
source through channel to drain, transistor is ON

Source Gate Drain

Polysilicon
SiO2

1
n+ n+
S D
p Bulk Si
bulk
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pMOS Transistor
 Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior

Source Gate Drain

Polysilicon
SiO2

p+ p+

n bulk Si
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EE6306

MOS Transistors Types & Symbols

G G G

S D S D S D
B
(a)NMOS Enhancement (b) NMOS Enhancement (c) NMOS Depletion
as 4-terminal device as 3-terminal device as 3-terminal device

G G G

S D S D S D
B
(d) PMOS Enhancement (e) PMOS Enhancement (f) PMOS Depletion
as 4-terminal device as 3-terminal device as 3-terminal device

MOS transistor symbols

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MOS(FET) Transistor As Switch

o The NMOS transistor can be viewed to act as a switch.
o When a gate voltage,VGS > threshold voltage VT, a
conducting channel is developed between drain &
source.
o A voltage difference between drain & source causes
current to flow between the two regions.
o VGS modulates the conductivity of the channel where the
larger the voltages difference between gate & source,
the smaller the channel resistance and the larger the
current.
o When VGate < VT no such channel exists, and the switch is
considered open.

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Switch Models of NMOS &

PMOS Transistors
|VGS | Gate |VGS | Gate

Source Drain Source Drain

(of carriers) (of carriers) (of carriers) (of carriers)

Open (off) (Gate = ‘0’) Closed (on) (Gate = ‘1’) Open (off) (Gate = ‘1’) Closed (on) (Gate = ‘0’)
Ron Ron

|VGS| < |VT| |VGS| > |VT| |VGS| > |VDD| – |VT| |VGS| < |VDD|– |VT|

Switch Models of MOSFETs

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Threshold Voltage Concept

G
VGS
+
S D
-

n+ n+

depletion
n-channel p-substrate region

B
Inversion of a channel in a NMOSFET

The value of VGS where strong inversion occurs is called

the threshold voltage, VT.
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EE6306

The Threshold Voltage

The value of VGS where strong inversion occurs is called the
threshold voltage VT.
Q B0 Qo QI
VT 0   ms  2 F    Implants (1.2)
C ox C ox C ox charge

Work function difference (-ve) QB0 = Depletion layer charge

kT N A
For NMOS, Fermi potential  F  ln (1.3)
q ni
ms = metal-semiconductor work function potential difference = m - s (-ve);
F = Fermi potential;
NA = acceptor ion concentration;
ni = intrinsic carrier concentration in pure Si  1.5x1010 cm-3 at 300K;
QB0 = charge in the space-charge layer when the arbituary reverse bias source to bulk
voltage VSB is zero; {-ve for p-type substrate & +ve for n-type substrate}
QI = Implant charge
Qo = fixed positive oxide charge;
Cox = gate oxide capacitance per unit area = ox/tox (= 3.97 with o = 3.5  10-13 F/cm).
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Body-Bias Effects
Up till now, we have ignored the presence of the p-type
substrate. In reality, the MOSFET is a four-terminal device with
the substrate being the bulk (B) terminal of the device.
0.9
Body-bias effects occur
0.85
when a voltage VSBn 0.8
exists between the 0.75
source and bulk 0.7
terminals of a nFET. 0.65
0.6
0.55
0.5
0.45
0.4
-2.5 -2 -1.5 -1 -0.5 0
VBS (V)
VT versus VBS
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EE6306 Body Bias Effects

The substrate bias effect Source Gate Drain

Polysilicon

• (also called body effect) SiO2

• increases VT for either type of device. 0

n+ n+
S D
p bulk Si

VSB is normally +ve for n-channel devices with the body

tied to ground.
In MOS ICs, it may sometime be impractical to connect
each source to the substrate. In these cases, possible VT
shift due to the body effect must be taken into account in
the circuit design.
A negative bias causes VT to increase from 0.45 V to 0.85 V.
Since this is the gate voltage necessary to invert channel, it
increases if the source voltage increases in the case of
source connected to the channel.
Increase in VT with VS is called the body effect.
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EE6306 Body Bias Effects

Body Effect Model

VT  VT 0    s  V SB   s  (1.4)

 VT0 is the threshold when the source is at the body potential.

That is at VSB = 0

NA
 s = surface potential at threshold s  2vT ln (1.5)
ni
 Depends on doping level NA and
 intrinsic carrier concentration ni

tox 2q si N A
  = body effect coefficient   2q si N A  (1.6)
 ox Cox
 (in the range of 0.4 to 1
V1/2)
 Depend also on doping level NA

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EE6306

Transistor in Linear Mode

Assuming VGS > VT VDS < VGS - VT
VGS
VDS
S G D
ID

n+ - V(x) + n+

B
Linear conduction in NMOSFET

*Current is a linear function of both VGS and VDS

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EE6306 Transistor in Linear Mode

At a point x along the channel, the voltage is V(x), and the

gate-to-channel voltage at that point equals to VGS -V(x).
Assume this voltage > VT all along the channel:

Channel charge Qi(x) = Cox·[VGS – V(x)  VT] (1.7)

where Cox = ox/tox (ox = 3.97  o = 3.5  10-11 F/m; o = oxide
permittivity; and tox = thickness of oxide (= 10 nm or smaller)

Current is the product of the drift velocity of the carrier n and

the available charge. Due to charge conservation, it is a
constant over the length of the channel. W is the width of the
channel in a direction perpendicular to the current flow.

ID = -n(x)Qi(x)W (1.8)

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EE6306 Transistor in Linear Mode

Electron velocity is related to electric field through mobility n

(m2/V.s) dV
 n    n  x    n (1.9)
dx

Combining all,
ID dx = nCoxW (VGS  V  VT)dV. (1.10)

Integrating Eq. (1.10) over the channel L yields the I-V relation
of the transistor.

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I-V Relation: Linear Mode

For long-channel devices (L > 0.25 micron):
When VDS  VGS – VT ,
W   V
2

I D  kn '  VGS  VT V DS  DS
 (1.11)
L   2 
where
kn’ = nCox and is the process transconductance parameter
(n is the carrier mobility (m2/Vsec)
kn = kn’  W/L is the gain factor of the device

For small VDS, there is a linear dependence between VDS

& ID, hence the name resistive or linear region

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Transistor in Saturation Mode

Assuming VGS > VT
VDS > VGS - VT
VGS
G D VDS
S
ID

n+ - VGS - VT + n+

Pinch-off

B
NMOSFET in saturation

The current remains constant (saturates)

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I-V Relation: Saturation Mode

For long channel devices:
 When VDS  VGS – VT , I '  k n '  W  V  V 2 (1.12)
D GS T
2 L

since the voltage difference over the induced channel (from

the pinch-off point to the source) remains fixed at VGS – VT.
 However, the effective length of the conductive channel is
modulated by the applied VDS, so

ID = ID’ (1 + VDS) (1.13)

where  is the channel-length modulation (varies with the inverse

of the channel length), i.e., an empirical constant parameter.
We will revisit channel-length modulation at the section of non-ideal
transistor behavior. 34
EE6306

Current Determinates
For a fixed VDS and VGS (> VT), IDS is a function of:
 the distance between the source and drain, L
 the channel width, W
 the threshold voltage, VT
 the thickness of the SiO2, tox
 the dielectric of the gate insulator (SiO2), ox
 the carrier mobility
 for NMOS: n = 500 cm2/V-sec
 for PMOS: p = 180 cm2/V-sec

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Power Supply Voltage

 GND = 0 V
 In 1980’s, VDD = 5V
 VDD has decreased in modern processes
 High VDD would damage modern tiny transistors
 Lower VDD saves power
 VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

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What will we be learning?

2. MOS Transistor Theory
 Introduction
 Threshold Voltages
 MOS Capacitor
 nMOS I-V Characteristics
 pMOS I-V Characteristics
 Gate and Diffusion Capacitance

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2.1 Introduction
 So far, we have treated transistors as ideal switches
 An ON transistor passes a finite amount of current
– Depends on terminal voltages
– Derive current-voltage (I-V) relationships
 Transistor gate, source, drain all have capacitance
– I = C (DV/Dt)  Dt = (C/I)DV
– Capacitance and current determine speed
 MOS transistor is hence a majority-carrier device in
which the current in a conducting channel between the
source and drain is controlled by a voltage applied to
the gate.

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MOS Transistor Symbols

 If the body (substrate or well) connection needs to be
shown, the symbols in Figure 2.1(b) will be used.

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MOS Capacitor – A Simple MOS Structure

 Gate and body form MOS capacitor
 Operating modes:
(a) Accumulation V < 0 polysilicon gate
g silicon dioxide insulator
(b) Depletion +
-
p-type body
(c) Inversion
(a)
0 < V g <Vt
+ depletion region
-

(b)
V g > Vt
FIG. 2. 2 + inversion region
MOS structure demonstrating - depletion region
(a) accumulation,
(b) depletion, and
(c) inversion. (c) 40
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(a) Accumulation Mode:

When a negative voltage is applied to the gate, the negative
charge on the gate causes the mobile positive charged holes to
be attracted to the region beneath the gate.
(b) Depletion Mode:
The low positive voltage applied to the gate results in some
positive charge on the gate. The holes in the body are repelled
from the region directly beneath the gate, resulting in depletion
region forming below the gate.
(c) Inversion Layer:
A higher positive potential exceeding a critical threshold voltage
Vt is applied to the gate, attracting more positive charge to the
gate. The holes are repelled further and a small number of free
electrons in the body are attracted to the region beneath the
gate. This conductive layer of electrons in the p-body is called the
inversion layer.
The threshold voltage depends on the number of dopants in the
body and the thickness tox of the oxide. It is usually positive for
nMOS but can be engineered to be negative.
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Terminal Voltages Vg
 Mode of operation depends on Vg, Vd, Vs +
Vgs
+
Vgd
– Vgs = Vg – Vs - -
– Vgd = Vg – Vd Vs Vd
- Vds +
– Vds = Vd – Vs = Vgs - Vgd
 Source and drain are symmetric diffusion terminals
– By convention, source is terminal at lower voltage
– Hence Vds  0
 nMOS body is grounded. First assume source is 0 too.
 Three regions of operation are:
– Cutoff
– Linear
– Saturation

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I. nMOS Cutoff Vgs = 0 Vgd

+ g +
 No channel - -
 Ids = 0 s d
n+ n+
FIG. 2.3
(a) nMOS transistor demonstrating p-type body
cut-off, linear and saturation
regions of operation b
• The above shows a nMOS transistor with a grounded source
and p-type body.
• The transistor consists of the MOS stack between two n-type
regions called the source (s) and drain (d).
• The source and drain have free electrons.
• The body has free holes but no free electrons.
• The junctions between the body and the source or drain are
reverse-biased, so almost zero current flows.
• The above mode shows that the transistor is cutoff. 43
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II. nMOS Linear, Resistive, or Unsaturated

Vgs> V
 Channel (inversion region of t + g +
Vgd = Vgs
electrons, i.e., the majority - -

carriers) that is formed when s d

Vds= 0
Vgs > Vt, connects the source n+ n+

and drain, creating a p-type body

conductive path. b
 Current flows from drain (d) to (b) If Vds = 0, there is no electric field to push
source (s), i.e., e- from s to d. current from drain to source.

 The number of carriers and Vgs> Vt Vgs > Vgd > Vt

the conductivity increases + g +
with the gate voltage. -
s
-
dI ds
 Linear channel formed and Ids n+ n+ 0 < V < V -V
ds gs t
increases with Vds p-type body
 Similar to linear resistor. b
 Current increases both the FIG. 2.3 (Contd.)
(c) With a small positive Vds applied to the
drain and gate voltages. drain, current Ids flows through the channel
from drain to source. 44
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nMOS Saturation
 If Vds becomes sufficiently large that Vgd < Vt, the channel is no
longer inverted near the drain and becomes pinched off.
 However, conduction is still brought about by the drift of
electrons under the influence of the positive drain voltage. As
electron reaches the end of the channel, they are injected
into the depletion region near the drain and accelerated
towards the drain. Above this drain voltage the current Ids is
controlled only by the gate voltage and ceases to be
influenced by the drain, i.e., Vds. This mode is called saturation.
V >V
gs t+ Vgd < V
+ t
g
- - V >V -V
d gs t
s d I ds
s
n+ n+
FIG. 2.3 (Contd.)
(d) Channel pinched-off. Ids p-type body
independent of Vds
b
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pMOS Transistor
 pMOS transistor operates in just the opposite fashion.
 The n-type body is tied to a high potential so the junctions
with the p-type source and drain are normally reverse-
biased.
 When the gate is also at high potential, no current flows
between the drain and source.
 When the gate voltage
is lowered by a threshold
Vt, holes are attracted
to form a p-type
channel immediately
beneath the gate,
allowing current to flow
between drain and
source. 46
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2.2 Ideal I-V Characteristics

 In Linear region, Ids depends on
– How much charge is in the channel?
– How fast is the charge moving?
 The delay of MOS circuits is determined by the time required to
charge or discharge the capacitance of the circuits.
 The gate of an MOS transistor is inherently a good capacitor
within a thin dielectric; indeed its capacitance is responsible for
attracting carriers to the channel and thus for the operation of
the device.
 The junctions of the reverse-biased p-n junctions from source or
drain to the body contribute additional parasitic capacitance.
 The capacitance of the wires interconnecting the transistors is
also very significant.
 The understanding of an idealized model relating current and
voltage (I-V) for a transistor provides a general understanding of
transistor behavior and will be covered in this section. 47
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Channel Charge
 MOS structure looks like parallel plate capacitor while
operating in inversion: Gate – oxide – channel
 When nMOS is switched on, the gate attracts carriers
(electrons) to form a channel.
 The electrons drift from source to drain at a rate proportional to
the electric field between these regions.
 Thus, we can compute currents if we know the amount of
charge in the channel and the rate at which it moves.

polysilicon
gate
W
t ox
n+ L n SiO2 gate oxide
(good insulator, ox= 3.9)
p-type body +
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Channel Charge
 Charge on each plate of a capacitor is Q = CV.

 Thus the charge in the channel Qchannel is Qchannel  C g Vgc  Vt 
where Cg is the capacitance of the gate to the channel and (2.1)
Vgs – Vt is the amount of voltage attracting charge to the
channel beyond the minimum required to invert from p to n.

*Note: The gate voltage is

reference to the channel,
which is not grounded. So
average channel potential, Vc

Vs  Vd  Vds
Vc   Vs 
2 2

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Gate Capacitance
 The gate can be modelled as a parallel plate capacitor
with capacitance proportional to area over thickness.
WL
C g   ox (2.2)
t ox
where the permittivity ox = 3.90 for SiO2 and 0 is the permittivity of free
space, 8.854  10-14 F/cm. Often the ox /tox term is called Cox, the
capacitance per unit area of the gate.
Cox = ox/tox

polysilicon
gate
W
t ox
n+ L n+ SiO2 gate oxide
p-type body (good insulator,  ox= 3.90 )
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Channel Charge
 A capacitor is a two-terminal device.
 When the transistor is on, the channel extends from the
source (and reaches the drain if the transistor is
unsaturated, or stops short in saturation).

Qchannel  CV or Qchannel  C g Vgc  Vt  (2.1)

WL
C  C g   ox  CoxWL (2.2)
t ox
 Vds 
(2.3)
V  V gc  Vt   V gs    Vt
 2 

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Carrier Velocity
 Charge is carried by e-.
 Carrier velocity, v, proportional to lateral E-field
between source and drain. v  E
(2.4)
Vds
 Electric field E (2.5)
L
 The time required for carriers to cross the channel
L
t (2.6)
v

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nMOS Linear I-V

 Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
Qchannel Qchannel
I ds   I ds 
t L/v
 W V 
 C ox V gs  Vt  ds Vds (2.7)
L 2 
 Vds 
  V gs  Vt  Vds
 2 
W
where   C ox , also known as gain factor of the device.
L
Eq. (2.7) describe the linear region of operation, for Vgs > Vt
and at relatively small Vds. It is called linear or resistive since
Vds/2 << Vgs – Vt, where Ids increases almost linearly with Vds.
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nMOS Saturation I-V

 If Vgd < Vt, channel pinches off near drain
– i.e., when Vds > Vdsat = Vgs – Vt
 The drain voltage no longer increases current

 Vdsat 
I dsat   V gs  Vt  Vdsat
 2 
 Substituting Vgs = Vdsat

I dsat  V gs  Vt 
2
(2.8)
2
 Idsat is sometime called the current when a transistor is fully
ON, i.e., Vgs = Vds = VDD.

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nMOS I-V Summary

 Shockley 1st order transistor models


 0 Vgs  Vt cutoff

  Vds V V  V
I ds   Vgs  Vt   ds linear (2.7)
 2 
ds dsat

 
Vgs  Vt 
2
 Vds  Vdsat saturation (2.8)
2

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Example
 Using the 0.6 m process from AMI Semiconductor,
– tox = 100 Å 2.5
Vgs = 5
  = 350 cm /V*s
2
2
– Vt = 0.7 V

I (mA)
 Plot Ids vs. Vds 1.5 Vgs = 4

– Vgs = 0, 1, 2, 3, 4, 5

ds
1
– Use W/L = 4/2  Vgs = 3
0.5
Vgs = 2
Vgs = 1
Solution: 0
0 1 2 3 4 5
We first calculate : Vds

W  3.9  8.85  1014   W  W

  Cox   350   8  L   120  A / V 2

L  100  10   L
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pMOS I-V
 All dopings and voltages are inverted for pMOS.

 Mobility p is determined
by holes:
– Typically 2-3x lower than
that of electrons n
– 120 cm2/V*s in AMI 0.6
m process
 Thus pMOS must be wider
to provide same current
– In this course, assume
n/p = 2

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2.3 C-V Characteristics

 Any two conductors separated by an insulator have
capacitance.
 Each terminal of an MOS transistor has capacitance to the
other terminals. In general, these capacitances are
nonlinear and voltage dependent (C-V); however, they
can be approximated as simple capacitors when their
behavior is averaged across the switching voltages of a
logic gate.
 Gate to channel capacitor is very important
– Creates channel charge necessary for operation
 Source and drain have capacitance to body
– Across reverse-biased diodes
– Called diffusion capacitance because it is associated
with source/drain diffusion
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2.3.1 Simple MOS Capacitance Model

I. Gate Capacitance
 The gate of an MOS transistor is a good capacitor.
 Its capacitance is necessary to attract charge to invert the
channel, so high gate capacitance is required to obtain
high Ids.
C g  C oxWL (2.9)

W
t ox
n+ L n+ SiO2 gate oxide
(good insulator, ox = 3.90)
p-type body
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I. Gate Capacitance (Continued)

 Most transistors used in logic are of minimum

manufacturable length L because this results in greatest
speed and lowest power consumption. Thus taking this
minimum L as a constant for a particular process, we can
define
C g  C permicon  W (2.10)

 ox
where C permicon  C ox L  L (2.11)
t ox

 For advanced manufacturing process in which both the

channel length and oxide thickness are reduced by the
same factor, Cpermicron remains unchanged (and has a
value of about 1.5 – 2 fF/m of gate width.

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II. Diffusion Capacitance

 In addition to the gate, the source and drain also have
capacitances. They are undesirable, and are hence called
parasitic capacitance. They arise from the reverse-biased p-
n junctions between the source or drain diffusion and the
body and hence are also called diffusion capacitance, Csb
and Cdb.
 Capacitance depends on area and perimeter of source
and drain diffusion, depth of diffusion, doping levels, and
voltage.
 As diffusion has both high capacitance and high resistance,
it is generally made as small as possible in the layout, where
– Use small diffusion nodes
– Comparable to Cg for contacted diff
– ½ Cg for uncontacted
– Varies with process
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II. Diffusion Capacitance (continued)

 Three types of diffusion regions are frequently seen, and
they are illustrated with two series transistors in Fig. 2.9.
(b) Drain of bottom transistor & source of top
transistor form a shared contacted diffusion region.

(c) Source & drain

are merged into an
(a) Each source & uncontacted region.
drain has its own
isolated region of
contacted diffusion.

Cg = Csb = Cdb ~ 2 fF/m (for contacted source and drain regions. The diffusion
capacitance of the uncontacted source or drain is lesser due to the smaller area. 62
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2.3.2 Detailed MOS Gate Capacitance Model

 The MOS gate sits above the channel and may partially
overlap the source and drain diffusion areas.
 The gate capacitance therefore has two components: the
intrinsic capacitance (over the channel) and the overlap
capacitances (to the source, drain, and body).

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Detailed MOS Gate Capacitance Model (continued)

 Intrinsic capacitance was approximated as a simple parallel

plate in Eq. (2.9). But bottom plate of capacitor is in fact
dependent on the mode of operation of the transistor.
1. Cutoff - When transistor is OFF (Vgs = 0), channel is not inverted
and charge on the gate is matched with opposite charge from
the body. This is called Cgb, the gate-to-body capacitance. As
Vgs increases but remains below a threshold, a depletion region
forms at the surface. This effectively moves the bottom plate
downwards from the oxide reducing the capacitance.
2. Linear - When Vgs > Vt, channel inverts and again serves as a
good conductive bottom plate. However, the channel is
connected to the source and drain, rather than the body. At
low value of Vds, the channel charge is roughly shared
between source and drain, so WLC ox C 0
C gs  C gd   (2.12)
2 2
As Vds increases, region near the drain becomes less inverted,
so a greater fraction of the capacitance is attributed to the
source and a smaller fraction to the drain. 64
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Detailed MOS Gate Capacitance Model (continued)

3. Saturation - At Vds > Vgs - Vt, the transistor saturates and the
channel pinches off. At this point, all the intrinsic capacitance is
to the source. Because of pinchoff, the capacitance in
saturation reduces to 2
C gs  C 0 (2.13)
3
for an ideal transistor.
The behavior in these three regions can be approximated
as shown in Table 2.1.
Table 2.1 Approximation of intrinsic MOS gate capacitance
Parameter Cutoff Linear Saturation
Cgb C0 0 0
Cgs 0 C0/2 2/3 C0
Cgd 0 C0/2 0
Cg = Cgs + Cgd + Cgb C0 C0 2/3 C0
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 The gate overlaps the source and drain by a small amount

in a real device and also has fringing fields terminating on
the source and drain.
 This leads to additional overlap capacitances, as shown in
Fig. 2.10.
 These capacitances are proportional to the width of the
transistor. Typical values are Cgsol = Cgdol = 0.2 – 0.4 fF/m.

C gs overlap   C gsolW (2.14)

C gd overlap   C gdolW (2.15)

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 The experimentally measured Cgs and Cgd of a long channel

nMOS transistor (W = 49.2 m, L = 4.5 m) is shown in Fig. 2.11(a).
 This graph shows the normalized capacitance varying as a
function of Vds for a number of Vgs – Vt values.
 Observe that at Vds = 0, Cgs = Cgd = C0/2.
 As Vds increases, the capacitances approach Cgs = (2/3)C0 and
Cgd = 0, as expected when the transistor is saturated.

(2/3)C0

C0/2

Fig. 2.11
(a) 67
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Fig. 2.11(b) shows measured capacitances of a shorter channel

transistor (W = 49.2 m, L = 0.75 m). Observe that Cgd does not
go to 0 in saturation because the overlap component Cgd(overlap)
is significant. Overlap capacitance becomes relatively more
important for shorter channel transistors because it is a larger
fraction of the total.

(b)
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 It is convenient to view the gate

capacitance as a single-
terminal capacitor attached to
the gate.
 Because the source and drain
actually form second terminals,
the effective gate capacitance
varies with the switching activity
of the source and drain.
 Fig. 2.12 shows the effective
gate capacitance in a 0.35 m
process for seven different
combinations of source and
drain behaviour.
 The overlap capacitance also
displays a voltage dependence.

 For the purpose of delay calculation of digital circuits, we

usually approximate Cg = Cgs + Cgd + Cgb ~ C0.
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2.3.3 Detailed MOS Diffusion Capacitance Model

 The reverse-biased p-n junction between the source diffusion
and the body distributes parasitic capacitance.
 The capacitance depends on:
– area AS and
– sidewall perimeter PS of the source diffusion region.
– Area AS = WD
– Perimeter PS = 2W + 2D
(Of this perimeter, W abuts the gate
& the remaining W + 2D does not)
 The total capacitance is
C sb  AS  C jbs  PS  C jbssw
Units: (2.16)
capacitance/area for Cjbs &
capacitance/length Cjbssw.

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Detailed MOS Diffusion Capacitance Models – Junction Capacitance

 Since the depletion region thickness depends on the reverse
bias, these parasitics are nonlinear. The area junction
capacitance term is  Vsb 
M J

C jbs  C j 1   (2.17)

 0 
where
CJ = junction capacitance at zero bias (highly process-dependent).
MJ = junction grading coefficient, typically 0.5 to 0.33 depending on
the abruptness of the diffusion junction.
0 = built-in potential that depends on doping level.
NAND
 0  vT ln (2.18)
ni2
vT = thermal voltage = kT/q (26 mV at room temperature), where
k = 1.38  10-23 J/K is Boltzmann’s constant,
T = absolute temperature (300 K at room temperature), and
q = 1.602  10-19 C is the charge of an electron.
ni = intrinsic carrier concentration in undoped Si = 1.451010 cm-3 at 300K.
NA and ND are the doping levels of the body source diffusion region.
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Detailed MOS Diffusion Capacitance Models – Sidewall Capacitance

 The sidewall capacitance term is of a similar form but uses
different coefficient  M JSW
 Vsb 
C jbssw  C jSW 1   (2.19)
 0 
 The capacitance distributed by the sidewall facing the
channel can be modified slightly by the presence of the
channel depletion region and the modified doping profiles. In
some SPICE models, the capacitance of this sidewall abutting
the gate is specified with another set of parameters:
 M JSWG
 Vsb 
C jbsswg  C jSWG 1   (2.20)
 0 
 The drain diffusion has a similar capacitance dependent on AD, PD, and
Vdb. Equivalent relationships hold for pMOS transistors, but doping levels
differ.
 As the capacitances are voltage-dependent, the most useful information
to the digital designers is the value averaged across a switching transition.
This is the Csb or Cdb value that was presented in Section 2.3.1. Analog
designers must minimize the consequences of these variations by using
good circuit design. 72
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Detailed MOS Diffusion Capacitance Models – Summary

 Diffusion regions were historically
used for short wires called runners
in processes with limited numbers
of metal levels.
 Diffusion capacitance are large
enough that such practice is now
discouraged.

Summary
 A MOS transistor can be viewed as a four-terminal device with
capacitances between each terminal pair as shown in Fig. 2.14.
 The gate capacitance includes an intrinsic component (to the
body, source and drain, or source alone, depending on
operating regime) and overlap terms with the source and drain.
 The source and drain have parasitic diffusion capacitance to the
body. 73
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Y. Hu’s Voltage Reference [2003]

74