CMOS Fabrication and Layout Rules

|| Jai Sri Gurudev ||
Sri Adichunchanagiri Shikshana Trust

(R)
SJB Institute of Technology

Department of Electronics & Communication Engineering
VLSI Design – 18EC72

MODULE - 2
By
Chetana R
Assistant Professor
Dept of ECE, SJBIT
02/19/202 Chetana R, Assistant Professor, Dept of ECE, SJBIT 1
3
Module-2
Fabrication: CMOS Fabrication and Layout, VLSI Design Flow, Introduction, CMOS Technologies, Layout
Design Rules, (1.5 and 3.1 to 3.3 of TEXT2).
MOSFET Scaling and Small-Geometry Effects, MOSFET Capacitances (3.5 to 3.6 of TEXT1)

TEXT BOOKS:
1. “CMOS Digital Integrated Circuits: Analysis and Design” - Sung Mo Kang & Yosuf Leblebici, Third
Edition, Tata McGraw-Hill.
2. “CMOS VLSI Design- A Circuits and Systems Perspective”- Neil H. E. Weste, and David Money Harris4th
Edition, Pearson Education.

REFERENCE BOOKS:
1. Adel Sedra and K. C. Smith, “Microelectronics Circuits Theory and Applications”, 6th or 7th Edition,
Oxford University Press, International Version, 2009.
2. Douglas A Pucknell & Kamran Eshragian, “Basic VLSI Design”, PHI 3rd Edition, (original Edition –
1994).
3. Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, TMH, 2007.
02/19/20
23
Chetana R, Assistant Professor, Dept of ECE, SJBIT 2
Fabrication: CMOS Fabrication and Layout, VLSI
Design Flow, Introduction, CMOS Technologies,
Layout Design Rules, (1.5 and 3.1 to 3.3 of TEXT2).

23
CMOS Fabrication and Layout
• Transistors are fabricated on thin silicon wafers called the

substrate.
• We can examine the physical layout of transistors from
two perspectives. One is the top view, obtained by looking
down on a wafer and the other is the cross-section,
obtained by slicing the wafer in the middle.
• We then define a set of masks used to manufacture the
different parts of the inverter.
• The size of the transistors and wires is set by the mask
dimensions.

23
Inverter Cross-Section
• The cross-section of an inverter

is seen built on a p-type
substrate.
• The pMOS transistor requires an
n-type body region, so an n-well
is diffused into the substrate.
• The nMOS transistor has heavily
doped n-type source and drain
regions and a polysilicon gate
over a thin layer of silicon
dioxide (SiO2, also called gate
oxide).

23
• pMOS has p-type source and drain
regions.
• Gates of the 2 transistors form the input
A.
• The source of the nMOS transistor is
connected to ground line and the source
of the pMOS transistor is connected to
VDD line.
• The drains of the 2 transistors are
connected to form the output Y.
• A thick layer of SiO2 called field oxide
prevents metal from shorting to other
layers except.

23
• The substrate must be tied to a low
potential to avoid forward-biasing the
p-n junction between the p-type
substrate and the n+ nMOS source or
drain.
• Likewise, the n-well must be tied to a
high potential.

23
Fabrication Process
• The fabrication sequence consists of a series of steps and

are defined through a process called photolithography.
• Smaller transistors are faster because electrons don’t have
to travel
• The inverter could be defined by a set of six masks: n-
well, polysilicon, n+ diffusion, p+ diffusion, contacts, and
metal.
• Figure shows a top view of the six masks.

23
23
• The process begins with the creation of an n-well on a
bare p-type silicon wafer.
• Figure (a) illustrates the bare substrate before processing.
• N-well is formed by adding Group V
dopants(phosporous)into the silicon substrate to change
the substrate from p-type to n-type.
• To define what regions receive n-wells, grow a protective
layer of oxide over the entire wafer, then remove it where
the wells are required.
• Then add the ntype dopants.

23
• The wafer is first oxidized at high-temperature
(typically 900–1200 °C) causing Si and O2 to react
and become SiO2 (Figure b).
• The oxide must be patterned to define the n-well.
• An organic photoresist that softens where exposed
to light is spun onto the wafer (Figure c).
• The softened photoresist is removed to expose the
oxide (Figure d).

23
• The oxide is etched with hydrofluoric acid (HF) where it
is not protected by the photoresist
• The well is formed where the substrate is not covered with
oxide.
• Two ways to add dopants are diffusion and ion
implantation.
• In the diffusion process, the wafer is placed in a furnace
with a gas containing the dopants. When heated, dopant
atoms diffuse into the substrate.
• With ion implantation, dopant ions are accelerated
through an electric field and blasted into the substrate. In
either method, the oxide layer prevents dopant atoms.
23
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• The transistor gates are formed consisting of polycrystalline silicon,
generally called polysilicon.
• The wafer is placed in a reactor with silane gas (SiH4) and heated for
polysilicon layer deposition by chemical vapor deposition.
• The n+ regions are introduced.
• For well, a protective layer of oxide is formed Figure c and patterned
with the n-diffusion mask Figure d.
• The n+ regions in Figure e are typically formed with ion implantation,
and called n-diffusion.
• Notice that the polysilicon gate over the nMOS transistor blocks the
diffusion
• This is called a self-aligned process because the source and drain of
the transistor are automatically formed adjacent to the gate.

23
• The process is repeated for the p-diffusion mask.
• The field oxide is grown to insulate the wafer.
• Finally, aluminum is sputtered filling the contact
• Sputtering involves blasting aluminum into a
vapor that evenly coats the wafer.
• The metal is patterned with the metal mask and
plasma etched to remove extra metal
• This completes the simple fabrication process.

23
23
Layout Design Rules
• Layout design rules describe how small features can be and in

Industry design rules are usually specified in microns.
• A single parameter, λ is considered
• This length is the distance between the source and drain of a
transistor and is set by the minimum width of a polysilicon
wire.
• For example, a 180 nm process has a minimum polysilicon
width (and hence transistor length) of 0.18 µm and uses design
rules with λ = 0.09 µm.
• The design rules are considered in terms of λ .
• Designers often describe a process by its feature size. Feature
size refers to minimum transistor length.

23
• The MOSIS rules are expressed in terms of λ.
• MOSIS service is a low-cost prototyping service that modifies designs.
• The rules describe the minimum width to avoid breaks in a line, minimum spacing
to avoid shorts between lines, and minimum overlap to ensure that two layers
completely overlap.
Easy-to-use set of design rules for layouts with two metal layers in an n-well process
is as follows:
• Metal and diffusion have minimum width and spacing of 4 λ .

• Contacts are 2 λ × 2 λ and must be surrounded by 1 λ on the layers above and
below.
• Polysilicon uses a width of 2 λ .
• Polysilicon overlaps diffusion by 2 λ where a transistor is desired and has a
spacing of 1 λ away where no transistor is desired.
• Polysilicon and contacts have a spacing of 3 λ from other polysilicon or contacts.
• N-well surrounds pMOS transistors by 6 λ and avoids nMOS transistors by 6 λ.
23
• Transistor dimensions are often
specified by their Width/Length (W/L)
ratio.
• For example, the nMOS transistor
formed where polysilicon crosses n-
diffusion has a W/L of 4/2.
• pMOS transistors are often wider than
nMOS transistors because holes move
more slowly than electrons so the
transistor has to be wider to deliver the
same current

23
Basic MOSIS design rules
Figure shows the for a process with two metal layers.

23
Figure (a) shows a unit inverter
layout with a unit nMOS transistor
and a double-sized pMOS transistor.
Figure (b) shows a schematic with
Width/ Length for each transistor.
Transistors are typically chosen with
short-channel because they are
faster, smaller, and consume less
power.
Figure (c) shows a shorthand we will
often use, specifying multiples of
unit width and assuming minimum
length.
23
Gate Layouts
• Figure (a) shows layout for an
inverter. The input A can be
connected from the top, bottom,
or left in polysilicon.
• The output Y is available at the
right side of the cell in metal.
• Recall that the p-substrate and n-
well must be tied to ground and
power, respectively.
• Figure (b) shows the same
inverter with well and substrate
taps placed under the power and
ground rails, respectively.

23
• Figure shows a 3-input
NAND gate.
• nMOS transistors are
connected in series while
the pMOS transistors are
connected in parallel.
• All these examples use
transistors of width 4 λ .

23
It is easy to estimate the area of a layout from the corresponding stick diagram even though
the diagram is not to scale.
If our wires have a width of 4 λ and a spacing of 4λ to the next wire, the track pitch is 8 λ, as
shown in Figure a.
This pitch also leaves room for a transistor to be placed between the wires Figure b.
Therefore, it is reasonable to estimate the height and width of a cell by counting the number
of metal tracks and multiplying by 8 λ
Pitch of routing tracks

23
Figure shows how to count tracks to estimate the size of a 3-
input NAND. There are four vertical wire tracks, multiplied
by 8 λ per track to give a cell width of 32λ. There are five
horizontal tracks, giving a cell height of 40 λ. Even though
the horizontal tracks are not drawn to scale, they are still
easy to count.
3-input NAND gate area estimation

23
Sketch a stick diagram for a CMOS gate and estimate the cell width and height.

23
Well Rules
• The n-well is usually a deep n-well and so sufficient

clearance between the n-well edges and the adjacent n+
diffusions should be provided.
• Being able to place nMOS and pMOS transistors closer
together can significantly reduce the size of SRAM cells.
• Because the n-well sheet resistance can be several kΩ per
square, it is necessary to ground the well thoroughly by
providing a sufficient number of well taps.
• This will prevent excessive voltage drops due to well
currents.

23
Transistor Rules
• CMOS transistors are generally defined by at least four physical
masks.
• These are active (also called diffusion, diff, thinox, OD, or RX),
n-select (also called n-implant, nimp, or nplus)
p-select (also called p-implant, pimp, or pplus)
polysilicon (also called poly, polyg, PO, or PC).
• The active mask defines areas where n- or ptype diffusion is to be
placed or the gates of transistors are to be placed.
• n-diffusion areas inside p-well regions define nMOS transistors.
• n-diffusion areas inside n-well regions define n-well contacts.
• Likewise, p-diffusion areas inside n-wells define pMOS transistors
• p-diffusion areas inside p-wells define substrate contacts.
• Hence, poly is required to extend beyond the edges of the active area.
This is often termed the gate extension.
23
Contact Rules
• Available contacts are:
Metal to p-active (p-diffusion)
Metal to n-active (n-diffusion)
Metal to polysilicon
Metal to well or substrate
• Other contacts such as buried polysilicon-active
contacts may be allowed for local interconnect.
• Each isolated well must be tied to supply voltage;
i.e. n-well must be tied to VDD
substrate or p-well to GND.
23
CMOS n-well process transistor
and well/substrate contact
construction

23
Metal
Rules
• Metal spacing may vary with the
width of the metal line
• That is, single metal wires cannot
be greater than a certain width.
• Nevertheless, width and spacing are
still greater for thicker metal layers.

23
Via Rules
• Vias are normally of uniform size

within a layer.
• They may increase in size toward the
top of a metal stack.
• For instance, large vias required on
power buses are constructed from an
array of uniformly sized vias.
23
MOSIS Scalable CMOS Design
Rules
• Most project designs often use the λ

based CMOS design rules from MOSIS
because they are simple and freely
available.
• MOSIS once offered a wide variety of
processes, from 2 µm to 180 nm.

23
Micron Design Rules
Table below lists a set of micron design rules for a 65 nm process.
The rules differ slightly from lambda based rules with λ= 0.035 µm.
Note that upper level metal rules are highly variable depending on the metal thickness; thicker
wires require greater widths and spacings and bigger vias.

23
MOSFET Scaling and Small-Geometry Effects,
MOSFET Capacitances (3.5 to 3.6 of TEXT1)

23
• The design of high-density chips in MOS VLSI is high so the sizes of the
transistors are as small as possible.
• The reduction of the size, i.e., the dimensions of MOSFETs, is commonly
referred to as scaling.
• The operational characteristics of the MOS transistor will change with the
reduction of its dimensions and their physical limitations.
• There are two basic types of size-reduction strategies: full scaling (also called
constant-field scaling) and constant voltage scaling.
• We will examine the scaling strategies and their effects and will consider physical
limitations and small-geometry effects.
• Scaling is reduction of overall dimensions of devices, preserving the geometric
ratios.
• Scaling would result in reduction of total silicon area, thereby increasing the
overall functional density of the chip.
• A constant scaling factor S > 1 is considered.

23
23
Scaling of a typical MOSFET by a
scaling factor of S

23
Full Scaling (Constant-Field Scaling)
• This attempts to preserve the magnitude of internal electric fields in the MOSFET, while
the dimensions are scaled down by a factor of S.
• Table below lists the scaling factors for all significant dimensions, potentials, and doping
densities of the MOS transistor.

23
• The gate oxide capacitance per unit area, on the other hand, is
changed.
• The aspect ratio WIL of the MOSFET will remain unchanged under
scaling.
• Transconductance parameter kn will also be scaled by a factor of S.
• Terminal voltages are scaled down by the factor S
• The linear-mode drain current of the scaled MOSFET is found as:

23
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Similarly, the saturation-mode drain current is also
reduced by the same scaling factor.

23
Power
Full scaling reduces both the drain current and the drain-to-source voltage by a factor of S;
hence, the power dissipation of the transistor will be reduced by the factor s2 .

23
• Certain voltage levels for all input and output voltages, would necessitate multiple
power supply voltages and complicated level shifter arrangements.
• For these reasons, constant-voltage scaling is usually preferred over full scaling.
• In constant-voltage scaling, all dimensions are reduced by a factor S. So the
power supply voltage and terminal voltages, on the other hand, remain unchanged.
• Table shows the constant-voltage scaling of key dimensions, voltages, and
densities.
• The gate oxide capacitance per unit area Cox is increased by a factor of S. Since
the terminal voltages remain unchanged, the linear mode drain current of the
scaled MOSFET is:

23
Constant-voltage scaling of MOSFET dimensions,
potentials, and doping densities
The saturation-mode drain current will be increased by a factor of S

23
Power dissipation. Since the drain current is increased by a factor of S
while the drain-to-source voltage remains unchanged, the power
dissipation of the MOSFET increases by a factor of S.

23
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23
Short-Channel Effects
• A MOS transistor is called a short-channel device if channel length

is same as the depletion region thicknesses of source and drain
junctions.
• The short-channel effects that arise in this case are attributed to two
physical phenomena:
 the limitations imposed on electron drift characteristics in the channel
 the modification of the threshold voltage due to the shortening channel
length.
• The lateral electric field Ey along the channel increases, as the
effective channel length is decreased.
• The electron drift velocity Vd in the channel is proportional to the
electric field for lower field values but drift velocity tends to
saturate at high channel electric fields.

23
The effective channel length Lef will be reduced due
to channel-length shortening.

23
• In short-channel MOS transistors, the vertical field
influences the scattering of carriers (collisions
suffered by the carriers) in the surface region, the
surface mobility is reduced with respect to the bulk
mobility.
• The dependence of the surface electron mobility
on the vertical electric field is as follows:

23
where µno is the low-field surface electron mobility
and theta is an empirical factor.
For a simple estimation of field-related mobility
reduction, can be approximated by
where η is also an empirical coefficient.

23
• We consider the modification of the threshold
voltage due to short-channel effects.
• The shape of this gate-induced bulk (channel)
depletion region was assumed to be rectangular,
extending from the source to the drain.
• The threshold value for long channel is given by

23
• Figure shows the simplified geometry of the gate-
induced bulk depletion region and the pn-junction
depletion regions in a short-channel MOS
transistor.

23
• The bulk depletion region is asymmetric
trapezoidal shape, instead of a rectangular
shape because of gate-induced charge.
• The drain depletion region is larger than the
source depletion region because the positive
drain-to-source voltage reverse-biases the
drain-substrate junction.

23
• Since the bulk depletion charge in the short-channel
device is smaller, the threshold voltage expression must be
modified
• where VT0 is the zero-bias threshold voltage calculated

using the conventional long channel and ΔV0 is the
threshold voltage shift (reduction) due to the short-
channel effect.
• The reduction represents the amount of charge differential
between a rectangular depletion region and a trapezoidal
depletion
02/19/20
23
region.
Chetana R, Assistant Professor, Dept of ECE, SJBIT 56
23
23
23
23
Consider the n-channel MOSFET process given in previous problem. In several digital
circuit
applications, the condition VSB = 0 cannot be guaranteed for all transistors. We will examine
in this example how a nonzero source-to-substrate voltage VSB affects the threshold voltage
of the MOS transistor.
Calculate the substrate-bias coefficient using the process parameters given
The voltage VSB will be assumed to vary between zero and 5 V.
It is seen that the threshold voltage variation is about 1.3 V over this range, which
could present serious design problems if neglected

23
23
First, we have to find the zero-bias threshold voltage using the conventional
formula
(3.23). The threshold voltage without the channel implant was already calculated
for the
same process parameters in Example 3.2, and was found to be V. = 0.40 V. The
additional p-type channel implant will increase the threshold voltage by an
amount of qN,
I Cx. Thus, we find the long-channel zero-bias threshold voltage for the process
described above as
The threshold voltage without the channel implant was already calculated for
the same process parameters and was found to be V. = 0.40 V.

23
Short-Channel Effects
• MOS transistor is called a short-channel device if its channel length is of

magnitude as the depletion region thicknesses.
• MOSFET can be defined as a short-channel device if the effective channel length
Leff is approximately equal to the source and drain junction depth x.
• The short-channel effects that arise in this case are attributed to two physical
phenomena
the limitations imposed on electron drift characteristics in the channel,
the modification of the threshold voltage due to the shortening channel length.
Note that the lateral electric field EY along the channel increases, as the effective
channel length is decreased.
The effective channel length L eff will be reduced due to channel-length shortening.

23
• In short-channel MOS transistors, the carrier velocity in
the channel is a function of the electric-field and the
surface mobility is reduced with respect to the bulk
mobility.
• The dependence of the surface electron mobility on the
vertical electric field can be expressed by the following
empirical formula

23

CMOS Fabrication and Layout Rules

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|| Jai Sri Gurudev ||

Sri Adichunchanagiri Shikshana Trust

SJB Institute of Technology

VLSI Design – 18EC72

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 3

• Transistors are fabricated on thin silicon wafers called the

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 4

• The cross-section of an inverter

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 5

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 6

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 7

• The fabrication sequence consists of a series of steps and

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 8

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 10

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 11

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 14

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 15

• Layout design rules describe how small features can be and in

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 17

• Metal and diffusion have minimum width and spacing of 4 λ .

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 19

Figure shows the for a process with two metal layers.

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 20

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 22

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 23

Pitch of routing tracks

3-input NAND gate area estimation

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 25

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 26

• The n-well is usually a deep n-well and so sufficient

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 27

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 30

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 31

• Vias are normally of uniform size

• Most project designs often use the λ

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 33

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 34

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 35

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 36

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 38

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 39

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 40

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 42

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 43

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 44

The saturation-mode drain current will be increased by a factor of S

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 45

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 46

• A MOS transistor is called a short-channel device if channel length

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 49

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 50

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 51

where η is also an empirical coefficient.

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 53

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 54

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 55

• where VT0 is the zero-bias threshold voltage calculated

The voltage VSB will be assumed to vary between zero and 5 V.

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 61

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 63

• MOS transistor is called a short-channel device if its channel length is of

02/19/20 Chetana R, Assistant Professor, Dept of ECE, SJBIT 64