VLSI DESIGN

MEL ZG621
Lecture-5
26-08-2023
Dr. Vilas H Gaidhane
vhgaidhane@dubai.bits-pilani.ac.in
BITS Pilani
Dubai Campus
 Lecture 5
Module 1 Module 2

1. MOS Inverters 1. Delay Calculations

2. CMOS Inverter

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 Resistive Load MOS Inverter
➢Enhancement-type n-MOS transistor acts as the
driver device.
➢The load consists of a simple linear resistor, RL.
Case I: For input voltages smaller than the
threshold voltage VTO the transistor is in cut-off,
and does not conduct any drain current. I D = I R = 0

Case II: Input voltage increase beyond VTO .

Note that driver transistor initially will be
saturation as Vout = VDS  VGS − VTO
k
I D = I R = n (Vin − VTO )
2
2
where VGS = Vin and kn = n Cox (W / L )
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 Resistive Load MOS Inverter
Case III: Further increase in input voltage the
drain current of the driver also increases, and the output
voltage starts to drop.
Vout = VDS  VGS − VTO
kn
ID = IR =  2 (Vin − VTO )Vout − Vout 2 
2  

Operation of driver transistor is summarized in

Table

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 Resistive Load MOS Inverter
1. Calculation of VOH

Vout = VDD − I R RL
For Vin  VTO Transistor will be
in cut-off region
ID = IR = 0
Vout = VDD = VOH
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 Resistive Load MOS Inverter
For Vin = VOH = VDD >VDS Transistor will be in linear region

2. Calculation of VOL VDD − Vout

ID = IR = and
RL
kn
ID =  2 (Vin − VTO )Vout − Vout 2 
2  
VDD − Vout kn
=  2 (Vin − VTO )Vout − Vout 2 
RL 2  
VDD − VOL kn
=  2 (VDD − VTO )VOL − VOL 2 
RL 2  
 1  2
VOL 2 − 2  VDD − VTO +  VOL + =0
 k n L 
R k R
n L
2
1  1  2VDD
VOL = VDD − VTO + −  VDD − VTO +  −
kn RL  k n RL  kn RL

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 Resistive Load MOS Inverter
3. Calculation of VIL
At VIL , VTC become equal to -1
Vout  Vin - VTO Transistor will be in saturation region
VDD − Vout
ID = IR = and
RL
VDD − Vout k
= n (Vin − VTO ) Differentiate both side
2
RL 2
with respect to Vin
1 dVout
− = kn (Vin − VTO )
RL dVin
1
− (-1) = kn (VIL − VTO )
RL
1
VIL = VTO +
kn RL

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 Resistive Load MOS Inverter
4. Calculation of VIH
VIH is the larger of the two voltage points on VTC at which the slope is equal to (-1).

At VIH , VTC become equal to -1

Vout  Vin - VTO Transistor will be in linear region
VDD − Vout
ID = IR = and
RL
VDD − Vout k
= n  2 (Vin − VTO ) Vout − Vout 2  Differentiate both side
RL 2  
with respect to Vin
1 dVout k  dV dVout 
− = n  2 (Vin − VTO ) out + 2Vout − 2Vout 
RL dVin 2  dVin dVin 
1
− (-1) = kn (VIH − VTO ) (-1) + 2Vout 
RL
1
VIH = VTO + 2Vout −
kn RL
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 Resistive Load MOS Inverter
VTC Curve for Resistive
load Inverter.

k n RL is a design parameter
which can be adjusted by the
circuit designer to achieve the
certain design goals.

For larger k n RL value VoL

become smaller and it
approaches to the ideal
inverter

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 ResistiveLoad n-MOS Inverter
➢Design of Resistive load nMOS inverter

Sample layout of resistive-load inverter circuits with (a) diffused resistor and (b)
undoped polysilicon resistor.
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 Resistive Load n-MOS Inverter
➢Power Consumption of Resistive load nMOS inverter

VDD − VOL
ID = IR =
RL

➢Assuming input voltage is low during 50% of operation time and high
during another 50% of time. The average DC Power

VDD VDD − VOL

PDC ( average ) =
2 RL

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 Enhancement Load MOS Inverter
➢Depending on the bias voltage applied to its gate terminal, the load
transistor can be operated either in the saturation or linear region.
➢The saturated enhancement-load inverter shown in Fig. (a) requires a
single voltage supply and a relatively simple fabrication process

➢The load device of the

inverter circuit shown in Fig.
(b), is always biased in the
linear region, but requires
two power supply.
➢Both has high DC power
dissipation.
➢Generally not used
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 Depletion Load nMOS Inverter

VTo ,load  0 (Negative)

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 Depletion Load nMOS Inverter
➢Depletion load nMOS inverter is same as
the enhancement type but more fabrication
steps may be required specially for channel
formation.
Advantages:
(i) sharp VTC transition and better noise
margins,
(ii) single power supply, and
(iii) smaller overall layout area.
When Vout  VDD + VT ,load (Linear)
When Vout  VDD + VT ,load (Saturation)
Corresponds to VDS ,load  VGS ,load − VT ,load (Saturation)

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7-Jan-18 MEL ZG621 VLSI Design 14
 Depletion Load nMOS Inverter

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 Depletion Load nMOS Inverter
➢Calculation of VOH (load device operate in linear region)
When the input voltage Vin is smaller than the driver threshold voltage VTO
the driver transistor is turned off and does not conduct any drain current.
I D ,load = 0 Therefore VOH = VDD

In saturation mod e
kn ,load
0 − VT ,load (Vout ) 
2
I D ,load =  
2 
kn ,load
VT ,load (Vout )
2
=
2
In Linear mod e
kn ,load 
2 VT ,load (Vout ) (VDD − Vout ) − (VDD − Vout ) 
2
I D ,load =
2  

7-Jan-18
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 Depletion Load nMOS Inverter
➢Calculation of VOL
To calculate the output low voltage VOL we assume that the input voltage
of the inverter is equal to VOH = VDD.
The driver transistor operates in the linear region while the depletion-
type load is in saturation.
kdriver k
 2 (VOH − VTO )VOL − V 2  = load  −VT ,load (VOL ) 
2

2  OL  2  
This second-order equation in VOL can be solved

 kload 
(VOH − VTO )   VT ,load (VOL )
2 2
VOL = VOH − VTO − −
 kdriver 
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 Depletion Load nMOS Inverter
➢Calculation of VIL dV0
By definition, the slope of the VTC is equal to (-1),.
= −1
dVin
The driver transistor operates in saturation while the load transistor
operates in the linear region.

kdriver
(Vin − VTO ) 2
2
kload  2
= 2 VT ,load (Vout ) (VDD − Vout ) − (VDD − Vout )
2   

Differentiate with respect to Vin

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 Depletion Load nMOS Inverter
➢Calculation of VIL
kload   dVout  
kdriver (Vin − VTO ) =  2 VT ,load (Vout )  −  +
2   dVin  
 dVT ,load   dVout 
2 (VDD − Vout )  −  − 2 (VDD − Vout )  − 
 dV in   dVin 

dVT ,load
Assume that the term is negligible with respect to the others.
dVin
dVout
Substitute Vin = VIL and = −1 we can obtain the
dVin
 kload 
VIL = VTO +    Vout − VDD + VT ,load (Vout ) 
 kdriver 
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MEL ZG621 VLSI Design 19
 Depletion Load nMOS Inverter
➢Calculation of VIH : At this input the slope is -1. The driver
transistor is in the linear region and load transistor is in saturation
kdriver kload
 2 (Vin − VTO )Vout − Vout  −VT ,load (Vout ) 
2  2
=
2   2
Differentiate both side with respect to Vin
  dVout   dVout  
kdriver Vout + (Vin − VTO )   − Vout  
  dVin   dVin  
 dVT ,load   dVout 
= kload  −VT ,load (Vout )     
 dVout   dVin 
 kload   dVT ,load 
VIH = VTO + 2Vout +   .  −VT ,load (Vout )  . 
 driver 
k  dV out 
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 CMOS Inverter
➢Complementary MOS (CMOS) is consist of PMOS and NMOS connected
to a common input signal and operating in a complementary mode
hence called as complementary MOS.
➢Circuit topology is push-pull in
the sense that for high input, the
nMOS transistor drives (pulls
down) the output node
➢For low input the pMOS
transistor drives (pulls up) the
output node
➢both devices contribute equally
to the circuit operation
characteristics

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 CMOS Inverter

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 CMOS Inverter
➢Advantages:
1. The steady-state power dissipation of the CMOS inverter circuit is
negligible, except for small power dissipation due to leakage
currents.
2. voltage transfer characteristic (VTC) exhibits a full output voltage
swing between 0 V and VDD, and that the VTC transition is usually
very sharp. It is closed to Ideal characteristics

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 CMOS Inverter

VGS ,n = Vin
VDS ,n = Vout
and
VGS , p = − (VDD − Vin )
VDS , p = − (VDD − Vout )

nMOS transistor operates in Saturation when

VDS ,n  VGS ,n − VTO ,n  Vout  Vin − VTO ,n
and pMOS transistor operates in saturation
VDS , p  VGS , p − VTO , p  Vout  Vin − VTO , p

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 CMOS Inverter

Case1: When Vin  VTO ,n

nMOS is cut-off and pMOS is
on operating in the linear region.
I D ,n = I D , p = 0
Vout = VOH = VDD

(
Case 2: When Vin voltage exceeds VDD + VTO , p )
pMOS is cut-off and nMOS is
on operating in the linear region.
I D ,n = I D , p = 0
Vout = VOL = 0

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 CMOS Inverter

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 CMOS Inverter
➢Calculation of VIL
➢By definition, the slope of the VTC is equal to (-1), i.e.,
dVout
= −1
dVin
when the input voltage is. Vin = VIL
➢nMOS transistor operates in saturation while the pMOS transistor
operates in the linear region.

I D ,n = I D , p

( )
kp
( )
kn 2
 2 VGS , p − VTO , p VDS , p − VDS 
VGS ,n − VTO ,n = 2
2  
, p
2

( )
kp 
( )
kn 2
2 Vin − VDD − VTO , p (Vout − VDD ) − (Vout − VDD )
2
Vin − VTO ,n =
2 2 
 
Now differentiate the equation with respect to Vin

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 CMOS Inverter
➢Calculation of VIL
Now differentiate the equation with respect to Vin
 dVout 
( ) (
kn Vin − VTO ,n = k p  Vin − VDD − VTO , p  )
dVout
+ (Vout − VDD ) − (Vout − VDD ) 
 dV in dV in 
dVout
Substitute Vin = VIL and = −1
dVin

( ) ( )
kn VIL − VTO ,n = k p  VIL − VDD − VTO , p  ( −1) + (Vout − VDD ) − (Vout − VDD )( −1) 
 
kn (VIL − VTO ,n ) = k p ( 2Vout − VIL + VTO , p − VDD )
2Vout + VTO , p − VDD + k RVTO ,n
VIL =
1 + kR
kn
where k R =
kp
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 CMOS Inverter
➢Calculation of VIH
When input is VIH , nMOS operates in linear region and pMOS operates saturation

(VGS , p − VTO , p )
kp
( )
kn 2
 2 VGS ,n − VTO ,n VDS ,n − VDS
2 =
2  
,n
2

(Vin − VDD − VTO , p )

kp
( )
kn 2
 2 VGS ,n − VTO ,n VDS ,n − VDS
2 
,n  =
2  2
Differentiate with respect to Vin
 dVout   dVout 
(
kn Vin − VTO ,n )   + Vout − Vout  (
 = k p Vin − VDD − VTO , p )
 dVin   dVin 
( ) (
kn VIH − VTO ,n  ( −1) + Vout − Vout ( −1) = k p VIH − VDD − VTO , p )
VIH =
(
VDD + VTO , p + k R 2Vout + VTO ,n )
1 + kR
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 Design of CMOS Inverter
 kn 
For symmetric inverter kn = k p therefore k R =   =1
 kp  symmetric
 
inverter

W  W 
n Cox    n 
kn  L n  L n
= =
kp W  W 
 p Cox   p  
 L p  L p
W 
 L 
 n  p 230cm / V  s
2
= 
W  n 580cm2 / V  s
 L 
 p
W  W 
 L  2. 5  L
 p  n
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 Design of CMOS Inverter
For symmetric inverter
1
(
VIL = 3VDD + 2VTO ,n
8
) and

1
(
VIH = 5VDD − 2VTO ,n
8
)
and
VIL + VIH = VDD
Noise margin
NM L = VIL − VOL = VIL
NM H = VOH − VVIH = VDD − VVIH

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 Design of CMOS Inverter
Consider a CMOS inverter circuit with the following parameters:
VDD = 3.3V
VTO ,n = 0.6V
VTO , p = −0.7V
kn = 200 A / V 2
k p = 80 A / V 2
Calculate the noise margins of the circuit.

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