SECOND ORDER EFFECTS

Channel length modulation

Threshold voltage (body effect)
Sub threshold region
Mobility variation
Fower-Nordheim Tunneling
Drain punchthrogh
Hot electrons
 Channel Length Modulation
• In saturation, pinch-off point moves
– As VDS is increased, pinch-off point moves
closer to source
– Effective channel length becomes shorter
– Current increases due to shorter channel
L  L  L
'

W
I D   nCox VGS  VTN  1  VDS 
1 2
2
L
 = channel length modulation coefficient
threshold voltage

source-to-body substrate bias

surface potential

threshold voltage for zero substrate

body effect parameter

oxide thickness

oxide permitivity
permitivity of silicon

doping concentration

charge of an electron
Sub threshold region
 Subthreshold current

Subtreshold
region

As VG increases, the surface

potential will increase.

There is very little majority carriers

underneath the gate.

There are two pn junctions. (B-S and B-D)

The density of the minority carrier
depends on the difference in the
voltage across the two pn junction diode.
A diffusion current will result the electron densities
at D and S are not identical.
Mobility variation
Fower-Nordheim Tunneling
 Drain Punchthrough
• Punch through in a MOSFET is an extreme case of
channel length modulation where the depletion layers
around the drain and source regions merge into a
single depletion region. The field underneath the gate
then becomes strongly dependent on the drain-source
voltage, as is the drain current. Punch through causes
a rapidly increasing current with increasing drain-
source voltage. This effect is undesirable as it
increases the output conductance and limits the
maximum operating voltage of the device
• Hot electrons
– High-velocity electrons can also impact the
drain, dislodging holes
– Holes are swept towards negatively-charged
substrate → cause substrate current
– Called impact ionization
– This is another factor which limits the process
scaling → voltage must scale down as length
scales
CMOS INVERTER – Lecture 1

•Regions of Operation
•Noise margin
•Inverter capacitances
•Delay, Rise and Fall time
 CMOS Inverter
• Complementary NMOS and PMOS
devices VDD
• In steady-state, only one device is on
(no static power consumption)
• Vin=1: NMOS on, PMOS off Vin Vout
– Vout = VOL = 0
• Vin=0: PMOS on, NMOS off
– Vout = VOH = VDD
Gnd

12
 CMOS Inverter: VTC
PMOS NMOS
Vin=4V
Drain current IDS

VDD
Vin=3V

Vout
Vin=2V

Vin=1V

Vout = VDS VDD 0 1 2 Vin 3 4

• Output goes completely to VDD and Gnd

• Sharp transition region

13
 CMOS inverter operation
VDD
• NMOS transistor:
– Cutoff if Vin < VTN
Vin Vout
– Linear if Vout < Vin – VTN
– Saturated if Vout > Vin – VTN
• PMOS transistor
– Cutoff if (Vin-VDD) < VTP → Vin < VDD+VTP
– Linear if (V -V )>V -V -V → V >V - V
out DD in DD TP out in TP

– Sat. if (Vout-VDD)<Vin-VDD-VTP → Vout < Vin-VTP

14
 CMOS
P linear
inverter VTC
P cutoff
N cutoff N linear

P linear
N sat P sat
N sat

P sat
N linear

15
 CMOS inverter VTC
• Increase W of PMOS
VDD kp=kn
kp increases
VTC moves to right
kp=5kn • Increase W of NMOS
Vout
kn increases
kp=0.2kn
VTC moves to left
• For VTH = VDD/2
k n = kp
VDD Wn  2Wp
Vin

16
 Inverter model: VTC
Voltage transfer curve (VTC):
plot of output voltage Vout vs. input voltage Vin

Vin Inverter Vout

Ideal digital inverter:

– When Vin=0, Vout=VDD
VDD ideal – When Vin=VDD, Vout=0
– Sharp transition region

Vout
actual

VDD
Vin
17
 Actual inverter: Voltage Swing VOH and VOL
• VOH and VOL represent the “high” and
“low” output voltages of the inverter
• VOH = output voltage when Vin = ‘0’
• VOL = output voltage when Vin = ‘1’
VDD
VOH • Ideally,VOH = VDD,VOL = 0
• Difference (VOH-VOL) is the voltage swing of
the gate
Vout
– Full-swing logic swings
VOL from ground to VDD
VDD
Vin

18
Inverter threshold

Inverter switching threshold:

– Point where voltage transfer
curve intersects line Vout=Vin
VOH Vout=Vin
– Represents the point at which
the inverter switches state
Vout VTH – Normally, VTH  VDD/2

VOL
VDD
Vin

19
Inverter threshold
Both the transistors are in saturation
So….
Equating the Saturation current of both the PMOS and NMOS
If Kn=Kp
Vtn=|Vtp|

Vin= vdd/2 Best for equal noise margin

 Noise Margins

• VIL and VIH measure effect of

input voltage on inverter
VOH Slope = -1 output
• VIL = largest input voltage recognized
Vout as logic ‘0’
• VIH = smallest input voltage
recognized as logic ‘1’
VOL
VIL VIH VDD • Defined as point on VTC where slope
= -1
Vin

22
 Noise margin (cont)
• Noise margin is a measure of the
interconnect robustness of an inverter
– NML = VIL - VOL
– NMH = VOH - VIH
• Models a chain of inverters. Example:
“1”
VOH – First inverter output is VOH
NMH – Second inverter recognizes input > VIH as
VIH
logic ‘1’
VIL – Difference VOH-VIH is “safety zone” for
NML
VOL noise
“0”

Ideally, noise margin should be

as large as possible

23
AND LOGIC
Power Dissipation
Power dissipation in CMOS circuits
comes from two components:
Static Power

The static power dissipation is the

product of total leakage current and the
supply voltage.
Dynamic Power
CMOS inverter: capacitances
VDD
Cgs,p Csb,p

Cap on node f:

• Junction cap
Cdb,p and Cdb,n
Cgd,p Cdb,p
Vin f • Gate capacitance
Cgd,n Cdb,n Cgd,p and Cgd,n
Cint Cg
• Interconnect cap
• Receiver gate cap

Cgs,n Csb,n
Gnd
33
CMOS inverter: capacitances

• Junction capacitances Cdb,p and Cdb,n:

– Equation for junction cap m
AC j 0  q N a N d 1 
C j V   , C j 0   
 2 N a  N d 0 
m
 V
 1  
 0 

– Non-linear, depends on voltage across junction

– Use Keq factor to get equivalent capacitance for a
voltage transition
Cdb  AK eq C j  PK eqswC jsw
34
CMOS inverter: capacitances

• Gate capacitances CGD,p and CGD,n:

– In steady state, what regions are transistors in?
– One is in cutoff: CGD = CGS = 0
– One is in saturation: CGD = 0
– Therefore, gate-to-drain capacitance is only due
to overlap capacitance:
C gd , p  C gd ,n  CoxWLD

However, also need to consider Miller effect ...

35
CMOS inverter: capacitances
Cgd1
Vout Vout

Vin Vin 2Cgd1

• When input rises by V, output falls by V

– Effective voltage change across Cgd1 is 2V
– Effective capacitance to ground is twice Cgd1
• Including Miller effect:

C gd , p  C gd ,n  2CoxWLD

36
CMOS inverter: capacitances

• Interconnect capacitance
– Due to capacitance of metal and poly lines used to
connect transistors
– Complex; includes parallel-plate and fringing-field
components
– For wide wires:
 tox = thickness of field oxide
Cint  ox
WL
tox
Sample capacitances for 1m process:
poly: 0.058 fF/m2 M1: 0.031 fF/m2
M2: 0.015 fF/m2 M3: 0.010 fF/m2

37
Review: CMOS inverter capacitances

• Receiver gate capacitance

– Includes all capacitances of gate(s) connected to
output node
– Unknown region of operation for receiver
transistor: total gate cap varies from (2/3)WLCox to
WLCox
– Ignore Miller effect since operation unknown
– Assume worst-case value, include overlap

C g  WLeff Cox  2WLD Cox

38
 CMOS Transmission Gate
nMOS transistors good at passing 0's but bad at passing 1's

pMOS transistors good at passing 1's but bad at passing 0's

perfect "transmission" gate places these in parallel:

Control Control Control

In Out
In Out In Out

Control Control
Control

Switches Transistors Transmission or

"Butterfly" Gate
47
 Transmission Gates
• Pass transistors produce degraded outputs
• Transmission gates pass both 0 and 1 well
Input Output
g = 0, gb = 1 g = 1, gb = 0
g
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1
gb

g g g
a b a b a b
gb gb gb

Circuits and Layout Slide 48

 Selection/Demultiplexing

S
Selector: I
Choose I0 if S = 0 0
Choose I1 if S = 1 S
S Z

I
1
S

Z0
Demultiplexer:
I to Z0 if S = 0 S
I S
I to Z1 if S = 1
Z1
S
49
 Use of Multiplexers or Demultiplexers
A Y

Demultiplexers Multiplexers

B Z

A Y

Demultiplexers Multiplexers

B Z

So far, we've only seen point-to-point connections among gates

Mux/Demux used to implement multiple source/multiple destination

interconnect ECE C03 Lecture 4 50
Well-formed Switching Logic
Problem with the Demux implementation:
multiple outputs, but only one connected to the input!

Z0

"0"
I
S S

Z1

"0"

The fix: additional logic to drive every output to a known value

Never allow outputs to "float"

ECE C03 Lecture 4 51

 Use of Multiplexers/Selectors
Multi-point connections

A0 A1 B0 B1
Multiple input sources
Sa MUX MUX Sb

A B

Sum

Ss DEMUX Multiple output destinations

S0 S1
 General Concept of Using Multiplexers
n
2 data inputs, n control inputs, 1 output
n
used to connect 2 points to a single point

control signal pattern form binary index of input connected to output

Z = A' I 0 + A I 1
A Z I1 I0 A Z
0 I0 0 0 0 0
1 I1 0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
Functional form
1 0 1 1
Logical form 1 1 0 1
1 1 1 1

Two alternative forms

ECE C03 Lecture 4
for a 2:1 Mux Truth Table 53
 Use of Multiplexers/Selectors
I0
2:1
mux Z Z = A' I 0 + A I 1
I1

I0
I1
4:1 Z Z = A' B' I0 + A' B I1 + A B' I2 + A B I3
I2 mux
I3

A B

I0
I1
I2
I3
I4
8:1
Z Z = A' B' C' I0 + A' B' C I1 + A' B C' I2 + A' B C I3 +
mux
I5 A B' C' I4 + A B' C I5 + A B C' I6 + A B C I7
I6
I7 n
In general, Z =  2 -1m I
k=0 k k
A B C in minterm shorthand form for a 2 n:1 Mux
ECE C03 Lecture 4 54
 Alternative Implementation
A B

I0 Z

I1

I2

I3

Gate
GateLevel
Level Transmission
TransmissionGate
Gate
Implementation
Implementation Implementation
Implementationofof
ofof4:1
4:1Mux
Mux 4:1
4:1Mux
Mux

thirty six transistors twenty transistors

ECE C03 Lecture 4 55
 Design of Large Multiplexers
Large multiplexers can be implemented by cascaded smaller ones

I0 0 4:1 8:1 Control signals B and C simultaneously

I1 1 mux mux choose one of I0-I3 and I4-I7
I2 2
I3 3S S 0 2:1 Z Control signal A chooses which of the
1 0
mux upper or lower MUX's output to gate to Z
I4 1 S
0 4:1
I5 I0 0
1 mux
I6 2 I1 1 S
I7 3 S1 S0
C
I2 0
B C A 0
I3 1 S
1
Alternative 8:1 Mux Implementation C 2
Z
I4 0
3 S0 S1
I5 1 S

A B
C
I6 0
I7 1 S

ECE C03 Lecture 4 56

C
 Multiplexers/Selectors as General
n-1
2
Purpose Blocks
:1 multiplexer can implement any function of n variables

n-1 control variables; remaining variable is a data input to the mux

Example:
F(A,B,C) = m0 + m2 + m6 + m7
= A' B' C' + A' B C' + A B C' + A B C

= A' B' (C') + A' B (C') + A B' (0) + A B (1)

1 0 A B C F
0 1 0 0 0 1 C 0
1 C F
2 F 0 0 1 0 C 1 4:1
0 3 8:1 0
0 1 0 1 2 MUX
0 4 MUX C 1
0 0 1 1 0 3
5 S1 S0
1 6 1 0 0 0
0 A B
1 7 S2 S1 S0 1 0 1 0
1 1 0 1
A B C 1
1 1 1 1
"Lookup Table"
ECE C03 Lecture 4 57
 Generalization of Multiplexer/Selector Logic
I1 I2 … I F
n

… 0 0 0 1 1 Four possible
n-1 Mux 0 1 0 1 configurations
control variables 1 of the truth table rows
single Mux
data variable 0 In In 1 Can be expressed as
a function of In, 0, 1

Example:
G(A,B,C,D) can be implemented by an 8:1 MUX:
1 0
K-map D 1
Choose A,B,C 0 2
as control variables 8:1 G
1 3
D 4 mux
D 5
Multiplexer D 6
Implementation D 7 S2 S1 S0
TTL
TTLpackage
packageefficient
efficient A B C
May be gate inefficient
May be gate inefficient
ECE C03 Lecture 4 58
 Decoders/Demultiplexers
n
Decoder: single data input, n control inputs, 2 outputs

control inputs (called select S) represent Binary index of output to which

the input is connected

data input usually called "enable" (G)

1:2 Decoder: 3:8 Decoder:

O0 = G • S; O1 = G • S O0 = G • S0 • S1 • S2

O1 = G • S0 • S1 • S2
2:4 Decoder:
O0 = G • S0 • S1 O2 = G • S0 • S1 • S2

O1 = G • S0 • S1 O3 = G • S0 • S1 • S2

O2 = G • S0 • S1 O4 = G • S0 • S1 • S2

O3 = G • S0 • S1 O5 = G • S0 • S1 • S2

O6 = G • S0 • S1 • S2
ECE C03 Lecture 4 O7 = G • S0 • S1 • S2 59
 Alternative Implementations
G /G
Output0 Output0
Select
Select

Output1 Output1

1:2 Decoder, Active High Enable 1:2 Decoder, Active Low Enable

G /G
Output0 Output0

Output1 Output1

Output2 Output2

Output3 Output3

Select0 Select1 Select0 Select1

2:4 Decoder, Active High Enable 2:4 Decoder, Active Low Enable
ECE C03 Lecture 4 60
 Switch Level Implementations Select

Select G Output
0
G Output Select
0 Select
Select "0"
Select
Select
Output Select
1
Select Output
1
Select
Naive, Incorrect Implementation
Select
All outputs not driven at all times "0"
Select

Correct 1:2 Decoder Implementation

61
Switch Implementation of 2:4
Decoder
Select Select
0 1

G Output
0

"0" Operation of 2:4 Decoder

"0"
S0 = 0, S1 = 0
G Output
1
one straight thru path
"0"
three diagonal paths
"0"

G Output
2

"0"

"0"

G Output
3

"0"

"0"

62
Decoder as a Logic Building Block
0 ABC
1 ABC
2 ABC Decoder Generates Appropriate
Enb
3:8 3 ABC Minterm based on Control Signals
dec 4 ABC
5 ABC
6 ABC
S2 S1 S0 7 ABC

A B C

Example Function:
F1 = A' B C' D + A' B' C D + A B C D
F2 = A B C' D' + A B C
F3 = (A' + B' + C' + D')

ECE C03 Lecture 4 63

Decoder as a Logic Building Block
0 ABCD
1 ABCD
F1
2 ABCD
3 ABCD
4 ABCD
5 ABCD
Enb 6 ABCD
4:16
7 ABCD
dec
8 ABCD F2
9 ABCD
10 ABCD
11 ABCD
12 ABCD
13 ABCD
14 ABCD
F3
S3 S2 S1 S0 15 ABCD

A B C D
If active low enable, then use NAND gates!

ECE C03 Lecture 4 64

 D Latch
• When CLK = 1, latch is transparent
– D flows through to Q like a buffer
• When CLK = 0, the latch is opaque
– Q holds its old value independent of D
• a.k.a. transparent latch or level-sensitive latch
CLK CLK

D
Latch

D Q
Q

Circuits and Layout Slide 65

 D Latch Design
• Multiplexer chooses D or old Q
CLK
CLK
D Q Q
1
Q D Q
0
CLK CLK

CLK

Circuits and Layout Slide 66

 D Latch Operation
Q Q
D Q D Q

CLK = 1 CLK = 0

CLK

Circuits and Layout Slide 67

 D Flip-flop
• When CLK rises, D is copied to Q
• At all other times, Q holds its value
• a.k.a. positive edge-triggered flip-flop, master-
slave flip-flop
CLK
CLK
D
Flop

D Q
Q

Circuits and Layout Slide 68

 Transmission gate latches

Simplest implementation Basic static latch Complete implementation

S
D Q D Q D Q
S S
Clk Clk Clk

(a) (b) (c)

- only 4 transistors - pull-up/pull-down keeper - Feedback turned off when

-Dynamic when S=1 - Conflict at node S whenever writing to the latch
-Susceptible to noise new data is written - No conflict
- Larger clock load

Nov. 14, 2003 69

 Transmission Gate Master-Slave Latch
(MSL)
Clk Clk 1
Clk Clk 1
Q
SM QM SS
D

Clk 1 Clk

Master Transmission
Gate Latch Slave Transmission
Gate Latch
MSL with unprotected input
(Gerosa et al. 1994), Copyright © 1994 IEEE
Nov. 14, 2003 70